axi_tdl 0.0.12 → 0.1.3
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- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +4 -2
- data/.gitignore +3 -1
- data/README.EN.md +7 -2
- data/README.md +6 -2
- data/Rakefile +8 -1
- data/axi_tdl.gemspec +1 -2
- data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
- data/lib/axi/AXI4/axi4_direct_B1.sv +23 -23
- data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
- data/lib/axi/AXI4/axi4_dpram_cache.sv +34 -34
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +1 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +24 -24
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +33 -33
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +2 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +72 -72
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +2 -1
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +21 -21
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +7 -1
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +45 -40
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +6 -2
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +30 -30
- data/lib/axi/AXI_stream/axis_insert_copy.rb +18 -4
- data/lib/axi/AXI_stream/axis_insert_copy.sv +29 -16
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +9 -9
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +38 -38
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +30 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
- data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +26 -0
- data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +101 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +2 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +4 -4
- data/lib/axi/common/common_ram_sim_wrapper.sv +10 -10
- data/lib/axi/common/common_ram_wrapper.sv +13 -13
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +27 -27
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +72 -0
- data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +58 -0
- data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +64 -0
- data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +69 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +150 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.rb +69 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.sv +125 -0
- data/lib/axi_tdl.rb +1 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/public_atom_module/CheckPClock.sv +53 -0
- data/lib/public_atom_module/LICENSE.md +674 -0
- data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
- data/lib/public_atom_module/bits_decode.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
- data/lib/public_atom_module/broaden.v +43 -0
- data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
- data/lib/public_atom_module/ceiling.v +39 -0
- data/lib/public_atom_module/ceiling_A1.v +42 -0
- data/lib/public_atom_module/clock_rst.sv +64 -0
- data/lib/public_atom_module/cross_clk_sync.v +37 -0
- data/lib/public_atom_module/edge_generator.v +50 -0
- data/lib/public_atom_module/flooring.v +36 -0
- data/lib/public_atom_module/latch_data.v +30 -0
- data/lib/public_atom_module/latency.v +48 -0
- data/lib/public_atom_module/latency_dynamic.v +83 -0
- data/lib/public_atom_module/latency_long.v +84 -0
- data/lib/public_atom_module/latency_verb.v +52 -0
- data/lib/public_atom_module/once_event.sv +65 -0
- data/lib/public_atom_module/pipe_reg.v +93 -0
- data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
- data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
- data/lib/tdl/Logic/logic_edge.rb +1 -1
- data/lib/tdl/auto_script/autogensdl.rb +16 -5
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +49 -10
- data/lib/tdl/basefunc.rb +1 -0
- data/lib/tdl/class_hdl/hdl_always_comb.rb +8 -4
- data/lib/tdl/class_hdl/hdl_always_ff.rb +49 -8
- data/lib/tdl/class_hdl/hdl_assign.rb +12 -4
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +18 -16
- data/lib/tdl/class_hdl/hdl_foreach.rb +4 -4
- data/lib/tdl/class_hdl/hdl_function.rb +8 -6
- data/lib/tdl/class_hdl/hdl_generate.rb +9 -5
- data/lib/tdl/class_hdl/hdl_initial.rb +36 -13
- data/lib/tdl/class_hdl/hdl_module_def.rb +27 -7
- data/lib/tdl/class_hdl/hdl_package.rb +45 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +117 -24
- data/lib/tdl/class_hdl/hdl_struct.rb +3 -3
- data/lib/tdl/class_hdl/hdl_verify.rb +1 -1
- data/lib/tdl/elements/Reset.rb +5 -9
- data/lib/tdl/elements/clock.rb +5 -9
- data/lib/tdl/elements/data_inf.rb +0 -17
- data/lib/tdl/elements/logic.rb +9 -31
- data/lib/tdl/elements/mail_box.rb +6 -1
- data/lib/tdl/elements/originclass.rb +23 -48
- data/lib/tdl/elements/parameter.rb +6 -7
- data/lib/tdl/examples/10_random/exp_random.sv +3 -3
- data/lib/tdl/examples/11_test_unit/dve.tcl +6 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +9 -8
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +6 -3
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +5 -5
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +9 -4
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +5 -5
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -2
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +42 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +9 -9
- data/lib/tdl/examples/11_test_unit/tu1.sv +1 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +13 -13
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +60 -60
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +17 -17
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +9 -9
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +10 -10
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +7 -7
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +4 -4
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +7 -7
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
- data/lib/tdl/examples/4_generate/test_generate.sv +11 -11
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +3 -3
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/body_package.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +5 -5
- data/lib/tdl/examples/7_module_with_package/head_package.sv +1 -1
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -2
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +9 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +13 -0
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +34 -0
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +2 -2
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +4 -2
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +39 -0
- data/lib/tdl/examples/9_itegration/test_top.sv +4 -4
- data/lib/tdl/examples/9_itegration/test_tttop.sv +4 -4
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +9 -0
- data/lib/tdl/examples/9_itegration/top.rb +1 -0
- data/lib/tdl/exlib/axis_eth_ex.rb +95 -0
- data/lib/tdl/exlib/axis_verify.rb +265 -0
- data/lib/tdl/exlib/clock_reset_verify.rb +29 -0
- data/lib/tdl/exlib/dve_tcl.rb +30 -11
- data/lib/tdl/exlib/itegration.rb +15 -3
- data/lib/tdl/exlib/itegration_verb.rb +167 -130
- data/lib/tdl/exlib/logic_verify.rb +88 -0
- data/lib/tdl/exlib/test_point.rb +96 -94
- data/lib/tdl/exlib/test_point.rb.bak +293 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +9 -9
- data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +34 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +79 -65
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +81 -16
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
- data/lib/tdl/sdlmodule/test_unit_module.rb +283 -33
- data/lib/tdl/sdlmodule/test_unit_module.rb.bak +143 -0
- data/lib/tdl/sdlmodule/top_module.rb +62 -58
- data/lib/tdl/sdlmodule/top_module.rb.bak +547 -0
- data/lib/tdl/tdl.rb +18 -3
- data/lib/tdl/tdlerror/tdlerror.rb +1 -1
- metadata +54 -121
- data/CODE_OF_CONDUCT.md +0 -74
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
@@ -3,9 +3,13 @@ module ClassHDL
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class HDLInitialBlock
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attr_accessor :opertor_chains
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def initialize
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attr_reader :belong_to_module
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def initialize(belong_to_module)
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@opertor_chains = []
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@belong_to_module = belong_to_module
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unless @belong_to_module
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raise TdlError.new("HDLInitialBlock must have belong_to_module")
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end
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end
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def instance(block_name=nil)
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str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
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else
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unless op.slaver
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rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
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rel_str = ClassHDL.compact_op_ch(op.instance(:assign, belong_to_module))
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str.push " #{rel_str};"
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end
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end
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end
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str.push "end\n"
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str.join("\n")
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end
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def instance_inspect()
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str = []
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block_name=nil
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str.push "initial begin#{block_name ? ':'.concat(block_name.to_s) : ''}"
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opertor_chains.each do |op|
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unless op.is_a? OpertorChain
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str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
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else
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unless op.slaver
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rel_str = ClassHDL.compact_op_ch(op.instance(:assign,belong_to_module))
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str.push " #{rel_str};"
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end
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end
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end
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def self.Initial(sdl_m,block_name=nil,&block)
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ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLInitialBlock.new) do |ab|
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ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLInitialBlock.new(sdl_m)) do |ab|
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AssignDefOpertor.with_rollback_opertors(:new,&block)
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# return ClassHDL::AssignDefOpertor.curr_assign_block
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AssignDefOpertor.with_rollback_opertors(:old) do
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class BlocAssertIF < BlockIF
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def instance(as_type= :cond)
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if cond.is_a? ClassHDL::OpertorChain
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head_str = "assert(#{cond.instance(:cond)})else begin"
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head_str = "assert(#{cond.instance(:cond, belong_to_module)})else begin"
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else
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head_str = "assert(#{cond.to_s})else begin"
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end
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opertor_chains.each do |oc|
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unless oc.is_a? BlockIF
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unless oc.slaver
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sub_str.push " #{oc.instance(as_type)};"
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sub_str.push " #{oc.instance(as_type,belong_to_module)};"
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end
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else
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sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
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return assert_old(cond,argv_str=formats,&block)
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end
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new_op = ClassHDL::BlocAssertIF.new
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new_op = ClassHDL::BlocAssertIF.new(self)
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ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
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if cond.is_a? ClassHDL::OpertorChain
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cond.slaver = true
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end
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def assert_old(cond,argv_str=nil,&block)
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new_op = ClassHDL::BlocAssertIF.new
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new_op = ClassHDL::BlocAssertIF.new(self)
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# if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
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# new_op.slaver = true
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# end
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@@ -130,17 +153,17 @@ class SdlModule
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end
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def assert_error(argv_str)
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ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{argv_str}\")".to_nq]))
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ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq]))
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ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{argv_str}\")".to_nq], self))
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ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq], self))
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end
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def assert_format_error(formats=[],args=[])
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ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{formats.join(' ')}\",#{args.map{|s| s.to_s}.join(',')})".to_nq]))
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ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq]))
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ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{formats.join(' ')}\",#{args.map{|s| s.to_s}.join(',')})".to_nq], self))
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ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq], self))
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end
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def initial_exec(str)
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ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new([str.to_s.to_nq]))
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ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new([str.to_s.to_nq], self))
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end
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alias_method :always_sim_exec, :initial_exec
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@@ -70,6 +70,9 @@ module ClassHDL
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def initialize(name,sdlm)
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@name = name
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@sdlm = sdlm
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unless SdlModule.exist_module?(@name)
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raise TdlError.new("Cant find module `#{name}` !!!")
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end
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end
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def inst(dname,&block)
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@@ -95,9 +98,23 @@ module ClassHDL
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# else
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# @sdlm.Instance(@name,dname.to_s,&block)
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# end
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rel = nil
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AssignDefOpertor.with_rollback_opertors(:old) do
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if block_given?
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rel = inst(dname,&block)
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else
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## 当没有block 判断 sdlm是否相应方法
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# if @sdlm.has_signal?(dname)
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# if SdlModule.call_module(@name).has_signal?(dname)
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if SdlModule.call_module(@name).respond_to?(dname)
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rel = SdlModule.call_module(@name).signal(dname)
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+
else
|
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+
# super
|
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+
raise TdlError.new( "Cant find signal `#{dname}` in module `#{@name}` path: #{SdlModule.call_module(@name).real_sv_path } !!!" )
|
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|
+
end
|
115
|
+
end
|
100
116
|
end
|
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+
return rel
|
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|
end
|
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119
|
|
103
120
|
end
|
@@ -153,6 +170,9 @@ module ClassHDL
|
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def initialize(sdlm,args={})
|
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@chain = []
|
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@sdlm = sdlm
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+
unless @sdlm
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+
raise TdlError.new("ImplicitPortBase<#{args.to_s}> dont have belong_to_module")
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+
end
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|
@up_args = args
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|
end
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178
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|
@@ -281,7 +301,7 @@ module ClassHDL
|
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if sub_type.is_a? StructMeta
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@sub_type.struct_slots.each do |e|
|
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|
obj.define_singleton_method(e.name) do
|
284
|
-
TdlSpace::ArrayChain.
|
304
|
+
TdlSpace::ArrayChain.create(obj: "#{obj.name}.#{e.name}".to_nq, belong_to_module: obj.belong_to_module)
|
285
305
|
end
|
286
306
|
end
|
287
307
|
end
|
@@ -363,27 +383,27 @@ class SdlModule
|
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363
383
|
|
364
384
|
def >>(*args)
|
365
385
|
str = "{>>{#{args.map{|e| e.to_s }.join(',')}}}"
|
366
|
-
TdlSpace::ArrayChain.
|
386
|
+
TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
|
367
387
|
end
|
368
388
|
|
369
389
|
def <<(*args)
|
370
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|
str = "{<<{#{args.map{|e| e.to_s }.join(',')}}}"
|
371
|
-
TdlSpace::ArrayChain.
|
391
|
+
TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
|
372
392
|
end
|
373
393
|
|
374
394
|
def logic_bind_(*args)
|
375
395
|
str = "{#{args.map{|e| e.to_s }.join(',')}}"
|
376
|
-
TdlSpace::ArrayChain.
|
396
|
+
TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
|
377
397
|
end
|
378
398
|
|
379
399
|
def clog2(arg)
|
380
400
|
str = "$clog2(#{arg.to_s})"
|
381
|
-
TdlSpace::ArrayChain.
|
401
|
+
TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
|
382
402
|
end
|
383
403
|
|
384
404
|
def bits(arg)
|
385
405
|
str = "$bits(#{arg.to_s})"
|
386
|
-
TdlSpace::ArrayChain.
|
406
|
+
TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
|
387
407
|
end
|
388
408
|
|
389
409
|
end
|
@@ -90,6 +90,51 @@ module ClassHDL
|
|
90
90
|
return str
|
91
91
|
end
|
92
92
|
|
93
|
+
def build_module_verb(ex_param: "",ex_port: "",ex_up_code: "",ex_down_code: "")
|
94
|
+
# Tdl.Puts pagination(module_name)
|
95
|
+
Tdl.Build_SdlModule_Puts(module_name)
|
96
|
+
|
97
|
+
ex_param = ex_param.to_s unless ex_param
|
98
|
+
ex_port = ex_port.to_s unless ex_port
|
99
|
+
ex_up_code = ex_up_code.to_s unless ex_up_code
|
100
|
+
ex_down_code = ex_down_code.to_s unless ex_down_code
|
101
|
+
|
102
|
+
# gen_auto_method # auto generate class method for interface
|
103
|
+
# draw = Tdl.inst + Tdl.draw
|
104
|
+
|
105
|
+
instance_draw_str = instance_draw # It must run before vars_define_inst,because some signals define when inst
|
106
|
+
vars_exec_inst_str = vars_exec_inst # It must run before vars_define_inst,because some signals define when vars exec
|
107
|
+
|
108
|
+
post_str = post_inst_stack_call()
|
109
|
+
|
110
|
+
unless post_str.strip.empty?
|
111
|
+
post_str = pagination("ROOT REF") + post_str
|
112
|
+
end
|
113
|
+
|
114
|
+
draw = pagination("define") + vars_define_inst + pagination("instance") + instance_draw_str + pagination("expression") + vars_exec_inst_str + post_str
|
115
|
+
|
116
|
+
unless ex_up_code.empty?
|
117
|
+
ex_up_code = "\n//------>> EX CODE <<-------------------\n" + ex_up_code + "//------<< EX CODE >>-------------------\n"
|
118
|
+
end
|
119
|
+
|
120
|
+
unless ex_down_code.empty?
|
121
|
+
ex_down_code = "//------>> EX CODE <<-------------------\n" + ex_down_code + "//------<< EX CODE >>-------------------\n"
|
122
|
+
end
|
123
|
+
|
124
|
+
|
125
|
+
module_name_str = @module_name
|
126
|
+
|
127
|
+
|
128
|
+
# str = module_head+"package #{module_name_str};\n" + build_params(ex_param) + ex_up_code + draw + ex_down_code + "\nendpackage:#{module_name_str}\n" + add_sub_module_file_paths
|
129
|
+
str = "package #{module_name_str};\n" + build_params(ex_param) + ex_up_code + draw + ex_down_code + "\nendpackage:#{module_name_str}\n" + add_sub_module_file_paths
|
130
|
+
|
131
|
+
create_vivado_tcl if @create_tcl
|
132
|
+
create_constraints_file if @create_sdc
|
133
|
+
|
134
|
+
return [module_head_verb,str]
|
135
|
+
end
|
136
|
+
|
137
|
+
|
93
138
|
end
|
94
139
|
|
95
140
|
# class ReqPakcgeLine
|
@@ -39,13 +39,28 @@ module ClassHDL
|
|
39
39
|
|
40
40
|
class OpertorChain
|
41
41
|
attr_accessor :slaver,:tree,:instance_add_brackets
|
42
|
-
|
43
|
-
def initialize(arg
|
42
|
+
attr_reader :belong_to_module
|
43
|
+
def initialize(arg, belong_to_module)
|
44
44
|
@tree = [] #[[inst0,symb0],[inst1,symb1],[other_chain,symb2],[other_chain,symb3]]
|
45
45
|
# self <symb0> inst0 <symb1> inst1 <symb2> ( other_chain ) <symb3> ( other_chain )
|
46
46
|
if arg
|
47
47
|
@tree << arg
|
48
48
|
end
|
49
|
+
@belong_to_module = belong_to_module
|
50
|
+
unless @belong_to_module
|
51
|
+
raise TdlError.new("OpertorChain must have belong_to_module")
|
52
|
+
end
|
53
|
+
end
|
54
|
+
|
55
|
+
def instance_inspect
|
56
|
+
str = ["self belong_to_module:#{belong_to_module.module_name}"]
|
57
|
+
index = 0
|
58
|
+
@tree.each do |node|
|
59
|
+
bl = "#{node[0].respond_to?(:belong_to_module) ? "belong_to_module:#{node[0].belong_to_module.module_name }" : '' }"
|
60
|
+
str << "{{ tree[#{index}][1]node[1]SYMB{#{node[1].to_s}} tree[#{index}][0]node[0]#{node[0].to_s} #{node[0].class} #{bl}}}"
|
61
|
+
index += 1
|
62
|
+
end
|
63
|
+
str.join(" ")
|
49
64
|
end
|
50
65
|
|
51
66
|
ClassHDL::OP_SYMBOLS.each do |os|
|
@@ -61,14 +76,14 @@ module ClassHDL
|
|
61
76
|
new_op = nil
|
62
77
|
AssignDefOpertor.with_rollback_opertors(:old) do
|
63
78
|
if tree.size == 2 && tree.last[1].to_s == "<="
|
64
|
-
new_op = OpertorChain.new
|
79
|
+
new_op = OpertorChain.new(nil,belong_to_module)
|
65
80
|
new_op.tree = new_op.tree + self.tree
|
66
81
|
new_op.tree.push [b,os]
|
67
82
|
elsif tree.size >= 2 && (!['*',"/","~"].include?(tree.last[1].to_s))
|
68
83
|
new_op = brackets
|
69
84
|
new_op.tree.push [b,os]
|
70
85
|
else
|
71
|
-
new_op = OpertorChain.new
|
86
|
+
new_op = OpertorChain.new(nil,belong_to_module)
|
72
87
|
new_op.tree = new_op.tree + self.tree
|
73
88
|
new_op.tree.push [b,os]
|
74
89
|
end
|
@@ -102,17 +117,20 @@ module ClassHDL
|
|
102
117
|
# self.nege = true
|
103
118
|
# return self
|
104
119
|
self.slaver = true
|
105
|
-
|
120
|
+
bel = belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
|
121
|
+
new_op = OpertorChain.new(["~(#{self.instance(:assign, bel)})".to_nq])
|
106
122
|
end
|
107
123
|
|
108
124
|
def brackets
|
109
125
|
self.slaver = true
|
110
|
-
|
126
|
+
bel = ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
|
127
|
+
new_op = OpertorChain.new(["(#{self.instance(:assign, belong_to_module || bel)})".to_nq], belong_to_module)
|
111
128
|
end
|
112
129
|
|
113
130
|
def clog2
|
114
131
|
self.slaver = true
|
115
|
-
|
132
|
+
bel = belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
|
133
|
+
new_op = OpertorChain.new(["$clog2(#{self.instance(:aasign, bel)})".to_nq],belong_to_module)
|
116
134
|
end
|
117
135
|
|
118
136
|
def self.define_op_flag(ruby_op,hdl_op)
|
@@ -126,7 +144,7 @@ module ClassHDL
|
|
126
144
|
# 计算生成新的OpertorChain 是 self 也需要抛弃
|
127
145
|
self.slaver = true
|
128
146
|
# return self
|
129
|
-
new_op = OpertorChain.new
|
147
|
+
new_op = OpertorChain.new(nil, belong_to_module)
|
130
148
|
new_op.tree = new_op.tree + self.tree
|
131
149
|
new_op.tree.push [b,hdl_op]
|
132
150
|
|
@@ -142,10 +160,13 @@ module ClassHDL
|
|
142
160
|
|
143
161
|
|
144
162
|
def to_s
|
145
|
-
instance(type=:cond)
|
163
|
+
instance(type=:cond,belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module ) )
|
146
164
|
end
|
147
165
|
|
148
|
-
def instance(type=:assign)
|
166
|
+
def instance(type=:assign,block_belong_to_module=nil,show=nil)
|
167
|
+
unless block_belong_to_module
|
168
|
+
raise TdlError.new("OpertorChain must has block_belong_to_module")
|
169
|
+
end
|
149
170
|
AssignDefOpertor.with_rollback_opertors(:old) do
|
150
171
|
str = ''
|
151
172
|
# both_symb_used = false
|
@@ -159,21 +180,76 @@ module ClassHDL
|
|
159
180
|
sb = " = "
|
160
181
|
end
|
161
182
|
else
|
183
|
+
|
162
184
|
sb = "#{node[1].to_s}"
|
163
185
|
end
|
164
186
|
else
|
165
|
-
sb = "#{node[1].to_s}
|
187
|
+
sb = "#{node[1].to_s}"
|
188
|
+
end
|
189
|
+
|
190
|
+
if cnt==1 && show
|
191
|
+
puts "tree[1][1]<#{node[1]}> 使用 #{sb}"
|
166
192
|
end
|
167
193
|
|
168
194
|
unless node[0].is_a? OpertorChain
|
169
195
|
## 判断是不是属于 Var <= "String" 形式
|
170
196
|
if (@tree.length == 2) && node[0].instance_of?(String) && !@slaver
|
171
197
|
str += (sb + '"' + node[0].to_s + '"')
|
198
|
+
if show
|
199
|
+
puts "tree 长度等于2; tree[#{cnt}][0] is string; op is not slaver"
|
200
|
+
end
|
172
201
|
elsif node[0].instance_of?(String)
|
173
202
|
# "如果是字符串 则原始输出"
|
174
203
|
str += (sb + '"' + node[0].to_s + '"')
|
204
|
+
if show
|
205
|
+
puts "tree[#{cnt}][0] is string"
|
206
|
+
end
|
175
207
|
else
|
176
|
-
str += (sb + node[0].to_s)
|
208
|
+
# str += (sb + node[0].to_s)
|
209
|
+
if block_belong_to_module
|
210
|
+
if (node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != block_belong_to_module) && node[0].belong_to_module.top_tb_ref? )
|
211
|
+
|
212
|
+
str += (sb + node[0].root_ref)
|
213
|
+
|
214
|
+
if show
|
215
|
+
puts "tree[#{cnt}][0].belong_to_module<#{node[0].belong_to_module.module_name}> != block_belong_to_module<#{block_belong_to_module.module_name}>"
|
216
|
+
end
|
217
|
+
## 反向添加到 TestUnitModule
|
218
|
+
if block_belong_to_module.is_a?(TestUnitModule)
|
219
|
+
block_belong_to_module.add_root_ref_ele(node[0])
|
220
|
+
if show
|
221
|
+
puts "block_belong_to_module<#{block_belong_to_module.module_name}> is TestUnitModule"
|
222
|
+
end
|
223
|
+
end
|
224
|
+
else
|
225
|
+
str += (sb + node[0].to_s)
|
226
|
+
if show
|
227
|
+
mmm = node[0].respond_to?(:belong_to_module) && node[0].belong_to_module.module_name
|
228
|
+
puts "tree[#{cnt}][0]<#{node[0].class}>: ref_root<#{node[0].respond_to?(:root_ref).to_s}> belong_to_module<#{mmm}> block_belong_to_module<#{block_belong_to_module.module_name}> ...."
|
229
|
+
end
|
230
|
+
end
|
231
|
+
elsif(node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != belong_to_module) && node[0].belong_to_module.top_tb_ref? )
|
232
|
+
# sb = "#{node[1].root_ref.to_s}"
|
233
|
+
str += (sb + node[0].root_ref)
|
234
|
+
|
235
|
+
if show
|
236
|
+
puts "tree[#{cnt}][0].belong_to_module<#{node[0].belong_to_module.module_name}> != op.belong_to_module<#{belong_to_module.module_name}>"
|
237
|
+
end
|
238
|
+
|
239
|
+
## 反向添加到 TestUnitModule
|
240
|
+
if belong_to_module.is_a?(TestUnitModule)
|
241
|
+
belong_to_module.add_root_ref_ele(node[0])
|
242
|
+
if show
|
243
|
+
puts "tree[#{cnt}][0]: op.belong_to_module<#{belong_to_module.module_name}> is TestUnitModule"
|
244
|
+
end
|
245
|
+
end
|
246
|
+
else
|
247
|
+
# sb = "#{node[1].to_s}"
|
248
|
+
str += (sb + node[0].to_s)
|
249
|
+
if show
|
250
|
+
puts "tree[#{cnt}][0]: op.belong_to_module<#{belong_to_module.module_name}> ..."
|
251
|
+
end
|
252
|
+
end
|
177
253
|
end
|
178
254
|
else
|
179
255
|
node[0].slaver = true
|
@@ -183,13 +259,17 @@ module ClassHDL
|
|
183
259
|
# if node[0].tree.length>2 && ["&","|","<",">"].include?(node[0].tree[1][1])
|
184
260
|
|
185
261
|
# else
|
262
|
+
|
186
263
|
if sb =~/(\||&){2,2}/
|
187
|
-
str += " #{sb}#{node[0].instance(:slaver).to_s}"
|
264
|
+
str += " #{sb}#{node[0].instance(:slaver,block_belong_to_module || belong_to_module).to_s}"
|
188
265
|
else
|
189
|
-
str += "#{sb}(#{node[0].instance(:slaver).to_s})"
|
266
|
+
str += "#{sb}(#{node[0].instance(:slaver,block_belong_to_module || belong_to_module).to_s})"
|
190
267
|
end
|
191
|
-
|
192
|
-
|
268
|
+
|
269
|
+
if show
|
270
|
+
puts "tree[#{cnt}][0] is op, block_belong_to_module<#{block_belong_to_module.to_s}> op.belong_to_module<#{belong_to_module.to_s}>"
|
271
|
+
end
|
272
|
+
|
193
273
|
end
|
194
274
|
cnt += 1
|
195
275
|
end
|
@@ -215,8 +295,10 @@ module ClassHDL
|
|
215
295
|
|
216
296
|
module AssignDefOpertor
|
217
297
|
@@included_class = []
|
218
|
-
@@curr_assign_block = HDLAssignBlock.new ##HDLAssignBlock ##HDLAlwaysCombBlock
|
219
|
-
@@
|
298
|
+
@@curr_assign_block = HDLAssignBlock.new(true) ##HDLAssignBlock ##HDLAlwaysCombBlock
|
299
|
+
# @@curr_assign_block = nil
|
300
|
+
@@curr_assign_block_stack = [HDLAssignBlock.new(true) ]
|
301
|
+
# @@curr_assign_block_stack = []
|
220
302
|
@@curr_opertor_stack = [:old]
|
221
303
|
|
222
304
|
def self.curr_opertor_stack
|
@@ -275,7 +357,19 @@ module ClassHDL
|
|
275
357
|
if b.is_a? OpertorChain
|
276
358
|
b.slaver = true
|
277
359
|
end
|
278
|
-
|
360
|
+
## 当 进行 X < Y 等运算时OpertorChain 需要获取 assign block的 belong_to_module
|
361
|
+
if @@curr_assign_block
|
362
|
+
bblm = @@curr_assign_block.belong_to_module
|
363
|
+
elsif self.respond_to?(:belong_to_module)
|
364
|
+
bblm = self.belong_to_module
|
365
|
+
elsif b.respond_to?(:belong_to_module)
|
366
|
+
bblm = b.belong_to_module
|
367
|
+
|
368
|
+
else
|
369
|
+
bblm = nil
|
370
|
+
end
|
371
|
+
|
372
|
+
new_op = OpertorChain.new(nil, bblm)
|
279
373
|
new_op.tree.push([self])
|
280
374
|
new_op.tree.push([b,symb])
|
281
375
|
if @@curr_assign_block
|
@@ -490,7 +584,7 @@ class BaseElm
|
|
490
584
|
|
491
585
|
@_array_chain_hash_[name.to_s] = rel
|
492
586
|
end
|
493
|
-
TdlSpace::ArrayChain.
|
587
|
+
TdlSpace::ArrayChain.create(obj: @_array_chain_hash_[name.to_s], lchain:[], belong_to_module: self.belong_to_module)
|
494
588
|
end
|
495
589
|
end
|
496
590
|
end
|
@@ -555,9 +649,8 @@ module TdlSpace
|
|
555
649
|
end
|
556
650
|
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
557
651
|
unless b
|
558
|
-
ArrayChain.
|
652
|
+
ArrayChain.create(obj: obj,lchain: chain+[a],belong_to_module: belong_to_module)
|
559
653
|
else
|
560
|
-
# ArrayChain.new(&obj,chain,[a,b])
|
561
654
|
@end_slice = [a,b]
|
562
655
|
self
|
563
656
|
end
|
@@ -589,7 +682,7 @@ module TdlSpace
|
|
589
682
|
end
|
590
683
|
|
591
684
|
def ~
|
592
|
-
ArrayChain.
|
685
|
+
ArrayChain.create(obj: "~#{self.to_s}", belong_to_module: belong_to_module)
|
593
686
|
end
|
594
687
|
end
|
595
688
|
end
|
@@ -642,7 +735,7 @@ module TdlSpace
|
|
642
735
|
end
|
643
736
|
|
644
737
|
module ClassHDL
|
645
|
-
class StructVar
|
738
|
+
class StructVar < AxiTdl::SdlModuleActiveBaseElm
|
646
739
|
include ClassHDL::AssignDefOpertor
|
647
740
|
end
|
648
741
|
end
|