axi_tdl 0.0.12 → 0.1.3

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Files changed (175) hide show
  1. checksums.yaml +4 -4
  2. data/.github/workflows/gem-push.yml +4 -2
  3. data/.gitignore +3 -1
  4. data/README.EN.md +7 -2
  5. data/README.md +6 -2
  6. data/Rakefile +8 -1
  7. data/axi_tdl.gemspec +1 -2
  8. data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
  9. data/lib/axi/AXI4/axi4_direct_B1.sv +23 -23
  10. data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
  11. data/lib/axi/AXI4/axi4_dpram_cache.sv +34 -34
  12. data/lib/axi/AXI4/axis_to_axi4_wr.rb +1 -0
  13. data/lib/axi/AXI4/axis_to_axi4_wr.sv +24 -24
  14. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
  15. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +33 -33
  16. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +2 -0
  17. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +72 -72
  18. data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +2 -1
  19. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +21 -21
  20. data/lib/axi/AXI_stream/axi_stream_split_channel.rb +7 -1
  21. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +45 -40
  22. data/lib/axi/AXI_stream/axis_head_cut_verb.sv +6 -2
  23. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +30 -30
  24. data/lib/axi/AXI_stream/axis_insert_copy.rb +18 -4
  25. data/lib/axi/AXI_stream/axis_insert_copy.sv +29 -16
  26. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +9 -9
  27. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +38 -38
  28. data/lib/axi/AXI_stream/axis_sim_master_model.rb +30 -0
  29. data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
  30. data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +26 -0
  31. data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +101 -0
  32. data/lib/axi/AXI_stream/axis_split_channel_verb.rb +2 -0
  33. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +4 -4
  34. data/lib/axi/common/common_ram_sim_wrapper.sv +10 -10
  35. data/lib/axi/common/common_ram_wrapper.sv +13 -13
  36. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +27 -27
  37. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +72 -0
  38. data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +58 -0
  39. data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +64 -0
  40. data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
  41. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +69 -0
  42. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +150 -0
  43. data/lib/axi/techbench/tb_axis_split_channel_verb.rb +69 -0
  44. data/lib/axi/techbench/tb_axis_split_channel_verb.sv +125 -0
  45. data/lib/axi_tdl.rb +1 -0
  46. data/lib/axi_tdl/version.rb +1 -1
  47. data/lib/public_atom_module/CheckPClock.sv +53 -0
  48. data/lib/public_atom_module/LICENSE.md +674 -0
  49. data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
  50. data/lib/public_atom_module/bits_decode.sv +71 -0
  51. data/lib/public_atom_module/bits_decode_verb.sv +71 -0
  52. data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
  53. data/lib/public_atom_module/broaden.v +43 -0
  54. data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
  55. data/lib/public_atom_module/ceiling.v +39 -0
  56. data/lib/public_atom_module/ceiling_A1.v +42 -0
  57. data/lib/public_atom_module/clock_rst.sv +64 -0
  58. data/lib/public_atom_module/cross_clk_sync.v +37 -0
  59. data/lib/public_atom_module/edge_generator.v +50 -0
  60. data/lib/public_atom_module/flooring.v +36 -0
  61. data/lib/public_atom_module/latch_data.v +30 -0
  62. data/lib/public_atom_module/latency.v +48 -0
  63. data/lib/public_atom_module/latency_dynamic.v +83 -0
  64. data/lib/public_atom_module/latency_long.v +84 -0
  65. data/lib/public_atom_module/latency_verb.v +52 -0
  66. data/lib/public_atom_module/once_event.sv +65 -0
  67. data/lib/public_atom_module/pipe_reg.v +93 -0
  68. data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
  69. data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
  70. data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
  71. data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
  72. data/lib/tdl/Logic/logic_edge.rb +1 -1
  73. data/lib/tdl/auto_script/autogensdl.rb +16 -5
  74. data/lib/tdl/axi4/axi4_interconnect_verb.rb +49 -10
  75. data/lib/tdl/basefunc.rb +1 -0
  76. data/lib/tdl/class_hdl/hdl_always_comb.rb +8 -4
  77. data/lib/tdl/class_hdl/hdl_always_ff.rb +49 -8
  78. data/lib/tdl/class_hdl/hdl_assign.rb +12 -4
  79. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +18 -16
  80. data/lib/tdl/class_hdl/hdl_foreach.rb +4 -4
  81. data/lib/tdl/class_hdl/hdl_function.rb +8 -6
  82. data/lib/tdl/class_hdl/hdl_generate.rb +9 -5
  83. data/lib/tdl/class_hdl/hdl_initial.rb +36 -13
  84. data/lib/tdl/class_hdl/hdl_module_def.rb +27 -7
  85. data/lib/tdl/class_hdl/hdl_package.rb +45 -0
  86. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +117 -24
  87. data/lib/tdl/class_hdl/hdl_struct.rb +3 -3
  88. data/lib/tdl/class_hdl/hdl_verify.rb +1 -1
  89. data/lib/tdl/elements/Reset.rb +5 -9
  90. data/lib/tdl/elements/clock.rb +5 -9
  91. data/lib/tdl/elements/data_inf.rb +0 -17
  92. data/lib/tdl/elements/logic.rb +9 -31
  93. data/lib/tdl/elements/mail_box.rb +6 -1
  94. data/lib/tdl/elements/originclass.rb +23 -48
  95. data/lib/tdl/elements/parameter.rb +6 -7
  96. data/lib/tdl/examples/10_random/exp_random.sv +3 -3
  97. data/lib/tdl/examples/11_test_unit/dve.tcl +6 -0
  98. data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +9 -8
  99. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +1 -1
  100. data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
  101. data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +6 -3
  102. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +5 -5
  103. data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +9 -4
  104. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +5 -5
  105. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -2
  106. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +42 -0
  107. data/lib/tdl/examples/11_test_unit/tu0.sv +9 -9
  108. data/lib/tdl/examples/11_test_unit/tu1.sv +1 -1
  109. data/lib/tdl/examples/1_define_module/exmple_md.sv +13 -13
  110. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +60 -60
  111. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +2 -2
  112. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +17 -17
  113. data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +9 -9
  114. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
  115. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +1 -1
  116. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +10 -10
  117. data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +3 -3
  118. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +7 -7
  119. data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +3 -3
  120. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
  121. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
  122. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +1 -1
  123. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
  124. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +2 -2
  125. data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +4 -4
  126. data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +2 -2
  127. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  128. data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +7 -7
  129. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +1 -1
  130. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
  131. data/lib/tdl/examples/4_generate/test_generate.sv +11 -11
  132. data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +3 -3
  133. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +1 -1
  134. data/lib/tdl/examples/7_module_with_package/body_package.sv +1 -1
  135. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +5 -5
  136. data/lib/tdl/examples/7_module_with_package/head_package.sv +1 -1
  137. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -2
  138. data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
  139. data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
  140. data/lib/tdl/examples/8_top_module/test_top_sim.sv +9 -0
  141. data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +13 -0
  142. data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +34 -0
  143. data/lib/tdl/examples/9_itegration/tb_test_top.sv +2 -2
  144. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +4 -2
  145. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +39 -0
  146. data/lib/tdl/examples/9_itegration/test_top.sv +4 -4
  147. data/lib/tdl/examples/9_itegration/test_tttop.sv +4 -4
  148. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +9 -0
  149. data/lib/tdl/examples/9_itegration/top.rb +1 -0
  150. data/lib/tdl/exlib/axis_eth_ex.rb +95 -0
  151. data/lib/tdl/exlib/axis_verify.rb +265 -0
  152. data/lib/tdl/exlib/clock_reset_verify.rb +29 -0
  153. data/lib/tdl/exlib/dve_tcl.rb +30 -11
  154. data/lib/tdl/exlib/itegration.rb +15 -3
  155. data/lib/tdl/exlib/itegration_verb.rb +167 -130
  156. data/lib/tdl/exlib/logic_verify.rb +88 -0
  157. data/lib/tdl/exlib/test_point.rb +96 -94
  158. data/lib/tdl/exlib/test_point.rb.bak +293 -0
  159. data/lib/tdl/rebuild_ele/ele_base.rb +9 -9
  160. data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +34 -0
  161. data/lib/tdl/sdlmodule/sdlmodule.rb +79 -65
  162. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
  163. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +81 -16
  164. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
  165. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
  166. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
  167. data/lib/tdl/sdlmodule/test_unit_module.rb +283 -33
  168. data/lib/tdl/sdlmodule/test_unit_module.rb.bak +143 -0
  169. data/lib/tdl/sdlmodule/top_module.rb +62 -58
  170. data/lib/tdl/sdlmodule/top_module.rb.bak +547 -0
  171. data/lib/tdl/tdl.rb +18 -3
  172. data/lib/tdl/tdlerror/tdlerror.rb +1 -1
  173. metadata +54 -121
  174. data/CODE_OF_CONDUCT.md +0 -74
  175. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
@@ -3,9 +3,13 @@ module ClassHDL
3
3
 
4
4
  class HDLInitialBlock
5
5
  attr_accessor :opertor_chains
6
-
7
- def initialize
6
+ attr_reader :belong_to_module
7
+ def initialize(belong_to_module)
8
8
  @opertor_chains = []
9
+ @belong_to_module = belong_to_module
10
+ unless @belong_to_module
11
+ raise TdlError.new("HDLInitialBlock must have belong_to_module")
12
+ end
9
13
  end
10
14
 
11
15
  def instance(block_name=nil)
@@ -16,7 +20,26 @@ module ClassHDL
16
20
  str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
17
21
  else
18
22
  unless op.slaver
19
- rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
23
+ rel_str = ClassHDL.compact_op_ch(op.instance(:assign, belong_to_module))
24
+ str.push " #{rel_str};"
25
+ end
26
+ end
27
+
28
+ end
29
+ str.push "end\n"
30
+ str.join("\n")
31
+ end
32
+
33
+ def instance_inspect()
34
+ str = []
35
+ block_name=nil
36
+ str.push "initial begin#{block_name ? ':'.concat(block_name.to_s) : ''}"
37
+ opertor_chains.each do |op|
38
+ unless op.is_a? OpertorChain
39
+ str.push op.instance(:assign).gsub(/^./){ |m| " #{m}"}
40
+ else
41
+ unless op.slaver
42
+ rel_str = ClassHDL.compact_op_ch(op.instance(:assign,belong_to_module))
20
43
  str.push " #{rel_str};"
21
44
  end
22
45
  end
@@ -28,7 +51,7 @@ module ClassHDL
28
51
  end
29
52
 
30
53
  def self.Initial(sdl_m,block_name=nil,&block)
31
- ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLInitialBlock.new) do |ab|
54
+ ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLInitialBlock.new(sdl_m)) do |ab|
32
55
  AssignDefOpertor.with_rollback_opertors(:new,&block)
33
56
  # return ClassHDL::AssignDefOpertor.curr_assign_block
34
57
  AssignDefOpertor.with_rollback_opertors(:old) do
@@ -40,7 +63,7 @@ module ClassHDL
40
63
  class BlocAssertIF < BlockIF
41
64
  def instance(as_type= :cond)
42
65
  if cond.is_a? ClassHDL::OpertorChain
43
- head_str = "assert(#{cond.instance(:cond)})else begin"
66
+ head_str = "assert(#{cond.instance(:cond, belong_to_module)})else begin"
44
67
  else
45
68
  head_str = "assert(#{cond.to_s})else begin"
46
69
  end
@@ -49,7 +72,7 @@ module ClassHDL
49
72
  opertor_chains.each do |oc|
50
73
  unless oc.is_a? BlockIF
51
74
  unless oc.slaver
52
- sub_str.push " #{oc.instance(as_type)};"
75
+ sub_str.push " #{oc.instance(as_type,belong_to_module)};"
53
76
  end
54
77
  else
55
78
  sub_str.push( oc.instance(as_type).gsub(/^./){ |m| " #{m}"} )
@@ -82,7 +105,7 @@ class SdlModule
82
105
  return assert_old(cond,argv_str=formats,&block)
83
106
  end
84
107
 
85
- new_op = ClassHDL::BlocAssertIF.new
108
+ new_op = ClassHDL::BlocAssertIF.new(self)
86
109
  ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab|
87
110
  if cond.is_a? ClassHDL::OpertorChain
88
111
  cond.slaver = true
@@ -102,7 +125,7 @@ class SdlModule
102
125
  end
103
126
 
104
127
  def assert_old(cond,argv_str=nil,&block)
105
- new_op = ClassHDL::BlocAssertIF.new
128
+ new_op = ClassHDL::BlocAssertIF.new(self)
106
129
  # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF
107
130
  # new_op.slaver = true
108
131
  # end
@@ -130,17 +153,17 @@ class SdlModule
130
153
  end
131
154
 
132
155
  def assert_error(argv_str)
133
- ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{argv_str}\")".to_nq]))
134
- ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq]))
156
+ ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{argv_str}\")".to_nq], self))
157
+ ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq], self))
135
158
  end
136
159
 
137
160
  def assert_format_error(formats=[],args=[])
138
- ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{formats.join(' ')}\",#{args.map{|s| s.to_s}.join(',')})".to_nq]))
139
- ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq]))
161
+ ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{formats.join(' ')}\",#{args.map{|s| s.to_s}.join(',')})".to_nq], self))
162
+ ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq], self))
140
163
  end
141
164
 
142
165
  def initial_exec(str)
143
- ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new([str.to_s.to_nq]))
166
+ ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new([str.to_s.to_nq], self))
144
167
  end
145
168
 
146
169
  alias_method :always_sim_exec, :initial_exec
@@ -70,6 +70,9 @@ module ClassHDL
70
70
  def initialize(name,sdlm)
71
71
  @name = name
72
72
  @sdlm = sdlm
73
+ unless SdlModule.exist_module?(@name)
74
+ raise TdlError.new("Cant find module `#{name}` !!!")
75
+ end
73
76
  end
74
77
 
75
78
  def inst(dname,&block)
@@ -95,9 +98,23 @@ module ClassHDL
95
98
  # else
96
99
  # @sdlm.Instance(@name,dname.to_s,&block)
97
100
  # end
101
+ rel = nil
98
102
  AssignDefOpertor.with_rollback_opertors(:old) do
99
- inst(dname,&block)
103
+ if block_given?
104
+ rel = inst(dname,&block)
105
+ else
106
+ ## 当没有block 判断 sdlm是否相应方法
107
+ # if @sdlm.has_signal?(dname)
108
+ # if SdlModule.call_module(@name).has_signal?(dname)
109
+ if SdlModule.call_module(@name).respond_to?(dname)
110
+ rel = SdlModule.call_module(@name).signal(dname)
111
+ else
112
+ # super
113
+ raise TdlError.new( "Cant find signal `#{dname}` in module `#{@name}` path: #{SdlModule.call_module(@name).real_sv_path } !!!" )
114
+ end
115
+ end
100
116
  end
117
+ return rel
101
118
  end
102
119
 
103
120
  end
@@ -153,6 +170,9 @@ module ClassHDL
153
170
  def initialize(sdlm,args={})
154
171
  @chain = []
155
172
  @sdlm = sdlm
173
+ unless @sdlm
174
+ raise TdlError.new("ImplicitPortBase<#{args.to_s}> dont have belong_to_module")
175
+ end
156
176
  @up_args = args
157
177
  end
158
178
 
@@ -281,7 +301,7 @@ module ClassHDL
281
301
  if sub_type.is_a? StructMeta
282
302
  @sub_type.struct_slots.each do |e|
283
303
  obj.define_singleton_method(e.name) do
284
- TdlSpace::ArrayChain.new("#{obj.name}.#{e.name}".to_nq)
304
+ TdlSpace::ArrayChain.create(obj: "#{obj.name}.#{e.name}".to_nq, belong_to_module: obj.belong_to_module)
285
305
  end
286
306
  end
287
307
  end
@@ -363,27 +383,27 @@ class SdlModule
363
383
 
364
384
  def >>(*args)
365
385
  str = "{>>{#{args.map{|e| e.to_s }.join(',')}}}"
366
- TdlSpace::ArrayChain.new(str)
386
+ TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
367
387
  end
368
388
 
369
389
  def <<(*args)
370
390
  str = "{<<{#{args.map{|e| e.to_s }.join(',')}}}"
371
- TdlSpace::ArrayChain.new(str)
391
+ TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
372
392
  end
373
393
 
374
394
  def logic_bind_(*args)
375
395
  str = "{#{args.map{|e| e.to_s }.join(',')}}"
376
- TdlSpace::ArrayChain.new(str)
396
+ TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
377
397
  end
378
398
 
379
399
  def clog2(arg)
380
400
  str = "$clog2(#{arg.to_s})"
381
- TdlSpace::ArrayChain.new(str)
401
+ TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
382
402
  end
383
403
 
384
404
  def bits(arg)
385
405
  str = "$bits(#{arg.to_s})"
386
- TdlSpace::ArrayChain.new(str)
406
+ TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
387
407
  end
388
408
 
389
409
  end
@@ -90,6 +90,51 @@ module ClassHDL
90
90
  return str
91
91
  end
92
92
 
93
+ def build_module_verb(ex_param: "",ex_port: "",ex_up_code: "",ex_down_code: "")
94
+ # Tdl.Puts pagination(module_name)
95
+ Tdl.Build_SdlModule_Puts(module_name)
96
+
97
+ ex_param = ex_param.to_s unless ex_param
98
+ ex_port = ex_port.to_s unless ex_port
99
+ ex_up_code = ex_up_code.to_s unless ex_up_code
100
+ ex_down_code = ex_down_code.to_s unless ex_down_code
101
+
102
+ # gen_auto_method # auto generate class method for interface
103
+ # draw = Tdl.inst + Tdl.draw
104
+
105
+ instance_draw_str = instance_draw # It must run before vars_define_inst,because some signals define when inst
106
+ vars_exec_inst_str = vars_exec_inst # It must run before vars_define_inst,because some signals define when vars exec
107
+
108
+ post_str = post_inst_stack_call()
109
+
110
+ unless post_str.strip.empty?
111
+ post_str = pagination("ROOT REF") + post_str
112
+ end
113
+
114
+ draw = pagination("define") + vars_define_inst + pagination("instance") + instance_draw_str + pagination("expression") + vars_exec_inst_str + post_str
115
+
116
+ unless ex_up_code.empty?
117
+ ex_up_code = "\n//------>> EX CODE <<-------------------\n" + ex_up_code + "//------<< EX CODE >>-------------------\n"
118
+ end
119
+
120
+ unless ex_down_code.empty?
121
+ ex_down_code = "//------>> EX CODE <<-------------------\n" + ex_down_code + "//------<< EX CODE >>-------------------\n"
122
+ end
123
+
124
+
125
+ module_name_str = @module_name
126
+
127
+
128
+ # str = module_head+"package #{module_name_str};\n" + build_params(ex_param) + ex_up_code + draw + ex_down_code + "\nendpackage:#{module_name_str}\n" + add_sub_module_file_paths
129
+ str = "package #{module_name_str};\n" + build_params(ex_param) + ex_up_code + draw + ex_down_code + "\nendpackage:#{module_name_str}\n" + add_sub_module_file_paths
130
+
131
+ create_vivado_tcl if @create_tcl
132
+ create_constraints_file if @create_sdc
133
+
134
+ return [module_head_verb,str]
135
+ end
136
+
137
+
93
138
  end
94
139
 
95
140
  # class ReqPakcgeLine
@@ -39,13 +39,28 @@ module ClassHDL
39
39
 
40
40
  class OpertorChain
41
41
  attr_accessor :slaver,:tree,:instance_add_brackets
42
-
43
- def initialize(arg=nil)
42
+ attr_reader :belong_to_module
43
+ def initialize(arg, belong_to_module)
44
44
  @tree = [] #[[inst0,symb0],[inst1,symb1],[other_chain,symb2],[other_chain,symb3]]
45
45
  # self <symb0> inst0 <symb1> inst1 <symb2> ( other_chain ) <symb3> ( other_chain )
46
46
  if arg
47
47
  @tree << arg
48
48
  end
49
+ @belong_to_module = belong_to_module
50
+ unless @belong_to_module
51
+ raise TdlError.new("OpertorChain must have belong_to_module")
52
+ end
53
+ end
54
+
55
+ def instance_inspect
56
+ str = ["self belong_to_module:#{belong_to_module.module_name}"]
57
+ index = 0
58
+ @tree.each do |node|
59
+ bl = "#{node[0].respond_to?(:belong_to_module) ? "belong_to_module:#{node[0].belong_to_module.module_name }" : '' }"
60
+ str << "{{ tree[#{index}][1]node[1]SYMB{#{node[1].to_s}} tree[#{index}][0]node[0]#{node[0].to_s} #{node[0].class} #{bl}}}"
61
+ index += 1
62
+ end
63
+ str.join(" ")
49
64
  end
50
65
 
51
66
  ClassHDL::OP_SYMBOLS.each do |os|
@@ -61,14 +76,14 @@ module ClassHDL
61
76
  new_op = nil
62
77
  AssignDefOpertor.with_rollback_opertors(:old) do
63
78
  if tree.size == 2 && tree.last[1].to_s == "<="
64
- new_op = OpertorChain.new
79
+ new_op = OpertorChain.new(nil,belong_to_module)
65
80
  new_op.tree = new_op.tree + self.tree
66
81
  new_op.tree.push [b,os]
67
82
  elsif tree.size >= 2 && (!['*',"/","~"].include?(tree.last[1].to_s))
68
83
  new_op = brackets
69
84
  new_op.tree.push [b,os]
70
85
  else
71
- new_op = OpertorChain.new
86
+ new_op = OpertorChain.new(nil,belong_to_module)
72
87
  new_op.tree = new_op.tree + self.tree
73
88
  new_op.tree.push [b,os]
74
89
  end
@@ -102,17 +117,20 @@ module ClassHDL
102
117
  # self.nege = true
103
118
  # return self
104
119
  self.slaver = true
105
- new_op = OpertorChain.new(["~(#{self.instance})".to_nq])
120
+ bel = belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
121
+ new_op = OpertorChain.new(["~(#{self.instance(:assign, bel)})".to_nq])
106
122
  end
107
123
 
108
124
  def brackets
109
125
  self.slaver = true
110
- new_op = OpertorChain.new(["(#{self.instance})".to_nq])
126
+ bel = ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
127
+ new_op = OpertorChain.new(["(#{self.instance(:assign, belong_to_module || bel)})".to_nq], belong_to_module)
111
128
  end
112
129
 
113
130
  def clog2
114
131
  self.slaver = true
115
- new_op = OpertorChain.new(["$clog2(#{self.instance})".to_nq])
132
+ bel = belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
133
+ new_op = OpertorChain.new(["$clog2(#{self.instance(:aasign, bel)})".to_nq],belong_to_module)
116
134
  end
117
135
 
118
136
  def self.define_op_flag(ruby_op,hdl_op)
@@ -126,7 +144,7 @@ module ClassHDL
126
144
  # 计算生成新的OpertorChain 是 self 也需要抛弃
127
145
  self.slaver = true
128
146
  # return self
129
- new_op = OpertorChain.new
147
+ new_op = OpertorChain.new(nil, belong_to_module)
130
148
  new_op.tree = new_op.tree + self.tree
131
149
  new_op.tree.push [b,hdl_op]
132
150
 
@@ -142,10 +160,13 @@ module ClassHDL
142
160
 
143
161
 
144
162
  def to_s
145
- instance(type=:cond)
163
+ instance(type=:cond,belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module ) )
146
164
  end
147
165
 
148
- def instance(type=:assign)
166
+ def instance(type=:assign,block_belong_to_module=nil,show=nil)
167
+ unless block_belong_to_module
168
+ raise TdlError.new("OpertorChain must has block_belong_to_module")
169
+ end
149
170
  AssignDefOpertor.with_rollback_opertors(:old) do
150
171
  str = ''
151
172
  # both_symb_used = false
@@ -159,21 +180,76 @@ module ClassHDL
159
180
  sb = " = "
160
181
  end
161
182
  else
183
+
162
184
  sb = "#{node[1].to_s}"
163
185
  end
164
186
  else
165
- sb = "#{node[1].to_s} "
187
+ sb = "#{node[1].to_s}"
188
+ end
189
+
190
+ if cnt==1 && show
191
+ puts "tree[1][1]<#{node[1]}> 使用 #{sb}"
166
192
  end
167
193
 
168
194
  unless node[0].is_a? OpertorChain
169
195
  ## 判断是不是属于 Var <= "String" 形式
170
196
  if (@tree.length == 2) && node[0].instance_of?(String) && !@slaver
171
197
  str += (sb + '"' + node[0].to_s + '"')
198
+ if show
199
+ puts "tree 长度等于2; tree[#{cnt}][0] is string; op is not slaver"
200
+ end
172
201
  elsif node[0].instance_of?(String)
173
202
  # "如果是字符串 则原始输出"
174
203
  str += (sb + '"' + node[0].to_s + '"')
204
+ if show
205
+ puts "tree[#{cnt}][0] is string"
206
+ end
175
207
  else
176
- str += (sb + node[0].to_s)
208
+ # str += (sb + node[0].to_s)
209
+ if block_belong_to_module
210
+ if (node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != block_belong_to_module) && node[0].belong_to_module.top_tb_ref? )
211
+
212
+ str += (sb + node[0].root_ref)
213
+
214
+ if show
215
+ puts "tree[#{cnt}][0].belong_to_module<#{node[0].belong_to_module.module_name}> != block_belong_to_module<#{block_belong_to_module.module_name}>"
216
+ end
217
+ ## 反向添加到 TestUnitModule
218
+ if block_belong_to_module.is_a?(TestUnitModule)
219
+ block_belong_to_module.add_root_ref_ele(node[0])
220
+ if show
221
+ puts "block_belong_to_module<#{block_belong_to_module.module_name}> is TestUnitModule"
222
+ end
223
+ end
224
+ else
225
+ str += (sb + node[0].to_s)
226
+ if show
227
+ mmm = node[0].respond_to?(:belong_to_module) && node[0].belong_to_module.module_name
228
+ puts "tree[#{cnt}][0]<#{node[0].class}>: ref_root<#{node[0].respond_to?(:root_ref).to_s}> belong_to_module<#{mmm}> block_belong_to_module<#{block_belong_to_module.module_name}> ...."
229
+ end
230
+ end
231
+ elsif(node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != belong_to_module) && node[0].belong_to_module.top_tb_ref? )
232
+ # sb = "#{node[1].root_ref.to_s}"
233
+ str += (sb + node[0].root_ref)
234
+
235
+ if show
236
+ puts "tree[#{cnt}][0].belong_to_module<#{node[0].belong_to_module.module_name}> != op.belong_to_module<#{belong_to_module.module_name}>"
237
+ end
238
+
239
+ ## 反向添加到 TestUnitModule
240
+ if belong_to_module.is_a?(TestUnitModule)
241
+ belong_to_module.add_root_ref_ele(node[0])
242
+ if show
243
+ puts "tree[#{cnt}][0]: op.belong_to_module<#{belong_to_module.module_name}> is TestUnitModule"
244
+ end
245
+ end
246
+ else
247
+ # sb = "#{node[1].to_s}"
248
+ str += (sb + node[0].to_s)
249
+ if show
250
+ puts "tree[#{cnt}][0]: op.belong_to_module<#{belong_to_module.module_name}> ..."
251
+ end
252
+ end
177
253
  end
178
254
  else
179
255
  node[0].slaver = true
@@ -183,13 +259,17 @@ module ClassHDL
183
259
  # if node[0].tree.length>2 && ["&","|","<",">"].include?(node[0].tree[1][1])
184
260
 
185
261
  # else
262
+
186
263
  if sb =~/(\||&){2,2}/
187
- str += " #{sb}#{node[0].instance(:slaver).to_s}"
264
+ str += " #{sb}#{node[0].instance(:slaver,block_belong_to_module || belong_to_module).to_s}"
188
265
  else
189
- str += "#{sb}(#{node[0].instance(:slaver).to_s})"
266
+ str += "#{sb}(#{node[0].instance(:slaver,block_belong_to_module || belong_to_module).to_s})"
190
267
  end
191
- # end
192
- # str += "#{sb}(#{"Node"})"
268
+
269
+ if show
270
+ puts "tree[#{cnt}][0] is op, block_belong_to_module<#{block_belong_to_module.to_s}> op.belong_to_module<#{belong_to_module.to_s}>"
271
+ end
272
+
193
273
  end
194
274
  cnt += 1
195
275
  end
@@ -215,8 +295,10 @@ module ClassHDL
215
295
 
216
296
  module AssignDefOpertor
217
297
  @@included_class = []
218
- @@curr_assign_block = HDLAssignBlock.new ##HDLAssignBlock ##HDLAlwaysCombBlock
219
- @@curr_assign_block_stack = [HDLAssignBlock.new ]
298
+ @@curr_assign_block = HDLAssignBlock.new(true) ##HDLAssignBlock ##HDLAlwaysCombBlock
299
+ # @@curr_assign_block = nil
300
+ @@curr_assign_block_stack = [HDLAssignBlock.new(true) ]
301
+ # @@curr_assign_block_stack = []
220
302
  @@curr_opertor_stack = [:old]
221
303
 
222
304
  def self.curr_opertor_stack
@@ -275,7 +357,19 @@ module ClassHDL
275
357
  if b.is_a? OpertorChain
276
358
  b.slaver = true
277
359
  end
278
- new_op = OpertorChain.new
360
+ ## 进行 X < Y 等运算时OpertorChain 需要获取 assign block的 belong_to_module
361
+ if @@curr_assign_block
362
+ bblm = @@curr_assign_block.belong_to_module
363
+ elsif self.respond_to?(:belong_to_module)
364
+ bblm = self.belong_to_module
365
+ elsif b.respond_to?(:belong_to_module)
366
+ bblm = b.belong_to_module
367
+
368
+ else
369
+ bblm = nil
370
+ end
371
+
372
+ new_op = OpertorChain.new(nil, bblm)
279
373
  new_op.tree.push([self])
280
374
  new_op.tree.push([b,symb])
281
375
  if @@curr_assign_block
@@ -490,7 +584,7 @@ class BaseElm
490
584
 
491
585
  @_array_chain_hash_[name.to_s] = rel
492
586
  end
493
- TdlSpace::ArrayChain.new(@_array_chain_hash_[name.to_s],[])
587
+ TdlSpace::ArrayChain.create(obj: @_array_chain_hash_[name.to_s], lchain:[], belong_to_module: self.belong_to_module)
494
588
  end
495
589
  end
496
590
  end
@@ -555,9 +649,8 @@ module TdlSpace
555
649
  end
556
650
  ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
557
651
  unless b
558
- ArrayChain.new(obj,chain+[a])
652
+ ArrayChain.create(obj: obj,lchain: chain+[a],belong_to_module: belong_to_module)
559
653
  else
560
- # ArrayChain.new(&obj,chain,[a,b])
561
654
  @end_slice = [a,b]
562
655
  self
563
656
  end
@@ -589,7 +682,7 @@ module TdlSpace
589
682
  end
590
683
 
591
684
  def ~
592
- ArrayChain.new("~#{self.to_s}")
685
+ ArrayChain.create(obj: "~#{self.to_s}", belong_to_module: belong_to_module)
593
686
  end
594
687
  end
595
688
  end
@@ -642,7 +735,7 @@ module TdlSpace
642
735
  end
643
736
 
644
737
  module ClassHDL
645
- class StructVar
738
+ class StructVar < AxiTdl::SdlModuleActiveBaseElm
646
739
  include ClassHDL::AssignDefOpertor
647
740
  end
648
741
  end