axi_tdl 0.0.12 → 0.1.3

data/lib/public_atom_module/cross_clk_sync.v

@@ -0,0 +1,37 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: 
+creaded: 2015/5/8 17:05:00
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module cross_clk_sync #(
+    parameter	LAT		= 2,
+    parameter	DSIZE	= 1
+)(
+    input					clk,
+    input					rst_n,
+    input [DSIZE-1:0]		d,
+    output[DSIZE-1:0]		q
+);
+
+reg	[DSIZE-1:0]		ltc		[LAT-1:0];
+
+always@(posedge clk/*,negedge rst_n*/)begin:GEN_LAT
+integer II;
+    if(~rst_n)begin
+        for(II=0;II<LAT;II=II+1)
+            ltc[II]		<= {DSIZE{1'b0}};
+    end else begin
+        ltc[0]	<= d;
+        for(II=1;II<LAT;II=II+1)
+            ltc[II]		<= ltc[II-1];
+end end
+
+assign	q	= ltc[LAT-1];
+
+endmodule

data/lib/public_atom_module/edge_generator.v

@@ -0,0 +1,50 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version:
+creaded:
+madified:
+***********************************************/
+module edge_generator #(
+    parameter    MODE    = "NORMAL"   // FAST NORMAL BEST
+)(
+    input        clk,
+    input        rst_n,
+    input        in,
+    output       raising,
+    output       falling
+);
+
+reg        in_d0;
+reg        in_d1;
+reg        raising_reg;
+reg        falling_reg;
+
+always@(posedge clk/*,negedge rst_n*/)begin
+    if(~rst_n)begin
+    in_d0           <= 1'b0;
+        in_d1        <= 1'b0;
+        raising_reg  <= 1'b0;
+        falling_reg  <= 1'b0;
+    end else begin
+    in_d0        <= in;
+        in_d1           <= in_d0;
+    if(MODE == "NORMAL")begin
+    raising_reg  <= {in_d0,in} == 2'b01 ;
+    falling_reg     <= {in_d0,in} == 2'b10 ;
+    end else if(MODE == "BEST")begin
+    raising_reg  <= {in_d1,in_d0} == 2'b01 ;
+    falling_reg  <= {in_d1,in_d0} == 2'b10 ;
+    end else begin
+    raising_reg  <= 1'b0;
+    falling_reg  <= 1'b0;
+end end end
+
+
+assign    raising    = (MODE == "FAST")? {in_d0,in} == 2'b01 : raising_reg;
+assign    falling    = (MODE == "FAST")? {in_d0,in} == 2'b10 : falling_reg;
+
+endmodule

data/lib/public_atom_module/flooring.v

@@ -0,0 +1,36 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.0
+creaded: 2015/7/23 13:56:28
+madified:2015/10/30 10:56:34
+***********************************************/
+`timescale 1ns/1ps
+module flooring #(
+	parameter	DSIZE		= 16,
+	parameter	CSIZE		= 4,		//must smaller than DSIZE
+	parameter	OSIZE		= 8,        //must not bigger than DSIZE-CSIZE
+	parameter	SEQUENTIAL	= "TRUE"
+)(
+	input				clock	,
+	input [DSIZE-1:0]	indata  ,
+	output[OSIZE-1:0]	outdata  
+);
+
+
+reg [OSIZE-1:0]		result;
+wire[OSIZE-1:0]		cm_result;
+
+assign	cm_result	= (indata[DSIZE-1-:CSIZE] == {CSIZE{1'b0}})? indata[DSIZE-1-CSIZE-:OSIZE] : {OSIZE{1'b1}}; 
+
+always@(posedge clock)
+	result	<= cm_result;
+
+
+assign	outdata	= (SEQUENTIAL == "TRUE")? result : (SEQUENTIAL == "FALSE")? cm_result : {OSIZE{1'b0}};
+
+endmodule
+

data/lib/public_atom_module/latch_data.v

@@ -0,0 +1,30 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.0
+creaded: 2015/6/5 17:26:19
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module latch_data #(
+	parameter	DSIZE	= 8
+)(
+	input				enable,
+	input [DSIZE-1:0]	in,
+	output[DSIZE-1:0]	out
+);
+
+
+reg	[DSIZE-1:0]	data;
+
+always@(enable)
+	if(enable)
+			data	= in;
+	else	data	= data;
+
+assign	out	= data;
+
+endmodule

data/lib/public_atom_module/latency.v

@@ -0,0 +1,48 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.1 : 2015/12/25 15:53:03
+    supply LAT = 0
+creaded: 2015/5/8 17:05:00
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module latency #(
+    parameter    LAT      = 2,
+    parameter    DSIZE    = 1
+)(
+    input                    clk,
+    input                    rst_n,
+    input [DSIZE-1:0]        d,
+    output[DSIZE-1:0]        q
+);
+
+reg    [DSIZE-1:0]        ltc        [LAT-1:0];
+
+generate
+if(LAT > 0)begin
+always@(posedge clk/*,negedge rst_n*/)begin:GEN_LAT
+integer II;
+    if(~rst_n)begin
+        for(II=0;II<LAT;II=II+1)
+            ltc[II]        <= {DSIZE{1'b0}};
+    end else begin
+        ltc[0]    <= d;
+        for(II=1;II<LAT;II=II+1)
+            ltc[II]        <= ltc[II-1];
+end end
+
+assign    q    = ltc[LAT-1];
+
+end else begin
+
+assign    q    = d;
+
+end
+endgenerate
+
+
+endmodule

data/lib/public_atom_module/latency_dynamic.v

@@ -0,0 +1,83 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.0
+creaded: 2016/4/1 上午10:45:19
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module latency_dynamic #(
+	parameter	LSIZE	= 10
+)(
+	input		        clk	,
+	input		        rst_n	,
+    input [LSIZE-1:0]   lat     ,
+	input		        d       ,
+	output		        q
+);
+
+wire    clock;
+assign  clock = clk;
+
+wire	d_falling;
+wire	d_raising;
+
+edge_generator #(
+	.MODE	("FAST")   // FAST NORMAL BEST
+)edge_generator_inst(
+	.clk			(clock			),
+	.rst_n          (rst_n          ),
+	.in             (d             	),
+	.raising        (d_raising     	),
+	.falling        (d_falling     	)
+);
+
+
+
+reg [LSIZE-1:0]	fedge_cnt;
+reg [LSIZE-1:0]	redge_cnt;
+
+always@(posedge clock/*,negedge rst_n*/)begin
+	if(~rst_n)	fedge_cnt	<= {LSIZE{1'b0}};
+	else begin
+		if(fedge_cnt == {LSIZE{1'b0}})begin
+			if(d_falling)
+					fedge_cnt	<= 10'd1;
+			else	fedge_cnt	<= {LSIZE{1'b0}};
+		end else begin
+			if(fedge_cnt == lat-1'b1)
+					fedge_cnt	<= {LSIZE{1'b0}};
+			else	fedge_cnt	<= fedge_cnt + 1'd1;
+end end end
+
+always@(posedge clock/*,negedge rst_n*/)begin
+	if(~rst_n)	redge_cnt	<= {LSIZE{1'b0}};
+	else begin
+		if(redge_cnt == {LSIZE{1'b0}})begin
+			if(d_raising)
+					redge_cnt	<= 10'd1;
+			else	redge_cnt	<= {LSIZE{1'b0}};
+		end else begin
+			if(redge_cnt == lat-1'b1)
+					redge_cnt	<= {LSIZE{1'b0}};
+			else	redge_cnt	<= redge_cnt + 1'd1;
+end end end
+
+reg	q_reg;
+
+always@(posedge clock/*,negedge rst_n*/)begin
+	if(~rst_n)	q_reg	<= 1'b0;
+	else if(fedge_cnt == lat-1'b1)
+				q_reg	<= 1'b0;
+	else if(redge_cnt == lat-1'b1)
+				q_reg	<= 1'b1;
+	else		q_reg	<= q_reg;
+end
+
+
+assign	q	= q_reg;
+
+endmodule

data/lib/public_atom_module/latency_long.v

@@ -0,0 +1,84 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERA.0.0
+creaded: 2015/12/1 13:44:09
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module latency_long #(
+	parameter	LAT		= 100
+)(
+	input		clock	,
+	input		rst_n	,
+	input		d       ,
+	output		q
+);
+
+wire	d_falling;
+wire	d_raising;
+
+edge_generator #(
+	.MODE	("FAST")   // FAST NORMAL BEST
+)edge_generator_inst(
+	.clk			(clock			),
+	.rst_n          (rst_n          ),
+	.in             (d             	),
+	.raising        (d_raising     	),
+	.falling        (d_falling     	)
+);
+
+
+localparam	PLAT	= LAT-1;
+localparam	DSIZE	= 	(LAT<=64)? 6 : (LAT<=128)? 7 : (LAT<=256)? 8 : 
+						(LAT<=512)? 9 : (LAT<=1024)? 10 : (LAT<=2048)? 11 : (LAT<=4096)? 12 : 32;
+
+reg [DSIZE-1:0]	fedge_cnt;
+reg [DSIZE-1:0]	redge_cnt;
+
+always@(posedge clock/*,negedge rst_n*/)begin
+	if(~rst_n)	fedge_cnt	<= {DSIZE{1'b0}};
+	else begin
+		if(fedge_cnt == {DSIZE{1'b0}})begin
+			if(d_falling)
+					fedge_cnt	<= 10'd1;
+			else	fedge_cnt	<= {DSIZE{1'b0}};
+		end else begin
+			if(fedge_cnt == PLAT)
+					fedge_cnt	<= {DSIZE{1'b0}};
+			else	fedge_cnt	<= fedge_cnt + 1'd1;
+end end end
+
+always@(posedge clock/*,negedge rst_n*/)begin
+	if(~rst_n)	redge_cnt	<= {DSIZE{1'b0}};
+	else begin
+		if(redge_cnt == {DSIZE{1'b0}})begin
+			if(d_raising)
+					redge_cnt	<= 10'd1;
+			else	redge_cnt	<= {DSIZE{1'b0}};
+		end else begin
+			if(redge_cnt == PLAT)
+					redge_cnt	<= {DSIZE{1'b0}};
+			else	redge_cnt	<= redge_cnt + 1'd1;
+end end end
+
+reg	q_reg;
+
+always@(posedge clock/*,negedge rst_n*/)begin
+	if(~rst_n)	q_reg	<= 1'b0;
+	else if(fedge_cnt == PLAT)
+				q_reg	<= 1'b0;
+	else if(redge_cnt == PLAT)
+				q_reg	<= 1'b1;
+	else		q_reg	<= q_reg;
+end
+
+
+assign	q	= q_reg;
+
+endmodule
+
+	

data/lib/public_atom_module/latency_verb.v

@@ -0,0 +1,52 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version: VERB.0.0 :2015/12/1 15:06:34
+	optimize long latency
+creaded: 2015/12/1 15:05:58
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module latency_verb #(
+	parameter	LAT		= 10,
+	parameter	DSIZE	= 1
+)(
+	input				clk		,
+	input				rst_n	,
+	input [DSIZE-1:0]	d		,
+	output[DSIZE-1:0]	q
+);
+
+genvar II;
+
+generate
+if(LAT<40)begin
+latency #(
+	.LAT		(LAT		),
+	.DSIZE		(DSIZE		)
+)lat_int(
+	.clk		(clk		),
+	.rst_n		(rst_n		),
+	.d			(d			),
+	.q			(q			)
+);
+end else begin
+for(II=0;II<DSIZE;II=II+1)begin:FOR_BLOCK
+latency_long #(
+	.LAT		(LAT		)
+)lat_int(
+	.clock		(clk		),
+	.rst_n		(rst_n		),
+	.d			(d[II]		),
+	.q			(q[II]		)
+);
+end
+end
+endgenerate
+
+endmodule
+
+	

data/lib/public_atom_module/once_event.sv

@@ -0,0 +1,65 @@
+/**********************************************
+______________                ______________
+______________ \  /\  /|\  /| ______________
+______________  \/  \/ | \/ | ______________
+descript:
+author : Young
+Version:
+creaded: xxxx.xx.xx
+madified:
+***********************************************/
+`timescale 1ns/1ps
+module once_event #(
+    parameter       MODE = "BOTH"           //RAISE FALL
+)(
+    input               clock,
+    input               rst_n,
+    input               signal,
+    output logic        trigger
+);
+
+logic   signal_raising;
+logic   signal_falling;
+
+edge_generator edge_generator_inst(
+/*input      */  .clk       (clock          ),
+/*input      */  .rst_n     (rst_n          ),
+/*input      */  .in        (signal         ),
+/*output     */  .raising   (signal_raising ),
+/*output     */  .falling   (signal_falling )
+);
+
+logic   raising;
+logic   falling;
+
+always_comb begin
+    if(MODE=="BOTH" || MODE=="RAISE")
+            raising     = signal_raising;
+    else    raising     = 1'b0;
+end
+
+always_comb begin
+    if(MODE=="BOTH" || MODE=="FALL")
+            falling     = signal_falling;
+    else    falling     = 1'b0;
+end
+
+always@(posedge clock,negedge  rst_n)begin:TRIGGER_RECORD_BLOCK
+logic       record;
+    if(~rst_n)begin
+        record  <= 1'b0;
+        trigger <= 1'b0;
+    end else begin
+        if(raising || falling)
+                record  <= 1'b1;
+        else    record  <= record;
+
+        if(record)
+                trigger <= 1'b0;
+        else if(raising || falling)
+                trigger <= 1'b1;
+        else    trigger <= 1'b0;
+    end
+end
+
+endmodule