axi_tdl 0.0.12 → 0.1.3

checksums.yaml

@@ -1,7 +1,7 @@
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+  data.tar.gz: 1c42c7ff45587b03dc9c859eb9c80d7274cf6ff73f006e5bc68ed578a0235a064bb480d7685bf8421432eecdba07d820147d2145037b6a55862e298865356138

data/.github/workflows/gem-push.yml

@@ -35,8 +35,10 @@ jobs:
         mkdir -p $HOME/.gem
         touch $HOME/.gem/credentials
         chmod 0600 $HOME/.gem/credentials
-        printf -- "---\n:rubygems_api_key: ${GEM_HOST_API_KEY}\n" > $HOME/.gem/credentials
+        printf -- "---\n:rubygems_api_key: ${RUBYGEMS_API_KEY}\n" > $HOME/.gem/credentials
         gem build *.gemspec
         gem push *.gem
       env:
-        GEM_HOST_API_KEY: "${{secrets.RUBYGEMS_AUTH_TOKEN}}"
+          GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
+          RUBYGEMS_API_KEY: ${{secrets.RUBYGEMS_API_KEY}}
+          # RELEASE_COMMAND: rake release

data/.gitignore

@@ -7,4 +7,6 @@
 /spec/reports/
 /tmp/
 .rake_tasks~
-lib/tdl/auto_script/tmp/
+lib/tdl/auto_script/tmp/
+/*.gem
+Gemfile.lock

data/README.EN.md

@@ -1,4 +1,9 @@
-# Axi
+
+# AxiTdl
+[![Gem Version](https://badge.fury.io/rb/axi_tdl.svg)](https://badge.fury.io/rb/axi_tdl)
+[![Build Status](https://travis-ci.com/CookDarwin/axi_tdl.svg?branch=main)](https://travis-ci.com/CookDarwin/axi_tdl)
+
+## Axi
   It is a wonderful library of axi4, but it is not full axi4, It is designed by systemverilog. I compact axi4 and add something to it.
 
   axi hdl path
@@ -6,7 +11,7 @@
 require 'axi_tdl'
 AxiTdl::AXI_PATH
 ```
-# Other
+## Other
   It contain a simple interface that only define three signals, `valid`, `ready`, and `data`. I think it is useful for design. 
 
 ## What is tdl?

data/README.md

@@ -1,4 +1,8 @@
-# Axi
+# AxiTdl
+[![Gem Version](https://badge.fury.io/rb/axi_tdl.svg)](https://badge.fury.io/rb/axi_tdl)
+[![Build Status](https://travis-ci.com/CookDarwin/axi_tdl.svg?branch=main)](https://travis-ci.com/CookDarwin/axi_tdl)
+
+## Axi
   axi是一个 axi4 拓展库，它使用的是删减版的AXI4协议，使用systemverilog开发，除此外我还拓展了AXI4的一些信号。
 
   axi hdl 所在路径可以如下Ruby 脚本获取
@@ -6,7 +10,7 @@
 require 'axi_tdl'
 AxiTdl::AXI_PATH
 ```
-# 其他
+## 其他
   此库还包含一个简单的接口定义, 接口信号只有 `valid`, `ready`, 和 `data`. 对于一些轻量设计很有帮助。
 
 ## tdl 是什么？

data/Rakefile

@@ -1,4 +1,4 @@
-require "bundler/gem_tasks"
+# require "bundler/gem_tasks"
 require "rake/clean"
 require "rake/testtask"
 require "fileutils"
@@ -12,3 +12,10 @@ Rake::TestTask.new(:test) do |t|
     # t.ruby_opts = ["-c"]
     # t.verbose = true
 end
+
+desc "编译TB"
+task :tb do 
+    require_relative "./lib/axi_tdl.rb"
+    puts AxiTdl::VERSION
+    require_relative "./lib/axi/techbench/tb_axi_stream_split_channel.rb"
+end

data/axi_tdl.gemspec

@@ -1,4 +1,3 @@
-
 lib = File.expand_path("../lib", __FILE__)
 $LOAD_PATH.unshift(lib) unless $LOAD_PATH.include?(lib)
 require "axi_tdl/version"
@@ -35,7 +34,7 @@ Gem::Specification.new do |spec|
   spec.executables   = spec.files.grep(%r{^exe/}) { |f| File.basename(f) }
   spec.require_paths = ["lib"]
 
-  spec.add_development_dependency "bundler", "~> 1.16"
+  # spec.add_development_dependency "bundler", "~> 1.16"
   spec.add_development_dependency "rake", "~> 10.0"
   # spec.add_development_dependency "rspec"
   spec.add_development_dependency "pry","~> 0.11"

data/lib/axi/AXI4/axi4_direct_A1.sv

@@ -53,7 +53,7 @@ initial begin
     case(MODE)
     "BOTH_to_BOTH","BOTH_to_ONLY_READ","BOTH_to_ONLY_WRITE":
         assert(slaver.MODE =="BOTH")
-        else $error("SLAVER AXIS MODE<%s> != BOTH",slaver.MODE);
+        else $error("SLAVER AXIS MODE<%0s> != BOTH",slaver.MODE);
     "ONLY_READ_to_BOTH":
         assert(slaver.MODE == "ONLY_READ")
         else $error("SLAVER AXIS MODE != ONLY_READ");

data/lib/axi/AXI4/axi4_direct_B1.sv

@@ -12,61 +12,61 @@ madified:
 (* axi4 = "true" *)
 module axi4_direct_B1 (
     (* up_stream = "true" *)
-    axi_inf.slaver      slaver,
+    axi_inf.slaver      slaver_inf,
     (* down_stream = "true" *)
-    axi_inf.master      master
+    axi_inf.master      master_inf
 );
 
 
 generate
-if(slaver.MODE == "ONLY_READ" && master.MODE == "ONLY_READ")
+if(slaver_inf.MODE == "ONLY_READ" && master_inf.MODE == "ONLY_READ")
 axi4_direct_A1 #(
     .MODE   ("ONLY_READ_to_ONLY_READ")    //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
 )axi4_direct_inst_ONLY_READ_to_ONLY_READ(
-/*  axi_inf.slaver */     .slaver   (slaver ),
-/*  axi_inf.master */     .master   (master )
+/*  axi_inf.slaver */     .slaver   (slaver_inf ),
+/*  axi_inf.master */     .master   (master_inf )
 );
-else if(slaver.MODE == "ONLY_READ" && master.MODE == "BOTH")
+else if(slaver_inf.MODE == "ONLY_READ" && master_inf.MODE == "BOTH")
 axi4_direct_A1 #(
     .MODE   ("ONLY_READ_to_BOTH")    //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
 )axi4_direct_inst_ONLY_READ_to_BOTH(
-/*  axi_inf.slaver */     .slaver   (slaver ),
-/*  axi_inf.master */     .master   (master )
+/*  axi_inf.slaver */     .slaver   (slaver_inf ),
+/*  axi_inf.master */     .master   (master_inf )
 );
-else if(slaver.MODE == "ONLY_WRITE" && master.MODE == "BOTH")
+else if(slaver_inf.MODE == "ONLY_WRITE" && master_inf.MODE == "BOTH")
 axi4_direct_A1 #(
     .MODE   ("ONLY_WRITE_to_BOTH")    //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
 )axi4_direct_inst_ONLY_WRITE_to_BOTH(
-/*  axi_inf.slaver */     .slaver   (slaver ),
-/*  axi_inf.master */     .master   (master )
+/*  axi_inf.slaver */     .slaver   (slaver_inf ),
+/*  axi_inf.master */     .master   (master_inf )
 );
-else if(slaver.MODE == "ONLY_WRITE" && master.MODE == "ONLY_WRITE")
+else if(slaver_inf.MODE == "ONLY_WRITE" && master_inf.MODE == "ONLY_WRITE")
 axi4_direct_A1 #(
     .MODE   ("ONLY_WRITE_to_ONLY_WRITE")    //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
 )axi4_direct_inst_ONLY_WRITE_to_ONLY_WRITE(
-/*  axi_inf.slaver */     .slaver   (slaver ),
-/*  axi_inf.master */     .master   (master )
+/*  axi_inf.slaver */     .slaver   (slaver_inf ),
+/*  axi_inf.master */     .master   (master_inf )
 );
-else if(slaver.MODE == "BOTH" && master.MODE == "ONLY_WRITE")
+else if(slaver_inf.MODE == "BOTH" && master_inf.MODE == "ONLY_WRITE")
 axi4_direct_A1 #(
     .MODE   ("BOTH_to_ONLY_WRITE")    //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
 )axi4_direct_inst_BOTH_to_ONLY_WRITE(
-/*  axi_inf.slaver */     .slaver   (slaver ),
-/*  axi_inf.master */     .master   (master )
+/*  axi_inf.slaver */     .slaver   (slaver_inf ),
+/*  axi_inf.master */     .master   (master_inf )
 );
-else if(slaver.MODE == "BOTH" && master.MODE == "ONLY_READ")
+else if(slaver_inf.MODE == "BOTH" && master_inf.MODE == "ONLY_READ")
 axi4_direct_A1 #(
     .MODE   ("BOTH_to_ONLY_READ")    //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
 )axi4_direct_inst_BOTH_to_ONLY_READ(
-/*  axi_inf.slaver */     .slaver   (slaver ),
-/*  axi_inf.master */     .master   (master )
+/*  axi_inf.slaver */     .slaver   (slaver_inf ),
+/*  axi_inf.master */     .master   (master_inf )
 );
-else if(slaver.MODE == "BOTH" && master.MODE == "BOTH")
+else if(slaver_inf.MODE == "BOTH" && master_inf.MODE == "BOTH")
 axi4_direct_A1 #(
     .MODE   ("BOTH_to_BOTH")    //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
 )axi4_direct_inst_BOTH_to_BOTH(
-/*  axi_inf.slaver */     .slaver   (slaver ),
-/*  axi_inf.master */     .master   (master )
+/*  axi_inf.slaver */     .slaver   (slaver_inf ),
+/*  axi_inf.master */     .master   (master_inf )
 );
 
 endgenerate

data/lib/axi/AXI4/axi4_direct_verc.sv

@@ -25,9 +25,9 @@ module axi4_direct_verc #(
     `parameter_string IGNORE_LSIZE = "FALSE"    //(* show = "false" *)
 )(
     (* axi4_up = "true" *)
-    axi_inf.slaver      slaver,
+    axi_inf.slaver      slaver_inf,
     (* axi4_down = "true" *)
-    axi_inf.master      master
+    axi_inf.master      master_inf
 );
 
 
@@ -36,60 +36,60 @@ import SystemPkg::*;
 initial begin
     #(1us);
     if(IGNORE_IDSIZE == "FALSE")begin
-        assert(slaver.IDSIZE <= master.IDSIZE)      //idsize of slaver can be smaller thane master's
+        assert(slaver_inf.IDSIZE <= master_inf.IDSIZE)      //idsize of slaver_inf can be smaller thane master_inf's
         else begin
             $error("SLAVER AXIS IDSIZE != MASTER AXIS IDSIZE");
             $finish;
         end
     end
     if(IGNORE_DSIZE == "FALSE")begin
-        assert(slaver.DSIZE == master.DSIZE)
+        assert(slaver_inf.DSIZE == master_inf.DSIZE)
         else $error("SLAVER AXIS DSIZE != MASTER AXIS DSIZE");
     end
     if(IGNORE_ASIZE == "FALSE")begin
-        assert(slaver.ASIZE == master.ASIZE)
+        assert(slaver_inf.ASIZE == master_inf.ASIZE)
         else $error("SLAVER AXIS ASIZE != MASTER AXIS ASIZE");
     end
     if(IGNORE_LSIZE == "FALSE")begin
-        assert(slaver.LSIZE == master.LSIZE)
+        assert(slaver_inf.LSIZE == master_inf.LSIZE)
         else $error("SLAVER AXIS LSIZE != MASTER AXIS LSIZE");
     end
     case(MODE)
     "BOTH_to_BOTH","BOTH_to_ONLY_READ","BOTH_to_ONLY_WRITE":
-        assert(slaver.MODE =="BOTH" && SLAVER_MODE=="BOTH")
-        else $error("SLAVER AXIS MODE<%s> != BOTH",slaver.MODE);
+        assert(slaver_inf.MODE =="BOTH" && SLAVER_MODE=="BOTH")
+        else $error("SLAVER AXIS MODE<%s> != BOTH",slaver_inf.MODE);
     "ONLY_READ_to_BOTH":
-        assert(slaver.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
+        assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
         else $error("SLAVER AXIS MODE != ONLY_READ");
     "ONLY_WRITE_to_BOTH","ONLY_WRITE_to_ONLY_WRITE":
-        assert(slaver.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
+        assert(slaver_inf.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
         else begin
             $error("SLAVER AXIS MODE != ONLY_WRITE");
             $finish;
         end
     "ONLY_READ_to_ONLY_READ":
-        assert(slaver.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
+        assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
         else $error("SLAVER AXIS MODE != ONLY_READ");
     default:
-        assert(slaver.MODE == "_____")
+        assert(slaver_inf.MODE == "_____")
         else $error("SLAVER AXIS MODE ERROR")  ;
     endcase
 
     case(MODE)
     "ONLY_WRITE_to_BOTH","ONLY_READ_to_BOTH","BOTH_to_BOTH":
-        assert(master.MODE == "BOTH" && MASTER_MODE=="BOTH")
+        assert(master_inf.MODE == "BOTH" && MASTER_MODE=="BOTH")
         else $error("MASTER AXIS MODE != BOTH");
     "BOTH_to_ONLY_READ":
-        assert(master.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READY")
+        assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READY")
         else $error("MASTER AXIS MODE != ONLY_READ");
     "BOTH_to_ONLY_WRITE","ONLY_WRITE_to_ONLY_WRITE":
-        assert(master.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
+        assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
         else $error("MASTER AXIS MODE != ONLY_WRITE");
     "ONLY_READ_to_ONLY_READ":
-        assert(master.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READ")
+        assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READ")
         else $error("MASTER AXIS MODE != ONLY_READ");
     default:
-        assert(master.MODE == "_____")
+        assert(master_inf.MODE == "_____")
         else $error("MASTER AXIS MODE ERROR");
     endcase
 
@@ -97,49 +97,49 @@ end
 
 generate
     if(MASTER_MODE!="ONLY_READ")begin
-        assign master.axi_awid     = slaver.axi_awid   ;
-        assign master.axi_awaddr   = slaver.axi_awaddr ;
-        assign master.axi_awlen    = slaver.axi_awlen  ;
-        assign master.axi_awsize   = slaver.axi_awsize ;
-        assign master.axi_awburst  = slaver.axi_awburst;
-        assign master.axi_awlock   = slaver.axi_awlock ;
-        assign master.axi_awcache  = slaver.axi_awcache;
-        assign master.axi_awprot   = slaver.axi_awprot ;
-        assign master.axi_awqos    = slaver.axi_awqos  ;
-        assign master.axi_awvalid  = slaver.axi_awvalid;
-        assign slaver.axi_awready  = master.axi_awready;
-        assign master.axi_wdata    = slaver.axi_wdata  ;
-        assign master.axi_wstrb    = slaver.axi_wstrb  ;
-        assign master.axi_wlast    = slaver.axi_wlast  ;
-        assign master.axi_wvalid   = slaver.axi_wvalid ;
-        assign slaver.axi_wready   = master.axi_wready ;
-        assign master.axi_bready   = slaver.axi_bready ;
-        assign slaver.axi_bid      = master.axi_bid    ;
-        assign slaver.axi_bresp    = master.axi_bresp  ;
-        assign slaver.axi_bvalid   = master.axi_bvalid ;
+        assign master_inf.axi_awid     = slaver_inf.axi_awid   ;
+        assign master_inf.axi_awaddr   = slaver_inf.axi_awaddr ;
+        assign master_inf.axi_awlen    = slaver_inf.axi_awlen  ;
+        assign master_inf.axi_awsize   = slaver_inf.axi_awsize ;
+        assign master_inf.axi_awburst  = slaver_inf.axi_awburst;
+        assign master_inf.axi_awlock   = slaver_inf.axi_awlock ;
+        assign master_inf.axi_awcache  = slaver_inf.axi_awcache;
+        assign master_inf.axi_awprot   = slaver_inf.axi_awprot ;
+        assign master_inf.axi_awqos    = slaver_inf.axi_awqos  ;
+        assign master_inf.axi_awvalid  = slaver_inf.axi_awvalid;
+        assign slaver_inf.axi_awready  = master_inf.axi_awready;
+        assign master_inf.axi_wdata    = slaver_inf.axi_wdata  ;
+        assign master_inf.axi_wstrb    = slaver_inf.axi_wstrb  ;
+        assign master_inf.axi_wlast    = slaver_inf.axi_wlast  ;
+        assign master_inf.axi_wvalid   = slaver_inf.axi_wvalid ;
+        assign slaver_inf.axi_wready   = master_inf.axi_wready ;
+        assign master_inf.axi_bready   = slaver_inf.axi_bready ;
+        assign slaver_inf.axi_bid      = master_inf.axi_bid    ;
+        assign slaver_inf.axi_bresp    = master_inf.axi_bresp  ;
+        assign slaver_inf.axi_bvalid   = master_inf.axi_bvalid ;
     end
 endgenerate
 
 
 generate
     if(MASTER_MODE!="ONLY_WRITE")begin
-        assign master.axi_arid     = slaver.axi_arid   ;
-        assign master.axi_araddr   = slaver.axi_araddr ;
-        assign master.axi_arlen    = slaver.axi_arlen  ;
-        assign master.axi_arsize   = slaver.axi_arsize ;
-        assign master.axi_arburst  = slaver.axi_arburst;
-        assign master.axi_arlock   = slaver.axi_arlock ;
-        assign master.axi_arcache  = slaver.axi_arcache;
-        assign master.axi_arprot   = slaver.axi_arprot ;
-        assign master.axi_arqos    = slaver.axi_arqos  ;
-        assign master.axi_arvalid  = slaver.axi_arvalid;
-        assign slaver.axi_arready  = master.axi_arready;
-        assign master.axi_rready   = slaver.axi_rready ;
-        assign slaver.axi_rid      = master.axi_rid    ;
-        assign slaver.axi_rdata    = master.axi_rdata  ;
-        assign slaver.axi_rresp    = master.axi_rresp  ;
-        assign slaver.axi_rlast    = master.axi_rlast  ;
-        assign slaver.axi_rvalid   = master.axi_rvalid ;
+        assign master_inf.axi_arid     = slaver_inf.axi_arid   ;
+        assign master_inf.axi_araddr   = slaver_inf.axi_araddr ;
+        assign master_inf.axi_arlen    = slaver_inf.axi_arlen  ;
+        assign master_inf.axi_arsize   = slaver_inf.axi_arsize ;
+        assign master_inf.axi_arburst  = slaver_inf.axi_arburst;
+        assign master_inf.axi_arlock   = slaver_inf.axi_arlock ;
+        assign master_inf.axi_arcache  = slaver_inf.axi_arcache;
+        assign master_inf.axi_arprot   = slaver_inf.axi_arprot ;
+        assign master_inf.axi_arqos    = slaver_inf.axi_arqos  ;
+        assign master_inf.axi_arvalid  = slaver_inf.axi_arvalid;
+        assign slaver_inf.axi_arready  = master_inf.axi_arready;
+        assign master_inf.axi_rready   = slaver_inf.axi_rready ;
+        assign slaver_inf.axi_rid      = master_inf.axi_rid    ;
+        assign slaver_inf.axi_rdata    = master_inf.axi_rdata  ;
+        assign slaver_inf.axi_rresp    = master_inf.axi_rresp  ;
+        assign slaver_inf.axi_rlast    = master_inf.axi_rlast  ;
+        assign slaver_inf.axi_rvalid   = master_inf.axi_rvalid ;
     end
 endgenerate
 

data/lib/axi/AXI4/axi4_dpram_cache.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+creaded: XXXX.XX.XX
 madified:
 ***********************************************/
 `timescale 1ns/1ps
@@ -20,7 +20,7 @@ module axi4_dpram_cache #(
 //==========================================================================
 //-------- define ----------------------------------------------------------
 
-cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE( a_inf.DSIZE/8)) xram_inf();
+cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE((a_inf.DSIZE / 8))) xram_inf();
 axi_stream_inf #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1),.USIZE(1)) a_axis_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(a_inf.DSIZE),.USIZE(1)) a_axis_rd_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
 data_inf_c #(.DSIZE(a_inf.ASIZE+1)) a_datac_rd_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
@@ -69,44 +69,44 @@ common_ram_wrapper #(
 //==========================================================================
 //-------- expression ------------------------------------------------------
 initial begin
-    assert( a_inf.ASIZE==b_inf.ASIZE)else begin
-         $error("a_inf.ASIZE != b_inf.ASIZE");
-         $stop;
+    assert(a_inf.ASIZE==b_inf.ASIZE)else begin
+        $error("a_inf.ASIZE != b_inf.ASIZE");
+        $stop;
     end
-    assert( a_inf.DSIZE==b_inf.DSIZE)else begin
-         $error("a_inf.ASIZE != b_inf.ASIZE");
-         $stop;
+    assert(a_inf.DSIZE==b_inf.DSIZE)else begin
+        $error("a_inf.ASIZE != b_inf.ASIZE");
+        $stop;
     end
 end
 
-assign  a_axis_inf.axis_tready = a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1] || (a_datac_rd_inf.ready && !a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1]);
-assign  a_datac_rd_inf.data = {a_axis_inf.axis_tlast,a_axis_inf.axis_tdata[ ( a_inf.ASIZE+a_inf.DSIZE+1-1)-1: ( a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1]};
-assign  a_datac_rd_inf.valid = a_axis_inf.axis_tvalid && !a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1];
+assign a_axis_inf.axis_tready = a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1] || (a_datac_rd_inf.ready && !a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1]);
+assign a_datac_rd_inf.data = {a_axis_inf.axis_tlast,a_axis_inf.axis_tdata[(a_inf.ASIZE+a_inf.DSIZE+1-1)-1:(a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1]};
+assign a_datac_rd_inf.valid = a_axis_inf.axis_tvalid && !a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1];
 
-assign  a_axis_rd_inf.axis_tvalid = a_datac_rd_rel_inf.valid;
-assign  a_axis_rd_inf.axis_tdata = a_datac_rd_rel_inf.data[ a_inf.DSIZE-1:0];
-assign  a_axis_rd_inf.axis_tlast = a_datac_rd_rel_inf.data[ a_inf.ASIZE+a_inf.DSIZE+1-1];
-assign  a_datac_rd_rel_inf.ready = a_axis_rd_inf.axis_tready;
-assign  xram_inf.addra = a_axis_inf.axis_tdata[ ( a_inf.ASIZE+a_inf.DSIZE+1-1)-1: ( a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1];
-assign  xram_inf.dia = a_axis_inf.axis_tdata[ a_inf.DSIZE-1:0];
-assign  xram_inf.wea = {xram_inf.MSIZE{a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1]}};
-assign  xram_inf.ena = 1'b1;
-assign  xram_inf.clka = a_inf.axi_aclk;
-assign  xram_inf.rsta = ~a_inf.axi_aresetn;
+assign a_axis_rd_inf.axis_tvalid = a_datac_rd_rel_inf.valid;
+assign a_axis_rd_inf.axis_tdata = a_datac_rd_rel_inf.data[a_inf.DSIZE-1:0];
+assign a_axis_rd_inf.axis_tlast = a_datac_rd_rel_inf.data[a_inf.ASIZE+a_inf.DSIZE+1-1];
+assign a_datac_rd_rel_inf.ready = a_axis_rd_inf.axis_tready;
+assign xram_inf.addra = a_axis_inf.axis_tdata[(a_inf.ASIZE+a_inf.DSIZE+1-1)-1:(a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1];
+assign xram_inf.dia = a_axis_inf.axis_tdata[a_inf.DSIZE-1:0];
+assign xram_inf.wea = {xram_inf.MSIZE{a_axis_inf.axis_tdata[a_inf.ASIZE+a_inf.DSIZE+1-1]}};
+assign xram_inf.ena = 1'b1;
+assign xram_inf.clka = a_inf.axi_aclk;
+assign xram_inf.rsta = ~a_inf.axi_aresetn;
 
-assign  b_axis_inf.axis_tready = b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1] || (b_datac_rd_inf.ready && !b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1]);
-assign  b_datac_rd_inf.data = {b_axis_inf.axis_tlast,b_axis_inf.axis_tdata[ ( b_inf.ASIZE+b_inf.DSIZE+1-1)-1: ( b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1]};
-assign  b_datac_rd_inf.valid = b_axis_inf.axis_tvalid && !b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1];
+assign b_axis_inf.axis_tready = b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1] || (b_datac_rd_inf.ready && !b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1]);
+assign b_datac_rd_inf.data = {b_axis_inf.axis_tlast,b_axis_inf.axis_tdata[(b_inf.ASIZE+b_inf.DSIZE+1-1)-1:(b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1]};
+assign b_datac_rd_inf.valid = b_axis_inf.axis_tvalid && !b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1];
 
-assign  b_axis_rd_inf.axis_tvalid = b_datac_rd_rel_inf.valid;
-assign  b_axis_rd_inf.axis_tdata = b_datac_rd_rel_inf.data[ b_inf.DSIZE-1:0];
-assign  b_axis_rd_inf.axis_tlast = b_datac_rd_rel_inf.data[ b_inf.ASIZE+b_inf.DSIZE+1-1];
-assign  b_datac_rd_rel_inf.ready = b_axis_rd_inf.axis_tready;
-assign  xram_inf.addrb = b_axis_inf.axis_tdata[ ( b_inf.ASIZE+b_inf.DSIZE+1-1)-1: ( b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1];
-assign  xram_inf.dib = b_axis_inf.axis_tdata[ b_inf.DSIZE-1:0];
-assign  xram_inf.web = {xram_inf.MSIZE{b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1]}};
-assign  xram_inf.enb = 1'b1;
-assign  xram_inf.clkb = b_inf.axi_aclk;
-assign  xram_inf.rstb = ~b_inf.axi_aresetn;
+assign b_axis_rd_inf.axis_tvalid = b_datac_rd_rel_inf.valid;
+assign b_axis_rd_inf.axis_tdata = b_datac_rd_rel_inf.data[b_inf.DSIZE-1:0];
+assign b_axis_rd_inf.axis_tlast = b_datac_rd_rel_inf.data[b_inf.ASIZE+b_inf.DSIZE+1-1];
+assign b_datac_rd_rel_inf.ready = b_axis_rd_inf.axis_tready;
+assign xram_inf.addrb = b_axis_inf.axis_tdata[(b_inf.ASIZE+b_inf.DSIZE+1-1)-1:(b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1];
+assign xram_inf.dib = b_axis_inf.axis_tdata[b_inf.DSIZE-1:0];
+assign xram_inf.web = {xram_inf.MSIZE{b_axis_inf.axis_tdata[b_inf.ASIZE+b_inf.DSIZE+1-1]}};
+assign xram_inf.enb = 1'b1;
+assign xram_inf.clkb = b_inf.axi_aclk;
+assign xram_inf.rstb = ~b_inf.axi_aresetn;
 
 endmodule