axi_tdl 0.0.12 → 0.1.3

data/lib/tdl/rebuild_ele/ele_base.rb

@@ -128,7 +128,7 @@ module TdlSpace
                 define_method(tdl_key) do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
                     unless rel 
-                        "#{inst_name}.#{hdl_key}".to_nq
+                        TdlSpace::ArrayChain.create(obj: "#{inst_name}.#{hdl_key}".to_nq, belong_to_module: belong_to_module)
                     else 
                         rel 
                     end
@@ -152,9 +152,9 @@ module TdlSpace
                 define_method('clock') do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
                     if !dimension || dimension.empty?
-                        rel || TdlSpace::ArrayChain.new("#{self.inst_name}.#{hdl_key}")
+                        rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
                     else  
-                        rel || TdlSpace::ArrayChain.new("#{self.inst_name}[0].#{hdl_key}")
+                        rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}[0].#{hdl_key}", belong_to_module: belong_to_module)
                     end
                 end
 
@@ -171,7 +171,7 @@ module TdlSpace
              self.class_exec(tdl_key) do |tdl_key|
                 define_method('reset') do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
-                    rel || TdlSpace::ArrayChain.new("#{self.inst_name}.#{hdl_key}")
+                    rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
                 end
 
                 define_method("reset=") do |arg|
@@ -200,7 +200,7 @@ module TdlSpace
             self.class_exec(tdl_key) do |tdl_key|
                 define_method(tdl_key) do 
                     rel = self.instance_variable_get("@_#{tdl_key}_") || default_value
-                    rel || TdlSpace::ArrayChain.new("#{self.inst_name}.#{hdl_key}")
+                    rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
                 end
 
                 define_method("#{tdl_key}=") do |arg|
@@ -215,7 +215,7 @@ module TdlSpace
                 _io_map(e,e,nil,'sdata',nil)
                 self.class_exec(e) do |e|
                     define_method(e) do 
-                        TdlSpace::ArrayChain.new("#{self.inst_name}.#{e}")
+                        TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{e}", belong_to_module: belong_to_module)
                     end
                 end
             end
@@ -225,7 +225,7 @@ module TdlSpace
             _io_map(name,name,nil,'pdata',dimension)
             self.class_exec(name) do |e|
                 define_method(e) do 
-                    TdlSpace::ArrayChain.new("#{self.inst_name}.#{e}")
+                    TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{e}", belong_to_module: belong_to_module)
                 end
             end
         end
@@ -374,7 +374,7 @@ module TdlSpace
                     e.slaver = true
                 end 
             end
-            TdlSpace::ArrayChain.new(self,a)
+            TdlSpace::ArrayChain.create(obj: self,lchain: a, belong_to_module: belong_to_module)
         end
 
         def instance(exp_len: nil)
@@ -537,7 +537,7 @@ module TdlSpace
 end
 
 module TdlSpace
-    class TdlBaseInterface
+    class TdlBaseInterface < AxiTdl::SdlModuleActiveBaseElm
         extend VarElemenAttr
         include VarElemenCore
 

data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb

@@ -0,0 +1,34 @@
+require 'sqlite3'
+module AxiTdl
+
+    module SdlmodulePathDB 
+        DB_PATH = File.join(__dir__, "../auto_script/tmp/sdlmodule_path_map.db" )
+        TARGET = SQLite3::Database.new DB_PATH
+
+        def self.ceate_sdlmoule_path_table
+
+            tabel = nil
+            TARGET.execute("SELECT count(*) FROM sqlite_master WHERE type='table' AND name='sdlmoule_mtime_path';") do |row|
+                tabel_exist = row 
+                break
+            end
+
+            # Create a table
+            unless table 
+                rows = TARGET.execute <<-SQL
+                    create table sdlmoule_mtime_path (
+                        name varchar(128),
+                        path varchar(1024),
+                        grade varchar(5),
+                        blog varchar(50)
+                    );
+                SQL
+            end
+
+            
+        end
+
+
+    end
+
+end

data/lib/tdl/sdlmodule/sdlmodule.rb

@@ -74,7 +74,7 @@ class SdlModule
             if e.is_a? String 
                 next 
             end
-            tmp = e.new(name:"#{head}_NC")
+            tmp = e.new(name:"#{head}_NC",belong_to_module: self)
             tmp.belong_to_module = self
             tmp.ghost = true
             instance_variable_set("@#{head}_NC",tmp)
@@ -116,6 +116,7 @@ class SdlModule
     attr_accessor :dont_gen_sv,:target_class
     ## 模块头部添加package引入
     attr_accessor :head_import_packages
+    attr_accessor :instanced_and_parent_module
 
     def initialize(name: "tdlmodule",out_sv_path: nil)
         # $new_m = self
@@ -126,16 +127,6 @@ class SdlModule
         @@allmodule << self
         @module_name = name
         @real_sv_path = File.join(@out_sv_path,"#{@module_name}.sv") if @out_sv_path
-        # @port_clocks = []
-        # @port_resets = []
-        # @port_params = []
-        # @port_logics = []
-        # @port_datainfs = []
-        # @port_datainf_c_s = []
-        # @port_videoinfs = []
-        # @port_axisinfs = []
-        # @port_axi4infs = []
-        # @port_axilinfs = []
 
         @port_clocks        = Hash.new
         @port_resets        = Hash.new
@@ -163,52 +154,16 @@ class SdlModule
             # self.instance_variable_set("#{head_str}_NC",tmp)
         end
         create_ghost
-        # @super_modules = []
-        # @Logic_collect = []
-        # @Logic_inst = []
-        # @Logic_draw = []
-        #
-        # @Clock_collect = []
-        # @Clock_inst = []
-        # @Clock_draw = []
-        #
-        # @Reset_collect = []
-        # @Reset_inst = []
-        # @Reset_draw = []
-        #
-        # @Parameter_collect = []
-        # @Parameter_inst = []
-        # @Parameter_draw = []
-        #
-        # @DataInf_collect = []
-        # @DataInf_inst = []
-        # @DataInf_draw = []
-        #
-        # @DataInf_C_collect = []
-        # @DataInf_C_inst = []
-        # @DataInf_C_draw = []
-        #
-        # @AxiStream_collect = []
-        # @AxiStream_inst = []
-        # @AxiStream_draw = []
-        #
-        # @AxiLite_collect = []
-        # @AxiLite_inst = []
-        # @AxiLite_draw = []
-        #
-        # @VideoInf_collect = []
-        # @VideoInf_inst = []
-        # @VideoInf_draw = []
-        #
-        # @Axi4_collect = []
-        # @Axi4_inst = []
-        # @Axi4_draw = []
+
         if block_given?
             yield(self)
         end
 
         @instanced_and_parent_module ||= Hash.new
         @instance_and_children_module ||= Hash.new
+
+        ## 记录当前模块被例化的 具体对象
+        @instances =[]
     end
 
     public
@@ -341,23 +296,26 @@ class SdlModule
     ## 例化模块
 
     def method_missing(method,*args,&block)
+        rel = nil
+        ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
+            @@_method_missing_sub_methds ||= []
+
+            @@_method_missing_sub_methds.each do |me|
+                rel = self.send(me,method,*args,&block)
+                if rel 
+                    rel 
+                end
+            end
 
-        @@_method_missing_sub_methds ||= []
-
-        @@_method_missing_sub_methds.each do |me|
-            rel = self.send(me,method,*args,&block)
+            ## 最后才调用阴性例化模块
+            rel = implicit_inst_module_method_missing(method,*args,&block)
             if rel 
-                return rel 
+                rel
+            else
+                super
             end
         end
-
-        ## 最后才调用阴性例化模块
-        rel = implicit_inst_module_method_missing(method,*args,&block)
-        if rel 
-            return rel
-        else
-            super
-        end
+        return rel
     end
 end
 
@@ -468,4 +426,60 @@ class SdlModule
             puts (fstr % [_indexs[xi], _names[xi], _paths[xi]])
         end
     end
-end
+end
+
+class SdlModule 
+
+    ## 获取信号的绝对路径
+    def path_refs(&block)
+        collects = []
+        if self != TopModule.current.techbench
+            @instances.each do |it|
+                it.origin.parents_inst_tree do |tree|
+                    ll = ["$root"]
+                    rt = tree.reverse
+                    rt.each_index do |index|
+                        if rt[index].respond_to? :module_name
+                            ll << rt[index].module_name 
+                        else 
+                            ll << rt[index].inst_name
+                        end
+                    end
+                    # ll << it.inst_name
+                    new_name = ll.join('.').to_nq
+                    if block_given?
+                        if yield(new_name)
+                            collects << new_name
+                        end 
+                    else
+                        collects << new_name
+                    end
+                end
+            end
+        else
+            collects = ["$root.#{self.module_name}".to_nq]
+        end
+        collects
+    end
+
+    ## 定义获取 信号的绝对路径
+    def root_ref(&block)
+        ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
+            rels = path_refs(&block)
+            if block_given?
+                sst = "block given"
+            else
+                sst = "no block"
+            end
+
+            if rels.size == 1
+                rels[0]
+            elsif rels.size == 0
+                raise TdlError.new "#{module_name} Cant find root ref {#{sst}}"
+            else
+                raise TdlError.new "#{module_name} Find multi root refs {#{sst}} \n#{rels.join("\n")}\n"
+            end
+        end
+    end
+
+end

data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb

@@ -88,7 +88,7 @@ module TdlSpace
                 dimension = []
             end
             name = to_inp(name)
-            belong_to_module.Def.logic(name: name,dsize: @chain.last || 1,dimension: dimension,type: @type || 'logic')
+            rel = belong_to_module.Def.logic(name: name,dsize: @chain.last || 1,dimension: dimension,type: @type || 'logic')
         end
 
         def wire 

data/lib/tdl/sdlmodule/sdlmodule_draw.rb

@@ -51,28 +51,34 @@ class SdlModule
         return if (@origin_sv || @dont_gen_sv)
         pre_inst_stack_call
         @out_sv_path ||= '..\..\tdl\test_sdlmodule'
-        # unless GlobalParam.sim
+        if File.exist?(File.join(@out_sv_path,"#{module_name}.sv")) 
+            old_str = File.open(File.join(@out_sv_path,"#{module_name}.sv")).read.sub(/\/\*.*?\*\//m,"").gsub(/\/\/.*/,"").sub(/^`timescale .*/,"").strip
+        
+
+            head_str,body_str = build_module_verb(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
+            new_str = head_str+body_str
+            if body_str.gsub(/\/\*.*?\*\//m,"").gsub(/\/\/.*/,"").strip != old_str
+                File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f|
+                    f.print new_str
+                end
+            end 
+        else
             File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f|
-                f.puts build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
+                f.print build_module_verb(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code).join("")
             end
-        # else
-        #     Tdl.Puts "+INFO+ It generate SIM top File"
-        #     File.open(File.join(out_sv_path,"#{module_name}_sim.sv"),"w") do |f|
-        #         f.puts build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
-        #     end
-        # end
+        end 
     end
 
-    def gen_sv_module_text
-        # @out_sv_path ||= File.dirname(File.expand_path(__FILE__))
-        return if (@origin_sv || @dont_gen_sv)
-        pre_inst_stack_call
-        @out_sv_path ||= '..\..\tdl\test_sdlmodule'
-        # unless GlobalParam.sim
+    # def gen_sv_module_text
+    #     # @out_sv_path ||= File.dirname(File.expand_path(__FILE__))
+    #     return if (@origin_sv || @dont_gen_sv)
+    #     pre_inst_stack_call
+    #     @out_sv_path ||= '..\..\tdl\test_sdlmodule'
+    #     # unless GlobalParam.sim
 
-        return build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
+    #     return build_module(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
 
-    end
+    # end
 
     def build_module(ex_param:"",ex_port:"",ex_up_code:"",ex_down_code:"")
         # Tdl.Puts pagination(module_name)
@@ -124,6 +130,58 @@ class SdlModule
         return str
     end
 
+    def build_module_verb(ex_param:"",ex_port:"",ex_up_code:"",ex_down_code:"") #return [ head, body]
+        # Tdl.Puts pagination(module_name)
+        Tdl.Build_SdlModule_Puts(module_name)
+
+        ex_param        = ex_param.to_s     unless ex_param
+        ex_port         = ex_port.to_s      unless ex_port
+        ex_up_code      = ex_up_code.to_s   unless ex_up_code
+        ex_down_code    = ex_down_code.to_s unless ex_down_code
+
+        # gen_auto_method     # auto generate class method for interface
+        # draw = Tdl.inst + Tdl.draw
+
+        instance_draw_str = instance_draw       # It must run before vars_define_inst,because some signals define when inst
+        vars_exec_inst_str = vars_exec_inst     # It must run before vars_define_inst,because some signals define when vars exec
+
+        post_str = post_inst_stack_call()
+
+        unless post_str.strip.empty?
+            post_str = pagination("ROOT REF") + post_str
+        end
+
+        draw = pagination("define") + vars_define_inst + pagination("instance") + instance_draw_str + pagination("expression") + vars_exec_inst_str + post_str
+
+        unless ex_up_code.empty?
+            ex_up_code = "\n//------>> EX CODE <<-------------------\n" + ex_up_code + "//------<< EX CODE >>-------------------\n"
+        end
+
+        unless ex_down_code.empty?
+            ex_down_code = "//------>> EX CODE <<-------------------\n" + ex_down_code + "//------<< EX CODE >>-------------------\n"
+        end
+
+        # str = module_head+"module #{@module_name}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + gen_lite_str() + draw + ex_down_code + "\nendmodule\n"
+        # unless GlobalParam.sim
+            module_name_str = @module_name
+        # else
+        #     module_name_str = @module_name+"_sim"
+        # end
+        unless head_import_packages
+            str = "module #{module_name_str}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + draw + ex_down_code + "\nendmodule\n" + add_sub_module_file_paths
+        else
+            head_import_pkgs_str = head_import_packages.map{|e| "import #{e}::*;" }.join('')
+            str = "module #{module_name_str} #{head_import_pkgs_str}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + draw + ex_down_code + "\nendmodule\n" + add_sub_module_file_paths
+        end
+
+        create_vivado_tcl if @create_tcl
+        create_constraints_file if @create_sdc
+
+        # return str
+        return [module_head_verb, str]
+    end
+
+
     private
 
     def old_module_head
@@ -149,6 +207,13 @@ madified:
 }
     end
 
+    def module_head_verb
+%Q{#{$__sdlmodule_head_logo__.sub(/created:.*/, "created: #{Time.now()}")}
+#{macro_def}
+#{head_class}
+}
+            end
+
     def head_class
         case(@target_class.to_s)
         when "AxiStream"

data/lib/tdl/sdlmodule/sdlmodule_instance.rb

@@ -448,6 +448,9 @@ class SdlModule
         # @ports = (@port_clocks + @port_resets + @port_logics + @port_datainfs + @port_datainf_c_s + @port_videoinfs + @port_axisinfs + @port_axi4infs + @port_axilinfs)
         @instance_cnt ||= 0
         inst_p = SdlInst.new(origin:self,name:name)
+     
+        @instances ||= []
+        @instances << inst_p
 
         @port_params.each do |k,v|
             inst_p.inst_param_hash[k.to_s] = nil

data/lib/tdl/sdlmodule/sdlmodule_port_define.rb

@@ -65,7 +65,7 @@ class SdlModule
         if value.is_a? Float
             type = :real
         end
-        tmp = Parameter.new(name:name.to_s,value:value,port:true,type:type,show:show)
+        tmp = Parameter.new(name:name.to_s,value:value,port:true,type:type,show:show, belong_to_module: self)
         add_to_new_module("@port_params",tmp)
         add_method_to_itgt(name,tmp)
         tmp
@@ -87,7 +87,7 @@ class SdlModule
         #     tmp
         # end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
-            tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension)
+            tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension, belong_to_module: self)
             add_to_new_module("@port_logics",tmp)
             add_method_to_itgt(name,tmp)
             tmp
@@ -109,7 +109,7 @@ class SdlModule
         #     tmp
         # end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
-            tmp = Logic.new(name:name,dsize:dsize,port:"output",dimension:dimension,type: 'logic')
+            tmp = Logic.new(name:name,dsize:dsize,port:"output",dimension:dimension,type: 'logic', belong_to_module: self)
             add_to_new_module("@port_logics",tmp)
 
             if block_given?
@@ -136,7 +136,7 @@ class SdlModule
         #     tmp
         # end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
-            tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension,type: '' )
+            tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension,type: '' , belong_to_module: self)
             add_to_new_module("@port_logics",tmp)
 
             if block_given?
@@ -150,7 +150,7 @@ class SdlModule
     def Clock(name,freqM:100,port: :input,pin:[],iostd:[],dsize:1,pin_prop:nil)
         port_name_chk(name)
         pin,iostd = parse_pin_prop(pin_prop) if pin_prop
-        a = Clock.new(name:name,freqM:freqM,port:port,dsize:dsize)
+        a = Clock.new(name:name,freqM:freqM,port:port,dsize:dsize, belong_to_module: self)
         add_to_new_module("@port_clocks",a)
 
         if block_given?
@@ -164,7 +164,7 @@ class SdlModule
     def Reset(name,port: :input,active:"low",pin:[],iostd:[],dsize:1,pin_prop:nil)
         port_name_chk(name)
         pin,iostd = parse_pin_prop(pin_prop) if pin_prop
-        a = Reset.new(name:name,active:active.to_s.downcase,port:port,dsize:dsize)
+        a = Reset.new(name:name,active:active.to_s.downcase,port:port,dsize:dsize, belong_to_module: self)
         add_to_new_module("@port_resets",a)
         # define_method(name){ a }
         add_method_to_itgt(name,a)