smallworld-re 1.0.3__py3-none-any.whl → 2.0.0__py3-none-any.whl

smallworld/state/cpus/mips64.py

@@ -1,5 +1,3 @@
-import typing
-
 from ... import platforms
 from .. import state
 from . import cpu
@@ -8,44 +6,6 @@ from . import cpu
 class MIPS64(cpu.CPU):
     """Abstract CPU state object for all MIPS64 targets"""
 
-    # Excluded registers:
-    # - zero: Hard-wired to zero
-    # - at: Reserved for assembler
-    # - kX: Reserved for kernel; used as general in some ABIs
-    # - fX: Floating-point registers
-    # - acX: Accumulator registers
-    _GENERAL_PURPOSE_REGS = [
-        "v0",
-        "v1",
-        "a0",
-        "a1",
-        "a2",
-        "a3",
-        "a4",
-        "a5",
-        "a6",
-        "a7",
-        "t0",
-        "t1",
-        "t2",
-        "t3",
-        "t4",
-        "t8",
-        "t9",
-        "s0",
-        "s1",
-        "s2",
-        "s3",
-        "s4",
-        "s5",
-        "s6",
-        "s7",
-        "s8",
-    ]
-
-    def get_general_purpose_registers(self) -> typing.List[str]:
-        return self._GENERAL_PURPOSE_REGS
-
     def __init__(self):
         super().__init__()
         # NOTE: MIPS registers have both a name and a number.
@@ -304,27 +264,27 @@ class MIPS64EL(MIPS64):
         # from 64-bit multiplication, amongst others.
         self.ac0 = state.Register("ac0", size=16)
         self.add(self.ac0)
-        self.lo = state.RegisterAlias("lo0", self.ac0, size=8, offset=0)
-        self.add(self.lo)
-        self.hi = state.RegisterAlias("hi0", self.ac0, size=8, offset=4)
-        self.add(self.hi)
+        self.lo0 = state.RegisterAlias("lo0", self.ac0, size=8, offset=0)
+        self.add(self.lo0)
+        self.hi0 = state.RegisterAlias("hi0", self.ac0, size=8, offset=8)
+        self.add(self.hi0)
         self.ac1 = state.Register("ac1", size=16)
         self.add(self.ac1)
         self.lo1 = state.RegisterAlias("lo1", self.ac1, size=8, offset=0)
         self.add(self.lo1)
-        self.hi1 = state.RegisterAlias("hi1", self.ac1, size=8, offset=4)
+        self.hi1 = state.RegisterAlias("hi1", self.ac1, size=8, offset=8)
         self.add(self.hi1)
         self.ac2 = state.Register("ac2", size=16)
         self.add(self.ac2)
         self.lo2 = state.RegisterAlias("lo2", self.ac2, size=8, offset=0)
         self.add(self.lo2)
-        self.hi2 = state.RegisterAlias("hi2", self.ac2, size=8, offset=4)
+        self.hi2 = state.RegisterAlias("hi2", self.ac2, size=8, offset=8)
         self.add(self.hi2)
         self.ac3 = state.Register("ac3", size=16)
         self.add(self.ac3)
         self.lo3 = state.RegisterAlias("lo3", self.ac3, size=8, offset=0)
         self.add(self.lo3)
-        self.hi3 = state.RegisterAlias("hi3", self.ac3, size=8, offset=4)
+        self.hi3 = state.RegisterAlias("hi3", self.ac3, size=8, offset=8)
         self.add(self.hi3)
         # TODO: MIPS has a boatload of extensions with their own registers.
         # There isn't a clean join between Sleigh, Unicorn, and MIPS docs.
@@ -346,27 +306,27 @@ class MIPS64BE(MIPS64):
         # *** Accumulator Registers ***
         # MIPS uses these to implement 64-bit results
         # from 32-bit multiplication, amongst others.
-        self.ac0 = state.Register("ac0", size=8)
+        self.ac0 = state.Register("ac0", size=16)
         self.add(self.ac0)
-        self.hi = state.RegisterAlias("hi0", self.ac0, size=8, offset=0)
-        self.add(self.hi)
-        self.lo = state.RegisterAlias("lo0", self.ac0, size=8, offset=4)
-        self.add(self.lo)
-        self.ac1 = state.Register("ac1", size=8)
+        self.hi0 = state.RegisterAlias("hi0", self.ac0, size=8, offset=0)
+        self.add(self.hi0)
+        self.lo0 = state.RegisterAlias("lo0", self.ac0, size=8, offset=8)
+        self.add(self.lo0)
+        self.ac1 = state.Register("ac1", size=16)
         self.add(self.ac1)
         self.hi1 = state.RegisterAlias("hi1", self.ac1, size=8, offset=0)
         self.add(self.hi1)
-        self.lo1 = state.RegisterAlias("lo1", self.ac1, size=8, offset=4)
+        self.lo1 = state.RegisterAlias("lo1", self.ac1, size=8, offset=8)
         self.add(self.lo1)
-        self.ac2 = state.Register("ac2", size=8)
+        self.ac2 = state.Register("ac2", size=16)
         self.add(self.ac2)
         self.hi2 = state.RegisterAlias("hi2", self.ac2, size=8, offset=0)
         self.add(self.hi2)
-        self.lo2 = state.RegisterAlias("lo2", self.ac2, size=8, offset=4)
+        self.lo2 = state.RegisterAlias("lo2", self.ac2, size=8, offset=8)
         self.add(self.lo2)
-        self.ac3 = state.Register("ac3", size=8)
+        self.ac3 = state.Register("ac3", size=16)
         self.add(self.ac3)
         self.hi3 = state.RegisterAlias("hi3", self.ac3, size=8, offset=0)
         self.add(self.hi3)
-        self.lo3 = state.RegisterAlias("lo3", self.ac3, size=8, offset=4)
+        self.lo3 = state.RegisterAlias("lo3", self.ac3, size=8, offset=8)
         self.add(self.lo3)

smallworld/state/cpus/powerpc.py

@@ -1,5 +1,3 @@
-import typing
-
 from ... import platforms
 from .. import state
 from . import cpu
@@ -8,11 +6,6 @@ from . import cpu
 class PowerPC(cpu.CPU):
     """CPU state for 32-bit PowerPC."""
 
-    _GENERAL_PURPOSE_REGS = [f"r{i}" for i in range(0, 32)]
-
-    def get_general_purpose_registers(self) -> typing.List[str]:
-        return self._GENERAL_PURPOSE_REGS
-
     def __init__(self, wordsize):
         super().__init__()
         # *** General Purpose Registers ***
@@ -199,8 +192,8 @@ class PowerPC(cpu.CPU):
         self.add(self.xer)
 
         # Floating Point Status and Control Register
-        self.fpsrc = state.Register("fpscr", size=4)
-        self.add(self.fpsrc)
+        self.fpscr = state.Register("fpscr", size=4)
+        self.add(self.fpscr)
 
         # TODO: This only focuses on the user-facing registrers.
         # ppc has a huge number of privileged registers.

smallworld/state/cpus/riscv.py

@@ -1,5 +1,3 @@
-import typing
-
 from ... import platforms, state
 from . import cpu
 
@@ -11,14 +9,6 @@ class RISCV64(cpu.CPU):
         platforms.Architecture.RISCV64, platforms.Byteorder.LITTLE
     )
 
-    def get_general_purpose_registers(self) -> typing.List[str]:
-        # - x0 is wired to zero
-        # - x1 is the link register
-        # - x2 is the stack pointer
-        # - x3 is the global pointer
-        # - x4 is the thread pointer
-        return [f"x{i}" for i in range(5, 32)]
-
     def __init__(self):
         super().__init__()
         # *** General-Purpose Registers ***
@@ -67,7 +57,7 @@ class RISCV64(cpu.CPU):
         self.x8 = state.Register("x8", 8)
         self.add(self.x8)
         self.s0 = state.RegisterAlias("s0", self.x8, 8, 0)
-        self.add(self.x8)
+        self.add(self.s0)
         # x9 is a callee-saved register
         self.x9 = state.Register("x9", 8)
         self.add(self.x9)

smallworld/state/cpus/xtensa.py

@@ -1,5 +1,3 @@
-import typing
-
 from ... import platforms, state
 from . import cpu
 
@@ -15,9 +13,6 @@ class XTensa(cpu.CPU):
     I'm not putting up with that shit for now.
     """
 
-    def get_general_purpose_registers(self) -> typing.List[str]:
-        return [f"a{i}" for i in range(0, 16)]
-
     def __init__(self):
         super().__init__()
         # *** General Purpose Registers ***

smallworld/state/memory/code.py

@@ -60,7 +60,39 @@ class Executable(memory.RawMemory):
         )
 
     @classmethod
-    def from_pe(cls, file: typing.BinaryIO):
+    def from_elf_core(
+        cls,
+        file: typing.BinaryIO,
+        address: typing.Optional[int] = None,
+        platform: typing.Optional[Platform] = None,
+        ignore_platform: bool = False,
+    ):
+        """
+        Load an ELF core dump (ET_CORE) from an open file-like object.
+
+        Arguments:
+            file: The open file-like object from which to read.
+            address: The address where this core dump should be loaded.
+            platform: Optional platform for header verification
+            ignore_platform: Skip platform ID and verification
+
+        Returns:
+            An Executable (specifically ElfCoreFile) parsed from the given core dump.
+        """
+        from .elf import ElfCoreFile
+
+        return ElfCoreFile(
+            file, user_base=address, platform=platform, ignore_platform=ignore_platform
+        )
+
+    @classmethod
+    def from_pe(
+        cls,
+        file: typing.BinaryIO,
+        address: typing.Optional[int] = None,
+        platform: typing.Optional[Platform] = None,
+        ignore_platform: bool = False,
+    ):
         """Load an PE executable from an open file-like object.
 
         Arguments:
@@ -70,7 +102,11 @@ class Executable(memory.RawMemory):
         Returns:
             An Executable parsed from the given PE file-like object.
         """
-        raise NotImplementedError("PE parsing not yet implemented")
+        from .pe import PEExecutable
+
+        return PEExecutable(
+            file, user_base=address, platform=platform, ignore_platform=ignore_platform
+        )
 
 
 __all__ = ["Executable"]

smallworld/state/memory/elf/__init__.py

@@ -1,3 +1,7 @@
+from .coredump import ElfCoreFile
 from .elf import ElfExecutable
 
-__all__ = ["ElfExecutable"]
+__all__ = [
+    "ElfExecutable",
+    "ElfCoreFile",
+]

smallworld/state/memory/elf/coredump/__init__.py

@@ -0,0 +1,3 @@
+from .coredump import ElfCoreFile
+
+__all__ = ["ElfCoreFile"]

smallworld/state/memory/elf/coredump/coredump.py

@@ -0,0 +1,46 @@
+import logging
+import typing
+
+import lief
+
+from .....exceptions import ConfigurationError
+from .....platforms import Platform
+from ....cpus import CPU
+from ..elf import ElfExecutable
+from .prstatus import PrStatus
+
+log = logging.getLogger(__name__)
+
+
+class ElfCoreFile(ElfExecutable):
+    """
+    Extended loader to handle core-dump (ET_CORE) ELF files.
+    """
+
+    def __init__(
+        self,
+        file: typing.BinaryIO,
+        platform: typing.Optional[Platform] = None,
+        ignore_platform: bool = False,
+        user_base: typing.Optional[int] = None,
+        page_size: int = 0x1000,
+    ):
+        super().__init__(
+            file=file,
+            platform=platform,
+            ignore_platform=ignore_platform,
+            user_base=user_base,
+            page_size=page_size,
+        )
+
+        assert self._elf is not None
+        parsed_elf = self._elf
+
+        if parsed_elf is None or parsed_elf.header.file_type != lief.ELF.E_TYPE.CORE:
+            raise ConfigurationError("This file is not an ELF core dump (ET_CORE).")
+
+        assert self.platform is not None
+        self.prstatus = PrStatus.for_platform(self.platform, parsed_elf)
+
+    def populate_cpu(self, cpu: CPU) -> None:
+        self.prstatus.populate_cpu(cpu)

smallworld/state/memory/elf/coredump/prstatus/__init__.py

@@ -0,0 +1,27 @@
+from .aarch64 import AArch64
+from .amd64 import AMD64
+from .arm import ARMv5T, ARMv6M, ARMv6MThumb, ARMv7A, ARMv7M, ARMv7R
+from .i386 import I386
+from .mips import MIPS32BE, MIPS32EL
+from .mips64 import MIPS64BE, MIPS64EL
+from .ppc import PowerPC32, PowerPC64
+from .prstatus import PrStatus
+
+__all__ = [
+    "AArch64",
+    "AMD64",
+    "ARMv5T",
+    "ARMv6M",
+    "ARMv6MThumb",
+    "ARMv7M",
+    "ARMv7R",
+    "ARMv7A",
+    "I386",
+    "MIPS32BE",
+    "MIPS32EL",
+    "MIPS64BE",
+    "MIPS64EL",
+    "PowerPC32",
+    "PowerPC64",
+    "PrStatus",
+]

smallworld/state/memory/elf/coredump/prstatus/aarch64.py

@@ -0,0 +1,46 @@
+from ...... import platforms
+from .prstatus import PrStatus
+
+
+class AArch64(PrStatus):
+    architecture = platforms.Architecture.AARCH64
+    byteorder = platforms.Byteorder.LITTLE
+
+    pr_regs_off = 112
+    pr_regs_size = 272
+
+    register_coords = [
+        ("x0", 0x0, 8),
+        ("x1", 0x8, 8),
+        ("x2", 0x10, 8),
+        ("x3", 0x18, 8),
+        ("x4", 0x20, 8),
+        ("x5", 0x28, 8),
+        ("x6", 0x30, 8),
+        ("x7", 0x38, 8),
+        ("x8", 0x40, 8),
+        ("x9", 0x48, 8),
+        ("x10", 0x50, 8),
+        ("x11", 0x58, 8),
+        ("x12", 0x60, 8),
+        ("x13", 0x68, 8),
+        ("x14", 0x70, 8),
+        ("x15", 0x78, 8),
+        ("x16", 0x80, 8),
+        ("x17", 0x88, 8),
+        ("x18", 0x90, 8),
+        ("x19", 0x98, 8),
+        ("x20", 0xA0, 8),
+        ("x21", 0xA8, 8),
+        ("x22", 0xB0, 8),
+        ("x23", 0xB8, 8),
+        ("x24", 0xC0, 8),
+        ("x25", 0xC8, 8),
+        ("x26", 0xD0, 8),
+        ("x27", 0xD8, 8),
+        ("x28", 0xE0, 8),
+        ("x29", 0xE8, 8),
+        ("x30", 0xF0, 8),
+        ("sp", 0xF8, 8),
+        ("pc", 0x100, 8),
+    ]

smallworld/state/memory/elf/coredump/prstatus/amd64.py

@@ -0,0 +1,40 @@
+from ...... import platforms
+from .prstatus import PrStatus
+
+
+class AMD64(PrStatus):
+    architecture = platforms.Architecture.X86_64
+    byteorder = platforms.Byteorder.LITTLE
+
+    pr_regs_off = 112
+    pr_regs_size = 216
+
+    register_coords = [
+        ("r15", 0x0, 8),
+        ("r14", 0x8, 8),
+        ("r13", 0x10, 8),
+        ("r12", 0x18, 8),
+        ("rbp", 0x20, 8),
+        ("rbx", 0x28, 8),
+        ("r11", 0x30, 8),
+        ("r10", 0x38, 8),
+        ("r9", 0x40, 8),
+        ("r8", 0x48, 8),
+        ("rax", 0x50, 8),
+        ("rcx", 0x58, 8),
+        ("rdx", 0x60, 8),
+        ("rsi", 0x68, 8),
+        ("rdi", 0x70, 8),
+        (None, 0x78, 8),  # orig_rax
+        ("rip", 0x80, 8),
+        ("cs", 0x88, 8),
+        ("eflags", 0x90, 8),
+        ("rsp", 0x98, 8),
+        ("ss", 0xA0, 8),
+        (None, 0xA8, 8),  # fs_base
+        (None, 0xB0, 8),  # gs_base
+        ("ds", 0xB8, 8),
+        ("es", 0xC0, 8),
+        ("fs", 0xC8, 8),
+        ("gs", 0xD0, 8),
+    ]

smallworld/state/memory/elf/coredump/prstatus/arm.py

@@ -0,0 +1,53 @@
+from ...... import platforms
+from .prstatus import PrStatus
+
+
+class ARM(PrStatus):
+    byteorder = platforms.Byteorder.LITTLE
+
+    pr_regs_off = 72
+    pr_regs_size = 72
+
+    register_coords = [
+        ("r0", 0x0, 4),
+        ("r1", 0x4, 4),
+        ("r2", 0x8, 4),
+        ("r3", 0xC, 4),
+        ("r4", 0x10, 4),
+        ("r5", 0x14, 4),
+        ("r6", 0x18, 4),
+        ("r7", 0x1C, 4),
+        ("r8", 0x20, 4),
+        ("r9", 0x24, 4),
+        ("r10", 0x28, 4),
+        ("r11", 0x2C, 4),
+        ("r12", 0x30, 4),
+        ("sp", 0x34, 4),
+        ("lr", 0x38, 4),
+        ("pc", 0x3C, 4),
+        # TODO: This is missing two registers.  One is the CPSR, but I have no idea which.
+    ]
+
+
+class ARMv5T(ARM):
+    architecture = platforms.Architecture.ARM_V5T
+
+
+class ARMv6M(ARM):
+    architecture = platforms.Architecture.ARM_V6M
+
+
+class ARMv6MThumb(ARM):
+    architecture = platforms.Architecture.ARM_V6M_THUMB
+
+
+class ARMv7M(ARM):
+    architecture = platforms.Architecture.ARM_V7M
+
+
+class ARMv7R(ARM):
+    architecture = platforms.Architecture.ARM_V7R
+
+
+class ARMv7A(ARM):
+    architecture = platforms.Architecture.ARM_V7A

smallworld/state/memory/elf/coredump/prstatus/i386.py

@@ -0,0 +1,30 @@
+from ...... import platforms
+from .prstatus import PrStatus
+
+
+class I386(PrStatus):
+    architecture = platforms.Architecture.X86_32
+    byteorder = platforms.Byteorder.LITTLE
+
+    pr_regs_off = 72
+    pr_regs_size = 68
+
+    register_coords = [
+        ("ebx", 0x0, 4),
+        ("ecx", 0x4, 4),
+        ("edx", 0x8, 4),
+        ("esi", 0xC, 4),
+        ("edi", 0x10, 4),
+        ("ebp", 0x14, 4),
+        ("eax", 0x18, 4),
+        ("ds", 0x1C, 4),
+        ("es", 0x20, 4),
+        ("fs", 0x24, 4),
+        ("gs", 0x28, 4),
+        (None, 0x2C, 4),  # orig_eax
+        ("eip", 0x30, 4),
+        ("cs", 0x34, 4),
+        ("eflags", 0x38, 4),
+        ("esp", 0x3C, 4),
+        ("ss", 0x40, 4),
+    ]

smallworld/state/memory/elf/coredump/prstatus/mips.py

@@ -0,0 +1,55 @@
+from ...... import platforms
+from .prstatus import PrStatus
+
+
+class MIPS32BE(PrStatus):
+    architecture = platforms.Architecture.MIPS32
+    byteorder = platforms.Byteorder.BIG
+
+    # This doesn't match what the struct def says;
+    # there's something extra in here.
+    pr_regs_off = 96
+    pr_regs_size = 180
+
+    register_coords = [
+        ("zero", 0x0, 4),
+        ("at", 0x4, 4),
+        ("v0", 0x8, 4),
+        ("v1", 0xC, 4),
+        ("a0", 0x10, 4),
+        ("a1", 0x14, 4),
+        ("a2", 0x18, 4),
+        ("a3", 0x1C, 4),
+        ("t0", 0x20, 4),
+        ("t1", 0x24, 4),
+        ("t2", 0x28, 4),
+        ("t3", 0x2C, 4),
+        ("t4", 0x30, 4),
+        ("t5", 0x34, 4),
+        ("t6", 0x38, 4),
+        ("t7", 0x3C, 4),
+        ("s0", 0x40, 4),
+        ("s1", 0x44, 4),
+        ("s2", 0x48, 4),
+        ("s3", 0x4C, 4),
+        ("s4", 0x50, 4),
+        ("s5", 0x54, 4),
+        ("s6", 0x58, 4),
+        ("s7", 0x5C, 4),
+        ("t8", 0x60, 4),
+        ("t9", 0x64, 4),
+        ("k0", 0x68, 4),
+        ("k1", 0x6C, 4),
+        ("gp", 0x70, 4),
+        ("sp", 0x74, 4),
+        ("s8", 0x78, 4),
+        ("ra", 0x7C, 4),
+        # No idea what goes here.
+        # There are exception pseudo-registers,
+        # but they don't fit nicely in this gap.
+        ("pc", 0x88, 4),
+    ]
+
+
+class MIPS32EL(MIPS32BE):
+    byteorder = platforms.Byteorder.LITTLE

smallworld/state/memory/elf/coredump/prstatus/mips64.py

@@ -0,0 +1,57 @@
+from ...... import platforms
+from .prstatus import PrStatus
+
+
+class MIPS64BE(PrStatus):
+    architecture = platforms.Architecture.MIPS64
+    byteorder = platforms.Byteorder.BIG
+
+    # This doesn't match what the struct def says;
+    # there's something extra in here.
+    pr_regs_off = 112
+    pr_regs_size = 360
+
+    register_coords = [
+        ("zero", 0x0, 8),
+        ("at", 0x8, 8),
+        ("v0", 0x10, 8),
+        ("v1", 0x18, 8),
+        ("a0", 0x20, 8),
+        ("a1", 0x28, 8),
+        ("a2", 0x30, 8),
+        ("a3", 0x38, 8),
+        ("a4", 0x40, 8),
+        ("a5", 0x48, 8),
+        ("a6", 0x50, 8),
+        ("a7", 0x58, 8),
+        ("t0", 0x60, 8),
+        ("t1", 0x68, 8),
+        ("t2", 0x70, 8),
+        ("t3", 0x78, 8),
+        ("s0", 0x80, 8),
+        ("s1", 0x88, 8),
+        ("s2", 0x90, 8),
+        ("s3", 0x98, 8),
+        ("s4", 0xA0, 8),
+        ("s5", 0xA8, 8),
+        ("s6", 0xB0, 8),
+        ("s7", 0xB8, 8),
+        ("t8", 0xC0, 8),
+        ("t9", 0xC8, 8),
+        ("k0", 0xD0, 8),
+        ("k1", 0xD8, 8),
+        ("gp", 0xE0, 8),
+        ("sp", 0xE8, 8),
+        ("s8", 0xF0, 8),
+        ("ra", 0xF8, 8),
+        # No idea what goes here.
+        # There are exception pseudo-registers,
+        # but they don't fit nicely in this gap.
+        (None, 0x100, 8),
+        (None, 0x108, 8),
+        ("pc", 0x110, 8),
+    ]
+
+
+class MIPS64EL(MIPS64BE):
+    byteorder = platforms.Byteorder.LITTLE