smallworld-re 1.0.3__py3-none-any.whl → 2.0.0__py3-none-any.whl

smallworld/platforms/defs/platformdef.py

@@ -0,0 +1,97 @@
+import abc
+import typing
+from dataclasses import dataclass
+
+from ... import utils
+from ..platforms import Architecture, Byteorder, Platform
+
+
+@dataclass(frozen=True)
+class RegisterDef:
+    name: str
+    size: int
+
+
+@dataclass(frozen=True)
+class RegisterAliasDef(RegisterDef):
+    parent: str
+    offset: int
+
+
+class PlatformDef(metaclass=abc.ABCMeta):
+    @property
+    @abc.abstractmethod
+    def architecture(self) -> Architecture:
+        """Architecture ID for this platform"""
+        raise NotImplementedError()
+
+    @property
+    @abc.abstractmethod
+    def byteorder(self) -> Byteorder:
+        """Byteorder for this platform"""
+        raise NotImplementedError()
+
+    @property
+    @abc.abstractmethod
+    def address_size(self) -> int:
+        """Address size in bytes"""
+        raise NotImplementedError()
+
+    @property
+    @abc.abstractmethod
+    def capstone_arch(self) -> int:
+        """Capstone Architecture ID"""
+        raise NotImplementedError()
+
+    @property
+    @abc.abstractmethod
+    def capstone_mode(self) -> int:
+        """Capstone Mode ID"""
+        raise NotImplementedError()
+
+    @property
+    @abc.abstractmethod
+    def conditional_branch_mnemonics(self) -> typing.Set[str]:
+        """Set of conditional branch mnemonics"""
+        raise NotImplementedError()
+
+    @property
+    @abc.abstractmethod
+    def compare_mnemonics(self) -> typing.Set[str]:
+        """Set of comparison mnemonics"""
+        raise NotImplementedError()
+
+    @property
+    @abc.abstractmethod
+    def pc_register(self) -> str:
+        """Program Counter register name"""
+        raise NotImplementedError()
+
+    @property
+    @abc.abstractmethod
+    def sp_register(self) -> str:
+        """Stack Pointer register name"""
+        raise NotImplementedError()
+
+    @property
+    @abc.abstractmethod
+    def general_purpose_registers(self) -> typing.List[str]:
+        """List of general-purpose register names"""
+        raise NotImplementedError()
+
+    @property
+    @abc.abstractmethod
+    def registers(self) -> typing.Dict[str, RegisterDef]:
+        """Mapping from canonical register names to register definitions"""
+        raise NotImplementedError()
+
+    @classmethod
+    def for_platform(cls, platform: Platform):
+        try:
+            return utils.find_subclass(
+                cls,
+                lambda x: x.architecture == platform.architecture
+                and x.byteorder == platform.byteorder,
+            )
+        except:
+            raise ValueError(f"No platform definition for {platform}")

smallworld/platforms/defs/powerpc.py

@@ -0,0 +1,259 @@
+import typing
+
+import capstone
+
+from ..platforms import Architecture, Byteorder
+from .platformdef import PlatformDef, RegisterAliasDef, RegisterDef
+
+# PowerPC's register naming convention is extrmely annoying:
+# it doesn't have one.
+#
+# Both the general-purpose registers
+# and floating-point registers are solely referenced by number,
+# thus making it maddening to tell which one you're talking about.
+#
+# Also, registers do have special uses within the ABI,
+# but aside from sp and bp, they're not really written down.
+
+
+class PowerPCPlatformDef(PlatformDef):
+    byteorder = Byteorder.BIG
+
+    capstone_arch = capstone.CS_ARCH_PPC
+
+    # PowerPC conditional branches are an abject pain.
+    # There are 172 possible ways to conditionally branch to an address,
+    # and a similar number of ways to branch to LR or CTR.
+    # Not all of these have mnemonics, but the ISA doesn't actually specify which.
+
+    # Branch to a label
+    _branch_to_label = {
+        # Conditional branch
+        "bc",
+        "beq",
+        "bne",
+        "blt",
+        "ble",
+        "bgt",
+        "bge",
+        "bso",
+        "bns",
+        # Decrement ctr and branch if non-zero
+        # NOTE: This can also include a conditional test
+        "bdnz",
+        # Decrement ctr and branch if zero
+        # NOTE: This can also include a conditional test
+        "bdz",
+    }
+    # Handle "branch-and-link" and "absolute address" variants
+    _branch_and_link_to_label = set(map(lambda x: f"{x}l", _branch_to_label))
+    _branch_absolute_to_label = set(map(lambda x: f"{x}a", _branch_to_label))
+    _branch_and_link_absolute_to_label = set(
+        map(lambda x: f"{x}a", _branch_and_link_to_label)
+    )
+
+    # Handle branch predictor suggestions
+    _branch_to_label_neutral = (
+        _branch_to_label
+        | _branch_and_link_to_label
+        | _branch_absolute_to_label
+        | _branch_and_link_absolute_to_label
+    )
+    _branch_to_label_likely = set(map(lambda x: f"{x}+", _branch_to_label_neutral))
+    _branch_to_label_unlikely = set(map(lambda x: f"{x}-", _branch_to_label_neutral))
+
+    # Collect branch to label
+    _branch_to_label_all = (
+        _branch_to_label_neutral | _branch_to_label_likely | _branch_to_label_unlikely
+    )
+
+    # Branch to LR looks the same as branch to label, but with an "lr" suffix after the condition code
+    _branch_to_lr = set(map(lambda x: f"{x}lr", _branch_to_label))
+    _branch_and_link_to_lr = set(map(lambda x: f"{x}l", _branch_to_lr))
+
+    # Handle branch predictor suggestions
+    _branch_to_lr_neutral = _branch_to_lr | _branch_and_link_to_lr
+    _branch_to_lr_likely = set(map(lambda x: f"{x}+", _branch_to_lr_neutral))
+    _branch_to_lr_unlikely = set(map(lambda x: f"{x}-", _branch_to_lr_neutral))
+
+    # Collect branch to LR
+    _branch_to_lr_all = (
+        _branch_to_lr_neutral | _branch_to_lr_likely | _branch_to_lr_unlikely
+    )
+
+    # Branch to CTR looks the same as branch to label, but with a "ctr" suffix after the condition code.
+    _branch_to_ctr = set(map(lambda x: f"{x}ctr", _branch_to_label))
+    # There are no mnemonics for using ctr as a counter and branch target at once.
+    _branch_to_ctr -= {"bdnzctr", "bdzctr"}
+    _branch_and_link_to_ctr = set(map(lambda x: f"{x}l", _branch_to_ctr))
+
+    # Handle branch predictor suggestions
+    _branch_to_ctr_neutral = _branch_to_ctr | _branch_and_link_to_ctr
+    _branch_to_ctr_likely = set(map(lambda x: f"{x}+", _branch_to_ctr_neutral))
+    _branch_to_ctr_unlikely = set(map(lambda x: f"{x}-", _branch_to_ctr_neutral))
+
+    # Collect branch to CTR
+    _branch_to_ctr_all = (
+        _branch_to_ctr_neutral | _branch_to_ctr_likely | _branch_to_lr_unlikely
+    )
+
+    # Finally, collect all conditional branch mnemonics
+    conditional_branch_mnemonics = (
+        _branch_to_label_all | _branch_to_lr_all | _branch_to_ctr_all
+    )
+
+    compare_mnemonics = {
+        # Compare registers
+        "cmpd",
+        "cmpw",
+        # Compare immediate
+        "cmpi",
+        "cmpdi",
+        "cmpwi",
+        # Compare logical immediate
+        "cmpli",
+        "cmpldi",
+        "cmplwi",
+        # Compare
+        "cmpl",
+        "cmpld",
+        "cmplw",
+    }
+
+    pc_register = "pc"
+    sp_register = "sp"
+
+    # Special registers
+    # - r0 and r2 are reserved for the assembler.
+    # - r1 is the stack pointer
+    # - r31 is the base (frame) pointer
+    general_purpose_registers = [f"r{i}" for i in range(3, 31)]
+
+    @property
+    def registers(self) -> typing.Dict[str, RegisterDef]:
+        return self._registers
+
+    def __init__(self):
+        self._registers = {
+            # *** General Purpose Registers ***
+            # NOTE: Used expressive names for GPRs and FPRs.
+            # gasm just refers to GPRs and FPRS by number.
+            # They use the same numbers; it's very annoying.
+            "r0": RegisterDef(name="r0", size=self.address_size),
+            # NOTE: GPR 1 is also the stack pointer.
+            "r1": RegisterDef(name="r1", size=self.address_size),
+            "sp": RegisterAliasDef("sp", parent="r1", size=self.address_size, offset=0),
+            "r2": RegisterDef(name="r2", size=self.address_size),
+            "r3": RegisterDef(name="r3", size=self.address_size),
+            "r4": RegisterDef(name="r4", size=self.address_size),
+            "r5": RegisterDef(name="r5", size=self.address_size),
+            "r6": RegisterDef(name="r6", size=self.address_size),
+            "r7": RegisterDef(name="r7", size=self.address_size),
+            "r8": RegisterDef(name="r8", size=self.address_size),
+            "r9": RegisterDef(name="r9", size=self.address_size),
+            "r10": RegisterDef(name="r10", size=self.address_size),
+            "r11": RegisterDef(name="r11", size=self.address_size),
+            "r12": RegisterDef(name="r12", size=self.address_size),
+            "r13": RegisterDef(name="r13", size=self.address_size),
+            "r14": RegisterDef(name="r14", size=self.address_size),
+            "r15": RegisterDef(name="r15", size=self.address_size),
+            "r16": RegisterDef(name="r16", size=self.address_size),
+            "r17": RegisterDef(name="r17", size=self.address_size),
+            "r18": RegisterDef(name="r18", size=self.address_size),
+            "r19": RegisterDef(name="r19", size=self.address_size),
+            "r20": RegisterDef(name="r20", size=self.address_size),
+            "r21": RegisterDef(name="r21", size=self.address_size),
+            "r22": RegisterDef(name="r22", size=self.address_size),
+            "r23": RegisterDef(name="r23", size=self.address_size),
+            "r24": RegisterDef(name="r24", size=self.address_size),
+            "r25": RegisterDef(name="r25", size=self.address_size),
+            "r26": RegisterDef(name="r26", size=self.address_size),
+            "r27": RegisterDef(name="r27", size=self.address_size),
+            "r28": RegisterDef(name="r28", size=self.address_size),
+            "r29": RegisterDef(name="r29", size=self.address_size),
+            "r30": RegisterDef(name="r30", size=self.address_size),
+            # NOTE: GPR 31 is also the base pointer
+            "r31": RegisterDef(name="r31", size=self.address_size),
+            "bp": RegisterAliasDef(
+                name="bp", parent="r31", size=self.address_size, offset=0
+            ),
+            # Floating Point Registers
+            # Always 8 bytes, regardless of self.address_size.
+            "f0": RegisterDef(name="f0", size=8),
+            "f1": RegisterDef(name="f1", size=8),
+            "f2": RegisterDef(name="f2", size=8),
+            "f3": RegisterDef(name="f3", size=8),
+            "f4": RegisterDef(name="f4", size=8),
+            "f5": RegisterDef(name="f5", size=8),
+            "f6": RegisterDef(name="f6", size=8),
+            "f7": RegisterDef(name="f7", size=8),
+            "f8": RegisterDef(name="f8", size=8),
+            "f9": RegisterDef(name="f9", size=8),
+            "f10": RegisterDef(name="f10", size=8),
+            "f11": RegisterDef(name="f11", size=8),
+            "f12": RegisterDef(name="f12", size=8),
+            "f13": RegisterDef(name="f13", size=8),
+            "f14": RegisterDef(name="f14", size=8),
+            "f15": RegisterDef(name="f15", size=8),
+            "f16": RegisterDef(name="f16", size=8),
+            "f17": RegisterDef(name="f17", size=8),
+            "f18": RegisterDef(name="f18", size=8),
+            "f19": RegisterDef(name="f19", size=8),
+            "f20": RegisterDef(name="f20", size=8),
+            "f21": RegisterDef(name="f21", size=8),
+            "f22": RegisterDef(name="f22", size=8),
+            "f23": RegisterDef(name="f23", size=8),
+            "f24": RegisterDef(name="f24", size=8),
+            "f25": RegisterDef(name="f25", size=8),
+            "f26": RegisterDef(name="f26", size=8),
+            "f27": RegisterDef(name="f27", size=8),
+            "f28": RegisterDef(name="f28", size=8),
+            "f29": RegisterDef(name="f29", size=8),
+            "f30": RegisterDef(name="f30", size=8),
+            "f31": RegisterDef(name="f31", size=8),
+            # *** Pointer Registers ***
+            # Program Counter.
+            # Not really a register; nothing can access it directly
+            "pc": RegisterDef(name="pc", size=self.address_size),
+            # Link Register
+            "lr": RegisterDef(name="lr", size=self.address_size),
+            # Counter Register
+            # Acts either as a loop index, or a branch target register
+            # Only `ctr` and `lr` can act as branch targets.
+            "ctr": RegisterDef(name="ctr", size=self.address_size),
+            # *** Condition Registers ***
+            # The actual condition register `cr` is a single 32-bit register,
+            # but it's broken into eight 4-bit fields which are accessed separately.
+            #
+            # Certain operations use specific registers by default,
+            # but some tests can specify a destination register.
+            "cr0": RegisterDef(name="cr0", size=1),  # Integer condition bits
+            "cr1": RegisterDef(name="cr1", size=1),  # Floating point condition bits
+            "cr2": RegisterDef(name="cr2", size=1),
+            "cr3": RegisterDef(name="cr3", size=1),
+            "cr4": RegisterDef(name="cr4", size=1),
+            "cr5": RegisterDef(name="cr5", size=1),
+            "cr6": RegisterDef(name="cr6", size=1),
+            "cr7": RegisterDef(name="cr7", size=1),
+            # Integer Exception Register
+            "xer": RegisterDef(name="xer", size=4),
+            # Floating Point Status and Control Register
+            "fpscr": RegisterDef(name="fpscr", size=4),
+            # TODO: This only focuses on the user-facing registrers.
+            # ppc has a huge number of privileged registers.
+            # Extend this as needed.
+        }
+
+
+class PowerPC32(PowerPCPlatformDef):
+    architecture = Architecture.POWERPC32
+
+    address_size = 4
+    capstone_mode = capstone.CS_MODE_32 | capstone.CS_MODE_BIG_ENDIAN
+
+
+class PowerPC64(PowerPCPlatformDef):
+    architecture = Architecture.POWERPC64
+
+    address_size = 8
+    capstone_mode = capstone.CS_MODE_64 | capstone.CS_MODE_BIG_ENDIAN

smallworld/platforms/defs/riscv.py

@@ -0,0 +1,257 @@
+import capstone
+
+from ..platforms import Architecture, Byteorder
+from .platformdef import PlatformDef, RegisterAliasDef, RegisterDef
+
+# NOTE: RiscV is designed to be an extensible language.
+# The core ISA is incredibly simple,
+# with a large number of optional extensions available
+# to chip manufacturers
+#
+# Support for any specific extension depends on the emulator.
+
+
+class RiscV64(PlatformDef):
+    architecture = Architecture.RISCV64
+    byteorder = Byteorder.LITTLE
+
+    address_size = 8
+
+    capstone_arch = capstone.CS_ARCH_RISCV
+    capstone_mode = capstone.CS_MODE_RISCV64
+
+    conditional_branch_mnemonics = {
+        # Core conditional branch instructions
+        "beq",
+        "bne",
+        "blt",
+        "bltu",
+        "ble",
+        "bleu",
+        "bgt",
+        "bgtu",
+        "bge",
+        "bgeu",
+    }
+
+    # RiscV core has no dedicated compare instructions
+    # (they're rather smug about this fact).
+    #
+    # - The "Zicond" extension adds conditional move instructions.
+    # - The "Zacas" extension adds compare-exchange instructions
+    compare_mnemonics = set()
+
+    pc_register = "pc"
+    sp_register = "sp"
+
+    # Special registers:
+    # - x0 is wired to zero
+    # - x1 is the link register
+    # - x2 is the stack pointer
+    # - x3 is the global pointer
+    # - x4 is the thread pointer
+    general_purpose_registers = [f"x{i}" for i in range(0, 32)]
+
+    registers = {
+        # *** General-Purpose Registers ***
+        # x0 is wired to 0, and aliased as "zero"
+        "x0": RegisterDef(name="x0", size=8),
+        "zero": RegisterAliasDef(name="zero", parent="x0", size=8, offset=0),
+        # x1 acts as the link register
+        # NOTE: ra is the official name; lr might be an angr invention.
+        "x1": RegisterDef(name="x1", size=8),
+        "ra": RegisterAliasDef(name="ra", parent="x1", size=8, offset=0),
+        # x2 acts as the stack pointer
+        "x2": RegisterDef(name="x2", size=8),
+        "sp": RegisterAliasDef(name="sp", parent="x2", size=8, offset=0),
+        # x3 acts as the global pointer
+        "x3": RegisterDef(name="x3", size=8),
+        "gp": RegisterAliasDef(name="gp", parent="x3", size=8, offset=0),
+        # x4 acts as the thread pointer
+        "x4": RegisterDef(name="x4", size=8),
+        "tp": RegisterAliasDef(name="tp", parent="x4", size=8, offset=0),
+        # x5 is a temporary register
+        "x5": RegisterDef(name="x5", size=8),
+        "t0": RegisterAliasDef(name="t0", parent="x5", size=8, offset=0),
+        # x6 is a temporary register
+        "x6": RegisterDef(name="x6", size=8),
+        "t1": RegisterAliasDef(name="t1", parent="x6", size=8, offset=0),
+        # x7 is a temporary register
+        "x7": RegisterDef(name="x7", size=8),
+        "t2": RegisterAliasDef(name="t2", parent="x7", size=8, offset=0),
+        # x8 is a callee-saved register
+        "x8": RegisterDef(name="x8", size=8),
+        "s0": RegisterAliasDef(name="s0", parent="x8", size=8, offset=0),
+        # x9 is a callee-saved register
+        "x9": RegisterDef(name="x9", size=8),
+        "s1": RegisterAliasDef(name="s1", parent="x9", size=8, offset=0),
+        # x10 is argument 0
+        "x10": RegisterDef(name="x10", size=8),
+        "a0": RegisterAliasDef(name="a0", parent="x10", size=8, offset=0),
+        # x11 is argument 1
+        "x11": RegisterDef(name="x11", size=8),
+        "a1": RegisterAliasDef(name="a1", parent="x11", size=8, offset=0),
+        # x12 is argument 2
+        "x12": RegisterDef(name="x12", size=8),
+        "a2": RegisterAliasDef(name="a2", parent="x12", size=8, offset=0),
+        # x13 is argument 3
+        "x13": RegisterDef(name="x13", size=8),
+        "a3": RegisterAliasDef(name="a3", parent="x13", size=8, offset=0),
+        # x14 is argument 4
+        "x14": RegisterDef(name="x14", size=8),
+        "a4": RegisterAliasDef(name="a4", parent="x14", size=8, offset=0),
+        # x15 is argument 5
+        "x15": RegisterDef(name="x15", size=8),
+        "a5": RegisterAliasDef(name="a5", parent="x15", size=8, offset=0),
+        # x16 is argument 6
+        "x16": RegisterDef(name="x16", size=8),
+        "a6": RegisterAliasDef(name="a6", parent="x16", size=8, offset=0),
+        # x17 is argument 7
+        "x17": RegisterDef(name="x17", size=8),
+        "a7": RegisterAliasDef(name="a7", parent="x17", size=8, offset=0),
+        # x18 is a callee-saved register
+        "x18": RegisterDef(name="x18", size=8),
+        "s2": RegisterAliasDef(name="s2", parent="x18", size=8, offset=0),
+        # x19 is a callee-saved register
+        "x19": RegisterDef(name="x19", size=8),
+        "s3": RegisterAliasDef(name="s3", parent="x19", size=8, offset=0),
+        # x20 is a callee-saved register
+        "x20": RegisterDef(name="x20", size=8),
+        "s4": RegisterAliasDef(name="s4", parent="x20", size=8, offset=0),
+        # x21 is a callee-saved register
+        "x21": RegisterDef(name="x21", size=8),
+        "s5": RegisterAliasDef(name="s5", parent="x21", size=8, offset=0),
+        # x22 is a callee-saved register
+        "x22": RegisterDef(name="x22", size=8),
+        "s6": RegisterAliasDef(name="s6", parent="x22", size=8, offset=0),
+        # x23 is a callee-saved register
+        "x23": RegisterDef(name="x23", size=8),
+        "s7": RegisterAliasDef(name="s7", parent="x23", size=8, offset=0),
+        # x24 is a callee-saved register
+        "x24": RegisterDef(name="x24", size=8),
+        "s8": RegisterAliasDef(name="s8", parent="x24", size=8, offset=0),
+        # x25 is a callee-saved register
+        "x25": RegisterDef(name="x25", size=8),
+        "s9": RegisterAliasDef(name="s9", parent="x25", size=8, offset=0),
+        # x26 is a callee-saved register
+        "x26": RegisterDef(name="x26", size=8),
+        "s10": RegisterAliasDef(name="s10", parent="x26", size=8, offset=0),
+        # x27 is a callee-saved register
+        "x27": RegisterDef(name="x27", size=8),
+        "s11": RegisterAliasDef(name="s11", parent="x27", size=8, offset=0),
+        # x28 is a temporary register
+        "x28": RegisterDef(name="x28", size=8),
+        "t3": RegisterAliasDef(name="t3", parent="x28", size=8, offset=0),
+        # x29 is a temporary register
+        "x29": RegisterDef(name="x29", size=8),
+        "t4": RegisterAliasDef(name="t4", parent="x29", size=8, offset=0),
+        # x30 is a temporary register
+        "x30": RegisterDef(name="x30", size=8),
+        "t5": RegisterAliasDef(name="t5", parent="x30", size=8, offset=0),
+        # x31 is a temporary register
+        "x31": RegisterDef(name="x31", size=8),
+        "t6": RegisterAliasDef(name="t6", parent="x31", size=8, offset=0),
+        # *** Program Counter ***
+        "pc": RegisterDef(name="pc", size=8),
+        # *** Floating-Point Registers ***
+        # f0 is a temporary register
+        "f0": RegisterDef(name="f0", size=8),
+        "ft0": RegisterAliasDef(name="ft0", parent="f0", size=8, offset=0),
+        # f1 is a temporary register
+        "f1": RegisterDef(name="f1", size=8),
+        "ft1": RegisterAliasDef(name="ft1", parent="f1", size=8, offset=0),
+        # f2 is a temporary register
+        "f2": RegisterDef(name="f2", size=8),
+        "ft2": RegisterAliasDef(name="ft2", parent="f2", size=8, offset=0),
+        # f3 is a temporary register
+        "f3": RegisterDef(name="f3", size=8),
+        "ft3": RegisterAliasDef(name="ft3", parent="f3", size=8, offset=0),
+        # f4 is a temporary register
+        "f4": RegisterDef(name="f4", size=8),
+        "ft4": RegisterAliasDef(name="ft4", parent="f4", size=8, offset=0),
+        # f5 is a temporary register
+        "f5": RegisterDef(name="f5", size=8),
+        "ft5": RegisterAliasDef(name="ft5", parent="f5", size=8, offset=0),
+        # f6 is a temporary register
+        "f6": RegisterDef(name="f6", size=8),
+        "ft6": RegisterAliasDef(name="ft6", parent="f6", size=8, offset=0),
+        # f7 is a temporary register
+        "f7": RegisterDef(name="f7", size=8),
+        "ft7": RegisterAliasDef(name="ft7", parent="f7", size=8, offset=0),
+        # f8 is a callee saved register
+        "f8": RegisterDef(name="f8", size=8),
+        "fs0": RegisterAliasDef(name="fs0", parent="f8", size=8, offset=0),
+        # f9 is a callee saved register
+        "f9": RegisterDef(name="f9", size=8),
+        "fs1": RegisterAliasDef(name="fs1", parent="f9", size=8, offset=0),
+        # f10 is argument 0
+        "f10": RegisterDef(name="f10", size=8),
+        "fa0": RegisterAliasDef(name="fa0", parent="f10", size=8, offset=0),
+        # f11 is argument 1
+        "f11": RegisterDef(name="f11", size=8),
+        "fa1": RegisterAliasDef(name="fa1", parent="f11", size=8, offset=0),
+        # f12 is argument 2
+        "f12": RegisterDef(name="f12", size=8),
+        "fa2": RegisterAliasDef(name="fa2", parent="f12", size=8, offset=0),
+        # f13 is argument 3
+        "f13": RegisterDef(name="f13", size=8),
+        "fa3": RegisterAliasDef(name="fa3", parent="f13", size=8, offset=0),
+        # f14 is argument 4
+        "f14": RegisterDef(name="f14", size=8),
+        "fa4": RegisterAliasDef(name="fa4", parent="f14", size=8, offset=0),
+        # f15 is argument 5
+        "f15": RegisterDef(name="f15", size=8),
+        "fa5": RegisterAliasDef(name="fa5", parent="f15", size=8, offset=0),
+        # f16 is argument 6
+        "f16": RegisterDef(name="f16", size=8),
+        "fa6": RegisterAliasDef(name="fa6", parent="f16", size=8, offset=0),
+        # f7 is argument 7
+        "f17": RegisterDef(name="f17", size=8),
+        "fa7": RegisterAliasDef(name="fa7", parent="f17", size=8, offset=0),
+        # f18 is a callee-saved register
+        "f18": RegisterDef(name="f18", size=8),
+        "fs2": RegisterAliasDef(name="fs2", parent="f18", size=8, offset=0),
+        # f19 is a callee-saved register
+        "f19": RegisterDef(name="f19", size=8),
+        "fs3": RegisterAliasDef(name="fs3", parent="f19", size=8, offset=0),
+        # f20 is a callee-saved register
+        "f20": RegisterDef(name="f20", size=8),
+        "fs4": RegisterAliasDef(name="fs4", parent="f20", size=8, offset=0),
+        # f21 is a callee-saved register
+        "f21": RegisterDef(name="f21", size=8),
+        "fs5": RegisterAliasDef(name="fs5", parent="f21", size=8, offset=0),
+        # f22 is a callee-saved register
+        "f22": RegisterDef(name="f22", size=8),
+        "fs6": RegisterAliasDef(name="fs6", parent="f22", size=8, offset=0),
+        # f23 is a callee-saved register
+        "f23": RegisterDef(name="f23", size=8),
+        "fs7": RegisterAliasDef(name="fs7", parent="f23", size=8, offset=0),
+        # f24 is a callee-saved register
+        "f24": RegisterDef(name="f24", size=8),
+        "fs8": RegisterAliasDef(name="fs8", parent="f24", size=8, offset=0),
+        # f25 is a callee-saved register
+        "f25": RegisterDef(name="f25", size=8),
+        "fs9": RegisterAliasDef(name="fs9", parent="f25", size=8, offset=0),
+        # f26 is a callee-saved register
+        "f26": RegisterDef(name="f26", size=8),
+        "fs10": RegisterAliasDef(name="fs10", parent="f26", size=8, offset=0),
+        # f27 is a callee-saved register
+        "f27": RegisterDef(name="f27", size=8),
+        "fs11": RegisterAliasDef(name="fs11", parent="f27", size=8, offset=0),
+        # f28 is a temporary register
+        "f28": RegisterDef(name="f28", size=8),
+        "ft8": RegisterAliasDef(name="ft8", parent="f28", size=8, offset=0),
+        # f29 is a temporary register
+        "f29": RegisterDef(name="f29", size=8),
+        "ft9": RegisterAliasDef(name="ft9", parent="f29", size=8, offset=0),
+        # f30 is a temporary register
+        "f30": RegisterDef(name="f30", size=8),
+        "ft10": RegisterAliasDef(name="ft10", parent="f30", size=8, offset=0),
+        # f31 is a temporary register
+        "f31": RegisterDef(name="f31", size=8),
+        "ft11": RegisterAliasDef(name="ft11", parent="f31", size=8, offset=0),
+        # *** Vector Registers ***
+        # NOTE: These exist, but are not supported
+        # *** Control and Status Registers ***
+        # NOTE: These exist, but aren't supported.
+    }