smallworld-re 1.0.3__py3-none-any.whl → 2.0.0__py3-none-any.whl

smallworld/emulators/unicorn/machdefs/i386.py

@@ -1,4 +1,3 @@
-import capstone
 import unicorn
 
 from ....platforms import Architecture, Byteorder
@@ -14,101 +13,96 @@ class i386MachineDef(UnicornMachineDef):
     uc_arch = unicorn.UC_ARCH_X86
     uc_mode = unicorn.UC_MODE_32
 
-    cs_arch = capstone.CS_ARCH_X86
-    cs_mode = capstone.CS_MODE_32
-
-    pc_reg = "eip"
-
     _registers = {
         # *** General Purpose Registers ***
-        "eax": (unicorn.x86_const.UC_X86_REG_EAX, "eax", 4, 0),
-        "ax": (unicorn.x86_const.UC_X86_REG_AX, "eax", 2, 0),
-        "al": (unicorn.x86_const.UC_X86_REG_AL, "eax", 1, 0),
-        "ah": (unicorn.x86_const.UC_X86_REG_AH, "eax", 1, 1),
-        "ebx": (unicorn.x86_const.UC_X86_REG_EBX, "ebx", 4, 0),
-        "bx": (unicorn.x86_const.UC_X86_REG_BX, "ebx", 2, 0),
-        "bl": (unicorn.x86_const.UC_X86_REG_BL, "ebx", 1, 0),
-        "bh": (unicorn.x86_const.UC_X86_REG_BH, "ebx", 1, 1),
-        "ecx": (unicorn.x86_const.UC_X86_REG_ECX, "ecx", 4, 0),
-        "cx": (unicorn.x86_const.UC_X86_REG_CX, "ecx", 2, 0),
-        "cl": (unicorn.x86_const.UC_X86_REG_CL, "ecx", 1, 0),
-        "ch": (unicorn.x86_const.UC_X86_REG_CH, "ecx", 1, 1),
-        "edx": (unicorn.x86_const.UC_X86_REG_EDX, "edx", 4, 0),
-        "dx": (unicorn.x86_const.UC_X86_REG_DX, "edx", 2, 0),
-        "dl": (unicorn.x86_const.UC_X86_REG_DL, "edx", 1, 0),
-        "dh": (unicorn.x86_const.UC_X86_REG_DH, "edx", 1, 1),
-        "esi": (unicorn.x86_const.UC_X86_REG_ESI, "esi", 4, 0),
-        "si": (unicorn.x86_const.UC_X86_REG_SI, "esi", 2, 0),
-        "sil": (unicorn.x86_const.UC_X86_REG_SIL, "esi", 1, 0),
-        "edi": (unicorn.x86_const.UC_X86_REG_EDI, "edi", 4, 0),
-        "di": (unicorn.x86_const.UC_X86_REG_DI, "edi", 2, 0),
-        "dil": (unicorn.x86_const.UC_X86_REG_DIL, "edi", 1, 0),
-        "ebp": (unicorn.x86_const.UC_X86_REG_EBP, "ebp", 4, 0),
-        "bp": (unicorn.x86_const.UC_X86_REG_BP, "ebp", 2, 0),
-        "bpl": (unicorn.x86_const.UC_X86_REG_BPL, "ebp", 1, 0),
-        "esp": (unicorn.x86_const.UC_X86_REG_ESP, "esp", 4, 0),
-        "sp": (unicorn.x86_const.UC_X86_REG_SP, "esp", 2, 0),
-        "spl": (unicorn.x86_const.UC_X86_REG_SPL, "esp", 1, 0),
+        "eax": unicorn.x86_const.UC_X86_REG_EAX,
+        "ax": unicorn.x86_const.UC_X86_REG_AX,
+        "al": unicorn.x86_const.UC_X86_REG_AL,
+        "ah": unicorn.x86_const.UC_X86_REG_AH,
+        "ebx": unicorn.x86_const.UC_X86_REG_EBX,
+        "bx": unicorn.x86_const.UC_X86_REG_BX,
+        "bl": unicorn.x86_const.UC_X86_REG_BL,
+        "bh": unicorn.x86_const.UC_X86_REG_BH,
+        "ecx": unicorn.x86_const.UC_X86_REG_ECX,
+        "cx": unicorn.x86_const.UC_X86_REG_CX,
+        "cl": unicorn.x86_const.UC_X86_REG_CL,
+        "ch": unicorn.x86_const.UC_X86_REG_CH,
+        "edx": unicorn.x86_const.UC_X86_REG_EDX,
+        "dx": unicorn.x86_const.UC_X86_REG_DX,
+        "dl": unicorn.x86_const.UC_X86_REG_DL,
+        "dh": unicorn.x86_const.UC_X86_REG_DH,
+        "esi": unicorn.x86_const.UC_X86_REG_ESI,
+        "si": unicorn.x86_const.UC_X86_REG_SI,
+        "sil": unicorn.x86_const.UC_X86_REG_SIL,
+        "edi": unicorn.x86_const.UC_X86_REG_EDI,
+        "di": unicorn.x86_const.UC_X86_REG_DI,
+        "dil": unicorn.x86_const.UC_X86_REG_DIL,
+        "ebp": unicorn.x86_const.UC_X86_REG_EBP,
+        "bp": unicorn.x86_const.UC_X86_REG_BP,
+        "bpl": unicorn.x86_const.UC_X86_REG_BPL,
+        "esp": unicorn.x86_const.UC_X86_REG_ESP,
+        "sp": unicorn.x86_const.UC_X86_REG_SP,
+        "spl": unicorn.x86_const.UC_X86_REG_SPL,
         # *** Instruction Pointer ***
-        "eip": (unicorn.x86_const.UC_X86_REG_EIP, "eip", 4, 0),
-        "ip": (unicorn.x86_const.UC_X86_REG_IP, "eip", 2, 0),
+        "eip": unicorn.x86_const.UC_X86_REG_EIP,
+        "ip": unicorn.x86_const.UC_X86_REG_IP,
         # *** Segment Registers ***
-        "cs": (unicorn.x86_const.UC_X86_REG_CS, "cs", 2, 0),
-        "ss": (unicorn.x86_const.UC_X86_REG_SS, "ss", 2, 0),
-        "ds": (unicorn.x86_const.UC_X86_REG_DS, "ds", 2, 0),
-        "es": (unicorn.x86_const.UC_X86_REG_ES, "es", 2, 0),
-        "fs": (unicorn.x86_const.UC_X86_REG_FS, "fs", 2, 0),
-        "gs": (unicorn.x86_const.UC_X86_REG_GS, "gs", 2, 0),
+        "cs": unicorn.x86_const.UC_X86_REG_CS,
+        "ss": unicorn.x86_const.UC_X86_REG_SS,
+        "ds": unicorn.x86_const.UC_X86_REG_DS,
+        "es": unicorn.x86_const.UC_X86_REG_ES,
+        "fs": unicorn.x86_const.UC_X86_REG_FS,
+        "gs": unicorn.x86_const.UC_X86_REG_GS,
         # *** Flags Registers ***
-        "eflags": (unicorn.x86_const.UC_X86_REG_EFLAGS, "eflags", 4, 0),
-        "flags": (unicorn.x86_const.UC_X86_REG_FLAGS, "eflags", 2, 0),
+        "eflags": unicorn.x86_const.UC_X86_REG_EFLAGS,
+        "flags": unicorn.x86_const.UC_X86_REG_FLAGS,
         # *** Control Registers ***
-        "cr0": (unicorn.x86_const.UC_X86_REG_CR0, "cr0", 4, 0),
-        "cr1": (unicorn.x86_const.UC_X86_REG_CR1, "cr1", 4, 0),
-        "cr2": (unicorn.x86_const.UC_X86_REG_CR2, "cr2", 4, 0),
-        "cr3": (unicorn.x86_const.UC_X86_REG_CR3, "cr3", 4, 0),
-        "cr4": (unicorn.x86_const.UC_X86_REG_CR4, "cr4", 4, 0),
+        "cr0": unicorn.x86_const.UC_X86_REG_CR0,
+        "cr1": unicorn.x86_const.UC_X86_REG_CR1,
+        "cr2": unicorn.x86_const.UC_X86_REG_CR2,
+        "cr3": unicorn.x86_const.UC_X86_REG_CR3,
+        "cr4": unicorn.x86_const.UC_X86_REG_CR4,
         # NOTE: I've got conflicting reports whether cr8 exists in i386.
-        "cr8": (unicorn.x86_const.UC_X86_REG_INVALID, "cr8", 4, 0),
+        "cr8": unicorn.x86_const.UC_X86_REG_INVALID,
         # *** Debug Registers ***
-        "dr0": (unicorn.x86_const.UC_X86_REG_DR0, "dr0", 4, 0),
-        "dr1": (unicorn.x86_const.UC_X86_REG_DR1, "dr1", 4, 0),
-        "dr2": (unicorn.x86_const.UC_X86_REG_DR2, "dr2", 4, 0),
-        "dr3": (unicorn.x86_const.UC_X86_REG_DR3, "dr3", 4, 0),
-        "dr6": (unicorn.x86_const.UC_X86_REG_DR6, "dr6", 4, 0),
-        "dr7": (unicorn.x86_const.UC_X86_REG_DR7, "dr7", 4, 0),
+        "dr0": unicorn.x86_const.UC_X86_REG_DR0,
+        "dr1": unicorn.x86_const.UC_X86_REG_DR1,
+        "dr2": unicorn.x86_const.UC_X86_REG_DR2,
+        "dr3": unicorn.x86_const.UC_X86_REG_DR3,
+        "dr6": unicorn.x86_const.UC_X86_REG_DR6,
+        "dr7": unicorn.x86_const.UC_X86_REG_DR7,
         # *** Descriptor Table Registers
         # NOTE: Yes, this is 6 bytes; 2 byte segment selector plus 4 byte offset
-        "gdtr": (unicorn.x86_const.UC_X86_REG_GDTR, "gdtr", 6, 0),
-        "idtr": (unicorn.x86_const.UC_X86_REG_IDTR, "idtr", 6, 0),
-        "ldtr": (unicorn.x86_const.UC_X86_REG_LDTR, "ldtr", 6, 0),
+        "gdtr": unicorn.x86_const.UC_X86_REG_GDTR,
+        "idtr": unicorn.x86_const.UC_X86_REG_IDTR,
+        "ldtr": unicorn.x86_const.UC_X86_REG_LDTR,
         # *** Task Register ***
         # NOTE: Yes, this is 6 bytes; 2 byte segment selector plus 4 byte offset
-        "tr": (unicorn.x86_const.UC_X86_REG_TR, "tr", 6, 0),
+        "tr": unicorn.x86_const.UC_X86_REG_TR,
         # *** x87 registers ***
         # NOTE: x87 is supported by Unicorn, but not by SmallWorld.
         # Values are represented as tuples (exponent: int, mantissa: int).
         # If you need x87 support, open a ticket.
-        "fpr0": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr0", 10, 0),
-        "fpr1": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr1", 10, 0),
-        "fpr2": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr2", 10, 0),
-        "fpr3": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr3", 10, 0),
-        "fpr4": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr4", 10, 0),
-        "fpr5": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr5", 10, 0),
-        "fpr6": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr6", 10, 0),
-        "fpr7": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr7", 10, 0),
+        "fpr0": unicorn.x86_const.UC_X86_REG_INVALID,
+        "fpr1": unicorn.x86_const.UC_X86_REG_INVALID,
+        "fpr2": unicorn.x86_const.UC_X86_REG_INVALID,
+        "fpr3": unicorn.x86_const.UC_X86_REG_INVALID,
+        "fpr4": unicorn.x86_const.UC_X86_REG_INVALID,
+        "fpr5": unicorn.x86_const.UC_X86_REG_INVALID,
+        "fpr6": unicorn.x86_const.UC_X86_REG_INVALID,
+        "fpr7": unicorn.x86_const.UC_X86_REG_INVALID,
         # x87 Control Register
-        "fctrl": (unicorn.x86_const.UC_X86_REG_FPCW, "fctrl", 2, 0),
+        "fctrl": unicorn.x86_const.UC_X86_REG_FPCW,
         # x87 Status Register
-        "fstat": (unicorn.x86_const.UC_X86_REG_FPSW, "fstat", 2, 0),
+        "fstat": unicorn.x86_const.UC_X86_REG_FPSW,
         # x87 Tag Register
-        "ftag": (unicorn.x86_const.UC_X86_REG_FPTAG, "ftag", 2, 0),
+        "ftag": unicorn.x86_const.UC_X86_REG_FPTAG,
         # x87 Last Instruction Register
-        "fip": (unicorn.x86_const.UC_X86_REG_FIP, "fip", 8, 0),
+        "fip": unicorn.x86_const.UC_X86_REG_FIP,
         # x87 Last Operand Pointer
-        "fdp": (unicorn.x86_const.UC_X86_REG_FDP, "fdp", 8, 0),
+        "fdp": unicorn.x86_const.UC_X86_REG_FDP,
         # x87 Last Opcode
-        "fop": (unicorn.x86_const.UC_X86_REG_FOP, "fop", 2, 0),
+        "fop": unicorn.x86_const.UC_X86_REG_FOP,
         # NOTE: Docs disagree on the format of fip and fdp.
         # One source describes them as 48-bit offset-plus-segment,
         # the other describes them as 64-bit.
@@ -117,21 +111,21 @@ class i386MachineDef(UnicornMachineDef):
         # *** MMX Registers ***
         # NOTE: The MMX registers are aliases for the low 8 bytes of the x87 registers.
         # The two subsystems cannot be used simultaneously.
-        "mm0": (unicorn.x86_const.UC_X86_REG_MM0, "fpr0", 8, 0),
-        "mm1": (unicorn.x86_const.UC_X86_REG_MM1, "fpr1", 8, 0),
-        "mm2": (unicorn.x86_const.UC_X86_REG_MM2, "fpr2", 8, 0),
-        "mm3": (unicorn.x86_const.UC_X86_REG_MM3, "fpr3", 8, 0),
-        "mm4": (unicorn.x86_const.UC_X86_REG_MM4, "fpr4", 8, 0),
-        "mm5": (unicorn.x86_const.UC_X86_REG_MM5, "fpr5", 8, 0),
-        "mm6": (unicorn.x86_const.UC_X86_REG_MM6, "fpr6", 8, 0),
-        "mm7": (unicorn.x86_const.UC_X86_REG_MM7, "fpr7", 8, 0),
+        "mm0": unicorn.x86_const.UC_X86_REG_MM0,
+        "mm1": unicorn.x86_const.UC_X86_REG_MM1,
+        "mm2": unicorn.x86_const.UC_X86_REG_MM2,
+        "mm3": unicorn.x86_const.UC_X86_REG_MM3,
+        "mm4": unicorn.x86_const.UC_X86_REG_MM4,
+        "mm5": unicorn.x86_const.UC_X86_REG_MM5,
+        "mm6": unicorn.x86_const.UC_X86_REG_MM6,
+        "mm7": unicorn.x86_const.UC_X86_REG_MM7,
         # *** SSE Registers ***
-        "xmm0": (unicorn.x86_const.UC_X86_REG_XMM0, "xmm0", 16, 0),
-        "xmm1": (unicorn.x86_const.UC_X86_REG_XMM1, "xmm1", 16, 0),
-        "xmm2": (unicorn.x86_const.UC_X86_REG_XMM2, "xmm2", 16, 0),
-        "xmm3": (unicorn.x86_const.UC_X86_REG_XMM3, "xmm3", 16, 0),
-        "xmm4": (unicorn.x86_const.UC_X86_REG_XMM4, "xmm4", 16, 0),
-        "xmm5": (unicorn.x86_const.UC_X86_REG_XMM5, "xmm5", 16, 0),
-        "xmm6": (unicorn.x86_const.UC_X86_REG_XMM6, "xmm6", 16, 0),
-        "xmm7": (unicorn.x86_const.UC_X86_REG_XMM7, "xmm7", 16, 0),
+        "xmm0": unicorn.x86_const.UC_X86_REG_XMM0,
+        "xmm1": unicorn.x86_const.UC_X86_REG_XMM1,
+        "xmm2": unicorn.x86_const.UC_X86_REG_XMM2,
+        "xmm3": unicorn.x86_const.UC_X86_REG_XMM3,
+        "xmm4": unicorn.x86_const.UC_X86_REG_XMM4,
+        "xmm5": unicorn.x86_const.UC_X86_REG_XMM5,
+        "xmm6": unicorn.x86_const.UC_X86_REG_XMM6,
+        "xmm7": unicorn.x86_const.UC_X86_REG_XMM7,
     }

smallworld/emulators/unicorn/machdefs/machdef.py

@@ -37,30 +37,9 @@ class UnicornMachineDef(metaclass=abc.ABCMeta):
         """
         return 0
 
-    @property
-    @abc.abstractmethod
-    def cs_arch(self) -> int:
-        """The capstone arch ID"""
-        return 0
-
-    @property
-    @abc.abstractmethod
-    def cs_mode(self) -> int:
-        """The capstone mode ID
-
-        This must include an byteorder flag
-        """
-        return 0
-
-    @property
-    @abc.abstractmethod
-    def pc_reg(self) -> str:
-        """The name of the Program Counter register for this machine"""
-        return ""
-
-    _registers: typing.Dict[str, typing.Tuple[typing.Any, str, int, int]] = {}
+    _registers: typing.Dict[str, int] = {}
 
-    def uc_reg(self, name: str) -> typing.Tuple[typing.Any, str, int, int]:
+    def uc_reg(self, name: str) -> int:
         """Convert a register name to unicorn constant
 
         This must cover all names defined in the CPU state model

smallworld/emulators/unicorn/machdefs/mips.py

@@ -1,4 +1,3 @@
-import capstone
 import unicorn
 
 from ....platforms import Architecture, Byteorder
@@ -13,134 +12,129 @@ class MIPSMachineDef(UnicornMachineDef):
     uc_arch = unicorn.UC_ARCH_MIPS
     uc_mode = unicorn.UC_MODE_MIPS32
 
-    cs_arch = capstone.CS_ARCH_MIPS
-    cs_mode = capstone.CS_MODE_MIPS32
-
-    pc_reg = "pc"
-
     def __init__(self):
         self._registers = {
             # *** General-Purpose Registers ***
             # Assembler Temporary Register
-            "at": (unicorn.mips_const.UC_MIPS_REG_AT, "at", 0, 4),
-            "1": (unicorn.mips_const.UC_MIPS_REG_1, "at", 0, 4),
+            "at": unicorn.mips_const.UC_MIPS_REG_AT,
+            "1": unicorn.mips_const.UC_MIPS_REG_1,
             # Return Value Registers
-            "v0": (unicorn.mips_const.UC_MIPS_REG_V0, "v0", 0, 4),
-            "2": (unicorn.mips_const.UC_MIPS_REG_2, "v0", 0, 4),
-            "v1": (unicorn.mips_const.UC_MIPS_REG_V1, "v1", 0, 4),
-            "3": (unicorn.mips_const.UC_MIPS_REG_3, "v1", 0, 4),
+            "v0": unicorn.mips_const.UC_MIPS_REG_V0,
+            "2": unicorn.mips_const.UC_MIPS_REG_2,
+            "v1": unicorn.mips_const.UC_MIPS_REG_V1,
+            "3": unicorn.mips_const.UC_MIPS_REG_3,
             # Argument Registers
-            "a0": (unicorn.mips_const.UC_MIPS_REG_A0, "a0", 0, 4),
-            "4": (unicorn.mips_const.UC_MIPS_REG_4, "a0", 0, 4),
-            "a1": (unicorn.mips_const.UC_MIPS_REG_A1, "a1", 0, 4),
-            "5": (unicorn.mips_const.UC_MIPS_REG_5, "a1", 0, 4),
-            "a2": (unicorn.mips_const.UC_MIPS_REG_A2, "a2", 0, 4),
-            "6": (unicorn.mips_const.UC_MIPS_REG_6, "a2", 0, 4),
-            "a3": (unicorn.mips_const.UC_MIPS_REG_A3, "a3", 0, 4),
-            "7": (unicorn.mips_const.UC_MIPS_REG_7, "a3", 0, 4),
+            "a0": unicorn.mips_const.UC_MIPS_REG_A0,
+            "4": unicorn.mips_const.UC_MIPS_REG_4,
+            "a1": unicorn.mips_const.UC_MIPS_REG_A1,
+            "5": unicorn.mips_const.UC_MIPS_REG_5,
+            "a2": unicorn.mips_const.UC_MIPS_REG_A2,
+            "6": unicorn.mips_const.UC_MIPS_REG_6,
+            "a3": unicorn.mips_const.UC_MIPS_REG_A3,
+            "7": unicorn.mips_const.UC_MIPS_REG_7,
             # Temporary Registers
-            "t0": (unicorn.mips_const.UC_MIPS_REG_T0, "t0", 0, 4),
-            "8": (unicorn.mips_const.UC_MIPS_REG_8, "t0", 0, 4),
-            "t1": (unicorn.mips_const.UC_MIPS_REG_T1, "t1", 0, 4),
-            "9": (unicorn.mips_const.UC_MIPS_REG_9, "t1", 0, 4),
-            "t2": (unicorn.mips_const.UC_MIPS_REG_T2, "t2", 0, 4),
-            "10": (unicorn.mips_const.UC_MIPS_REG_10, "t2", 0, 4),
-            "t3": (unicorn.mips_const.UC_MIPS_REG_T3, "t3", 0, 4),
-            "11": (unicorn.mips_const.UC_MIPS_REG_11, "t3", 0, 4),
-            "t4": (unicorn.mips_const.UC_MIPS_REG_T4, "t4", 0, 4),
-            "12": (unicorn.mips_const.UC_MIPS_REG_12, "t4", 0, 4),
-            "t5": (unicorn.mips_const.UC_MIPS_REG_T5, "t5", 0, 4),
-            "13": (unicorn.mips_const.UC_MIPS_REG_13, "t5", 0, 4),
-            "t6": (unicorn.mips_const.UC_MIPS_REG_T6, "t6", 0, 4),
-            "14": (unicorn.mips_const.UC_MIPS_REG_14, "t6", 0, 4),
-            "t7": (unicorn.mips_const.UC_MIPS_REG_T7, "t7", 0, 4),
-            "15": (unicorn.mips_const.UC_MIPS_REG_15, "t7", 0, 4),
-            "t8": (unicorn.mips_const.UC_MIPS_REG_T8, "t8", 0, 4),
-            "24": (unicorn.mips_const.UC_MIPS_REG_24, "t8", 0, 4),
-            "t9": (unicorn.mips_const.UC_MIPS_REG_T9, "t9", 0, 4),
-            "25": (unicorn.mips_const.UC_MIPS_REG_25, "t9", 0, 4),
+            "t0": unicorn.mips_const.UC_MIPS_REG_T0,
+            "8": unicorn.mips_const.UC_MIPS_REG_8,
+            "t1": unicorn.mips_const.UC_MIPS_REG_T1,
+            "9": unicorn.mips_const.UC_MIPS_REG_9,
+            "t2": unicorn.mips_const.UC_MIPS_REG_T2,
+            "10": unicorn.mips_const.UC_MIPS_REG_10,
+            "t3": unicorn.mips_const.UC_MIPS_REG_T3,
+            "11": unicorn.mips_const.UC_MIPS_REG_11,
+            "t4": unicorn.mips_const.UC_MIPS_REG_T4,
+            "12": unicorn.mips_const.UC_MIPS_REG_12,
+            "t5": unicorn.mips_const.UC_MIPS_REG_T5,
+            "13": unicorn.mips_const.UC_MIPS_REG_13,
+            "t6": unicorn.mips_const.UC_MIPS_REG_T6,
+            "14": unicorn.mips_const.UC_MIPS_REG_14,
+            "t7": unicorn.mips_const.UC_MIPS_REG_T7,
+            "15": unicorn.mips_const.UC_MIPS_REG_15,
+            "t8": unicorn.mips_const.UC_MIPS_REG_T8,
+            "24": unicorn.mips_const.UC_MIPS_REG_24,
+            "t9": unicorn.mips_const.UC_MIPS_REG_T9,
+            "25": unicorn.mips_const.UC_MIPS_REG_25,
             # Saved Registers
-            "s0": (unicorn.mips_const.UC_MIPS_REG_S0, "s0", 0, 4),
-            "16": (unicorn.mips_const.UC_MIPS_REG_16, "s0", 0, 4),
-            "s1": (unicorn.mips_const.UC_MIPS_REG_S1, "s1", 0, 4),
-            "17": (unicorn.mips_const.UC_MIPS_REG_17, "s1", 0, 4),
-            "s2": (unicorn.mips_const.UC_MIPS_REG_S2, "s2", 0, 4),
-            "18": (unicorn.mips_const.UC_MIPS_REG_18, "s2", 0, 4),
-            "s3": (unicorn.mips_const.UC_MIPS_REG_S3, "s3", 0, 4),
-            "19": (unicorn.mips_const.UC_MIPS_REG_19, "s3", 0, 4),
-            "s4": (unicorn.mips_const.UC_MIPS_REG_S4, "s4", 0, 4),
-            "20": (unicorn.mips_const.UC_MIPS_REG_20, "s4", 0, 4),
-            "s5": (unicorn.mips_const.UC_MIPS_REG_S5, "s5", 0, 4),
-            "21": (unicorn.mips_const.UC_MIPS_REG_21, "s5", 0, 4),
-            "s6": (unicorn.mips_const.UC_MIPS_REG_S6, "s6", 0, 4),
-            "22": (unicorn.mips_const.UC_MIPS_REG_22, "s6", 0, 4),
-            "s7": (unicorn.mips_const.UC_MIPS_REG_S7, "s7", 0, 4),
-            "23": (unicorn.mips_const.UC_MIPS_REG_23, "s7", 0, 4),
+            "s0": unicorn.mips_const.UC_MIPS_REG_S0,
+            "16": unicorn.mips_const.UC_MIPS_REG_16,
+            "s1": unicorn.mips_const.UC_MIPS_REG_S1,
+            "17": unicorn.mips_const.UC_MIPS_REG_17,
+            "s2": unicorn.mips_const.UC_MIPS_REG_S2,
+            "18": unicorn.mips_const.UC_MIPS_REG_18,
+            "s3": unicorn.mips_const.UC_MIPS_REG_S3,
+            "19": unicorn.mips_const.UC_MIPS_REG_19,
+            "s4": unicorn.mips_const.UC_MIPS_REG_S4,
+            "20": unicorn.mips_const.UC_MIPS_REG_20,
+            "s5": unicorn.mips_const.UC_MIPS_REG_S5,
+            "21": unicorn.mips_const.UC_MIPS_REG_21,
+            "s6": unicorn.mips_const.UC_MIPS_REG_S6,
+            "22": unicorn.mips_const.UC_MIPS_REG_22,
+            "s7": unicorn.mips_const.UC_MIPS_REG_S7,
+            "23": unicorn.mips_const.UC_MIPS_REG_23,
             # NOTE: Register 30 used to be FP, is now also s8
-            "s8": (unicorn.mips_const.UC_MIPS_REG_S8, "s8", 0, 4),
-            "fp": (unicorn.mips_const.UC_MIPS_REG_FP, "s8", 0, 4),
-            "30": (unicorn.mips_const.UC_MIPS_REG_30, "s8", 0, 4),
+            "s8": unicorn.mips_const.UC_MIPS_REG_S8,
+            "fp": unicorn.mips_const.UC_MIPS_REG_FP,
+            "30": unicorn.mips_const.UC_MIPS_REG_30,
             # Kernel-reserved registers
-            "k0": (unicorn.mips_const.UC_MIPS_REG_K0, "k0", 0, 4),
-            "26": (unicorn.mips_const.UC_MIPS_REG_26, "k0", 0, 4),
-            "k1": (unicorn.mips_const.UC_MIPS_REG_K1, "k1", 0, 4),
-            "27": (unicorn.mips_const.UC_MIPS_REG_27, "k1", 0, 4),
+            "k0": unicorn.mips_const.UC_MIPS_REG_K0,
+            "26": unicorn.mips_const.UC_MIPS_REG_26,
+            "k1": unicorn.mips_const.UC_MIPS_REG_K1,
+            "27": unicorn.mips_const.UC_MIPS_REG_27,
             # *** Pointer Registers ***
             # Zero Register
-            "zero": (unicorn.mips_const.UC_MIPS_REG_ZERO, "zero", 0, 4),
-            "0": (unicorn.mips_const.UC_MIPS_REG_0, "zero", 0, 4),
+            "zero": unicorn.mips_const.UC_MIPS_REG_ZERO,
+            "0": unicorn.mips_const.UC_MIPS_REG_0,
             # Global Pointer Register
-            "gp": (unicorn.mips_const.UC_MIPS_REG_GP, "gp", 0, 4),
-            "28": (unicorn.mips_const.UC_MIPS_REG_28, "gp", 0, 4),
+            "gp": unicorn.mips_const.UC_MIPS_REG_GP,
+            "28": unicorn.mips_const.UC_MIPS_REG_28,
             # Stack Pointer Register
-            "sp": (unicorn.mips_const.UC_MIPS_REG_SP, "sp", 0, 4),
-            "29": (unicorn.mips_const.UC_MIPS_REG_29, "sp", 0, 4),
+            "sp": unicorn.mips_const.UC_MIPS_REG_SP,
+            "29": unicorn.mips_const.UC_MIPS_REG_29,
             # Return Address Register
-            "ra": (unicorn.mips_const.UC_MIPS_REG_RA, "ra", 0, 4),
-            "31": (unicorn.mips_const.UC_MIPS_REG_31, "ra", 0, 4),
+            "ra": unicorn.mips_const.UC_MIPS_REG_RA,
+            "31": unicorn.mips_const.UC_MIPS_REG_31,
             # Program Counter
-            "pc": (unicorn.mips_const.UC_MIPS_REG_PC, "pc", 0, 4),
+            "pc": unicorn.mips_const.UC_MIPS_REG_PC,
             # *** Floating-point Registers ***
-            "f0": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f0", 0, 4),
-            "f1": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f1", 0, 4),
-            "f2": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f2", 0, 4),
-            "f3": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f3", 0, 4),
-            "f4": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f4", 0, 4),
-            "f5": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f5", 0, 4),
-            "f6": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f6", 0, 4),
-            "f7": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f7", 0, 4),
-            "f8": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f8", 0, 4),
-            "f9": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f9", 0, 4),
-            "f10": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f10", 0, 4),
-            "f11": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f11", 0, 4),
-            "f12": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f12", 0, 4),
-            "f13": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f13", 0, 4),
-            "f14": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f14", 0, 4),
-            "f15": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f15", 0, 4),
-            "f16": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f16", 0, 4),
-            "f17": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f17", 0, 4),
-            "f18": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f18", 0, 4),
-            "f19": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f19", 0, 4),
-            "f20": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f20", 0, 4),
-            "f21": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f21", 0, 4),
-            "f22": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f22", 0, 4),
-            "f23": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f23", 0, 4),
-            "f24": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f24", 0, 4),
-            "f25": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f25", 0, 4),
-            "f26": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f26", 0, 4),
-            "f27": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f27", 0, 4),
-            "f28": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f28", 0, 4),
-            "f29": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f29", 0, 4),
-            "f30": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f30", 0, 4),
-            "f31": (unicorn.mips_const.UC_MIPS_REG_INVALID, "f31", 0, 4),
+            "f0": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f1": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f2": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f3": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f4": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f5": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f6": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f7": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f8": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f9": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f10": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f11": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f12": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f13": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f14": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f15": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f16": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f17": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f18": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f19": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f20": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f21": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f22": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f23": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f24": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f25": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f26": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f27": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f28": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f29": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f30": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "f31": unicorn.mips_const.UC_MIPS_REG_INVALID,
             # *** Floating Point Control Registers ***
             # NOTE: These are taken from Sleigh, and the MIPS docs.
             # Unicorn doesn't use these names, and has a different number of registers.
-            "fir": (unicorn.mips_const.UC_MIPS_REG_INVALID, "fir", 0, 4),
-            "fcsr": (unicorn.mips_const.UC_MIPS_REG_INVALID, "fcsr", 0, 4),
-            "fexr": (unicorn.mips_const.UC_MIPS_REG_INVALID, "fexr", 0, 4),
-            "fenr": (unicorn.mips_const.UC_MIPS_REG_INVALID, "fenr", 0, 4),
-            "fccr": (unicorn.mips_const.UC_MIPS_REG_INVALID, "fccr", 0, 4),
+            "fir": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "fcsr": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "fexr": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "fenr": unicorn.mips_const.UC_MIPS_REG_INVALID,
+            "fccr": unicorn.mips_const.UC_MIPS_REG_INVALID,
         }
 
 
@@ -155,18 +149,18 @@ class MIPSELMachineDef(MIPSMachineDef):
             {
                 # *** Accumulator Registers ***
                 # TODO: Unicorn broke support for these in 2.0.2
-                "ac0": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac0", 0, 8),
-                "lo0": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac0", 0, 4),
-                "hi0": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac0", 4, 4),
-                "ac1": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac1", 0, 8),
-                "lo1": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac1", 0, 4),
-                "hi1": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac1", 4, 4),
-                "ac2": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac2", 0, 8),
-                "lo2": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac2", 0, 4),
-                "hi2": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac2", 4, 4),
-                "ac3": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac3", 0, 8),
-                "lo3": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac3", 0, 4),
-                "hi3": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac3", 4, 4),
+                "ac0": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "lo0": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "hi0": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "ac1": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "lo1": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "hi1": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "ac2": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "lo2": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "hi2": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "ac3": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "lo3": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "hi3": unicorn.mips_const.UC_MIPS_REG_INVALID,
             }
         )
 
@@ -178,25 +172,23 @@ class MIPSBEMachineDef(MIPSMachineDef):
 
     uc_mode = unicorn.UC_MODE_MIPS32 | unicorn.UC_MODE_BIG_ENDIAN
 
-    cs_mode = capstone.CS_MODE_MIPS32 | capstone.CS_MODE_BIG_ENDIAN
-
     def __init__(self):
         super().__init__()
         self._registers.update(
             {
                 # *** Accumulator Registers ***
                 # TODO: Unicorn broke support for these in 2.0.2
-                "ac0": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac0", 0, 8),
-                "hi0": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac0", 0, 4),
-                "lo0": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac0", 4, 4),
-                "ac1": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac1", 0, 8),
-                "hi1": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac1", 0, 4),
-                "lo1": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac1", 4, 4),
-                "ac2": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac2", 0, 8),
-                "hi2": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac2", 0, 4),
-                "lo2": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac2", 4, 4),
-                "ac3": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac3", 0, 8),
-                "hi3": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac3", 0, 4),
-                "lo3": (unicorn.mips_const.UC_MIPS_REG_INVALID, "ac3", 4, 4),
+                "ac0": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "hi0": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "lo0": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "ac1": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "hi1": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "lo1": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "ac2": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "hi2": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "lo2": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "ac3": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "hi3": unicorn.mips_const.UC_MIPS_REG_INVALID,
+                "lo3": unicorn.mips_const.UC_MIPS_REG_INVALID,
             }
         )