smallworld-re 1.0.3__py3-none-any.whl → 2.0.0__py3-none-any.whl

smallworld/platforms/defs/xtensa.py

@@ -0,0 +1,96 @@
+from ..platforms import Architecture, Byteorder
+from .platformdef import PlatformDef, RegisterAliasDef, RegisterDef
+
+# NOTE: Xtensa is designed to be an extensible language
+# There are options for Xtensa chips to implement almost any
+# ISA feature you can bally well think of,
+# some of which are closed-source and closed-spec.
+#
+# Support for any specific extension depends on the emulator.
+
+
+class Xtensa(PlatformDef):
+    architecture = Architecture.XTENSA
+    byteorder = Byteorder.LITTLE
+
+    address_size = 4
+
+    conditional_branch_mnemonics = {
+        # Compare to zero and branch
+        "beqz",
+        "bnez",
+        "bgez",
+        "bltz",
+        # Compare to immediate and branch
+        "beqi",
+        "bnei",
+        "bgei",
+        "blti",
+        # Compare to unsigned immediate and branch
+        "bgeui",
+        "bltui",
+        # Compare to register and branch
+        "beq",
+        "bne",
+        "bge",
+        "blt",
+        # Compare to unsigned register and branch
+        "bgeu",
+        "bltu",
+        # Bit test versus immediate and branch
+        "bbci",
+        "bbsi",
+        # Bit test versus register and branch
+        "bbc",
+        "bbs",
+        # Test against bitmask and branch
+        "bany",
+        "bnone",
+        "ball",
+        "bnall",
+    }
+
+    # Xtensa core has no comparison operations;
+    # they're built into the branch instructions.
+    compare_mnemonics = set()
+
+    # NOTE: Capstone does not yet support xtensa
+    # It looks like it's either planned, or present in a newer version than we use.
+    capstone_arch = -1
+    capstone_mode = -1
+
+    pc_register = "pc"
+    sp_register = "sp"
+
+    # Special registers:
+    # - a0 is the default link register
+    # - a1 is the stack pointer
+    general_purpose_registers = [f"a{i}" for i in range(2, 16)]
+
+    registers = {
+        # *** General Purpose Registers ***
+        # a0 is also the default link register, but it doesn't get an alias
+        "a0": RegisterDef(name="a0", size=4),
+        # a1 is also the stack pointer
+        "a1": RegisterDef(name="a1", size=4),
+        "sp": RegisterAliasDef(name="sp", parent="a1", size=4, offset=0),
+        "a2": RegisterDef(name="a2", size=4),
+        "a3": RegisterDef(name="a3", size=4),
+        "a4": RegisterDef(name="a4", size=4),
+        "a5": RegisterDef(name="a5", size=4),
+        "a6": RegisterDef(name="a6", size=4),
+        "a7": RegisterDef(name="a7", size=4),
+        "a8": RegisterDef(name="a8", size=4),
+        "a9": RegisterDef(name="a9", size=4),
+        "a10": RegisterDef(name="a10", size=4),
+        "a11": RegisterDef(name="a11", size=4),
+        "a12": RegisterDef(name="a12", size=4),
+        "a13": RegisterDef(name="a13", size=4),
+        "a14": RegisterDef(name="a14", size=4),
+        "a15": RegisterDef(name="a15", size=4),
+        # *** Program Counter ***
+        "pc": RegisterDef(name="pc", size=4),
+        # *** Shift Amount Register ***
+        # This thing is actually 6 bits.
+        "sar": RegisterDef(name="sar", size=4),
+    }

smallworld/{platforms.py → platforms/platforms.py}

@@ -36,6 +36,9 @@ class Architecture(enum.Enum):
     ARM_V7R = "arm-v7r"
     ARM_V7A = "arm-v7a"
 
+    LOONGARCH32 = "loongarch32"
+    LOONGARCH64 = "loongarch64"
+
     RISCV64 = "riscv-64"
 
     XTENSA = "xtensa"

smallworld/state/cpus/__init__.py

@@ -4,6 +4,7 @@ from .arm import ARMv5T, ARMv6M, ARMv6MThumb, ARMv7A, ARMv7M, ARMv7R
 from .cpu import *  # noqa: F401, F403
 from .cpu import __all__ as __cpu__
 from .i386 import I386
+from .loongarch import LoongArch64
 from .mips import MIPSBE, MIPSEL
 from .mips64 import MIPS64BE, MIPS64EL
 from .powerpc import PowerPC32, PowerPC64
@@ -20,6 +21,7 @@ __all__ = __cpu__ + [
     "ARMv7R",
     "ARMv7A",
     "I386",
+    "LoongArch64",
     "MIPS64EL",
     "MIPS64BE",
     "MIPSEL",

smallworld/state/cpus/aarch64.py

@@ -1,5 +1,3 @@
-import typing
-
 from ... import platforms, state
 from . import cpu
 
@@ -15,13 +13,6 @@ class AArch64(cpu.CPU):
         platforms.Architecture.AARCH64, platforms.Byteorder.LITTLE
     )
 
-    def get_general_purpose_registers(self) -> typing.List[str]:
-        # Special registers:
-        # x29: frame pointer
-        # x30: link register
-        # x31: stack pointer or zero, depending on instruction
-        return [f"x{i}" for i in range(0, 29)]
-
     def __init__(self):
         super().__init__()
         # *** General Purpose Registers ***

smallworld/state/cpus/amd64.py

@@ -1,5 +1,3 @@
-import typing
-
 from ... import platforms
 from .. import state
 from ..x86_registers import X86MMRRegister
@@ -16,28 +14,6 @@ class AMD64(cpu.CPU):
     the old ones, we need new platforms.
     """
 
-    _GENERAL_PURPOSE_REGS = [
-        "rax",
-        "rbx",
-        "rcx",
-        "rdx",
-        "rdi",
-        "rsi",
-        "rbp",
-        "rsp",
-        "r8",
-        "r9",
-        "r10",
-        "r11",
-        "r12",
-        "r13",
-        "r14",
-        "r15",
-    ]
-
-    def get_general_purpose_registers(self) -> typing.List[str]:
-        return self._GENERAL_PURPOSE_REGS
-
     def __init__(self):
         super().__init__()
         # *** General Purpose Registers ***
@@ -168,7 +144,7 @@ class AMD64(cpu.CPU):
 
         self.rsi = state.Register("rsi", 8)
         self.add(self.rsi)
-        self.esi = state.RegisterAlias("rsi", self.rsi, 4, 0)
+        self.esi = state.RegisterAlias("esi", self.rsi, 4, 0)
         self.add(self.esi)
         self.si = state.RegisterAlias("si", self.rsi, 2, 0)
         self.add(self.si)
@@ -177,7 +153,7 @@ class AMD64(cpu.CPU):
 
         self.rsp = state.Register("rsp", 8)
         self.add(self.rsp)
-        self.esp = state.RegisterAlias("rsp", self.rsp, 4, 0)
+        self.esp = state.RegisterAlias("esp", self.rsp, 4, 0)
         self.add(self.esp)
         self.sp = state.RegisterAlias("sp", self.rsp, 2, 0)
         self.add(self.sp)
@@ -186,7 +162,7 @@ class AMD64(cpu.CPU):
 
         self.rbp = state.Register("rbp", 8)
         self.add(self.rbp)
-        self.ebp = state.RegisterAlias("rbp", self.rbp, 4, 0)
+        self.ebp = state.RegisterAlias("ebp", self.rbp, 4, 0)
         self.add(self.ebp)
         self.bp = state.RegisterAlias("bp", self.rbp, 2, 0)
         self.add(self.bp)
@@ -196,7 +172,7 @@ class AMD64(cpu.CPU):
         # *** Instruction Pointer ***
         self.rip = state.Register("rip", 8)
         self.add(self.rip)
-        self.eip = state.RegisterAlias("rip", self.rip, 4, 0)
+        self.eip = state.RegisterAlias("eip", self.rip, 4, 0)
         self.add(self.eip)
         self.ip = state.RegisterAlias("ip", self.rip, 2, 0)
         self.add(self.ip)
@@ -225,6 +201,8 @@ class AMD64(cpu.CPU):
         self.add(self.fs)
         self.gs = state.Register("gs", 8)
         self.add(self.gs)
+        self.ss = state.Register("ss", 8)
+        self.add(self.ss)
 
         # *** Control Registers ***
         self.cr0 = state.Register("cr0", 8)

smallworld/state/cpus/arm.py

@@ -1,5 +1,3 @@
-import typing
-
 from ... import platforms
 from .. import state
 from . import cpu
@@ -16,15 +14,6 @@ class ARM(cpu.CPU):
     dimensions of difference for the available modes.
     """
 
-    # Special registers:
-    # r13: stack pointer
-    # r14: link register
-    # r15: Program counter
-    _GENERAL_PURPOSE_REGS = [f"r{i}" for i in range(0, 13)]
-
-    def get_general_purpose_registers(self) -> typing.List[str]:
-        return self._GENERAL_PURPOSE_REGS
-
     def __init__(self):
         super().__init__()
         # *** General-purpose registers ***

smallworld/state/cpus/cpu.py

@@ -1,5 +1,4 @@
 import abc
-import typing
 
 from ... import platforms, utils
 from .. import state
@@ -54,16 +53,6 @@ class CPU(state.StatefulSet):
         except ValueError:
             raise ValueError(f"no model for {platform}")
 
-    @abc.abstractmethod
-    def get_general_purpose_registers(self) -> typing.List[str]:
-        """Get a list of general purpose register names.
-
-        Returns:
-            A list of the general purpose register names for this CPU.
-        """
-
-        pass
-
     def __repr__(self) -> str:
         return f"{self.__class__.__name__}({self.platform})"
 

smallworld/state/cpus/i386.py

@@ -1,5 +1,3 @@
-import typing
-
 from ... import platforms
 from .. import state
 from ..x86_registers import X86MMRRegister
@@ -13,11 +11,6 @@ class I386(cpu.CPU):
         platforms.Architecture.X86_32, platforms.Byteorder.LITTLE
     )
 
-    _GENERAL_PURPOSE_REGS = ["eax", "ebx", "ecx", "edx", "edi", "esi", "ebp", "esp"]
-
-    def get_general_purpose_registers(self) -> typing.List[str]:
-        return self._GENERAL_PURPOSE_REGS
-
     def __init__(self):
         super().__init__()
         # *** General Purpose Registers ***

smallworld/state/cpus/loongarch.py

@@ -0,0 +1,299 @@
+from ... import platforms
+from .. import state
+from . import cpu
+
+
+class LoongArch(cpu.CPU):
+    """Abstract CPU state object for all LoongArch targets"""
+
+    def __init__(self, wordsize: int) -> None:
+        super().__init__()
+        # Program counter (not a real register)
+        self.pc = state.Register("pc", size=wordsize)
+        self.add(self.pc)
+        # Zero register
+        self.r0 = state.Register("r0", size=wordsize)
+        self.add(self.r0)
+        self.zero = state.RegisterAlias("zero", self.r0, size=wordsize, offset=0)
+        self.add(self.zero)
+        # Return address
+        self.r1 = state.Register("r1", size=wordsize)
+        self.add(self.r1)
+        self.ra = state.RegisterAlias("ra", self.r1, size=wordsize, offset=0)
+        self.add(self.ra)
+        # TLS pointer
+        self.r2 = state.Register("r2", size=wordsize)
+        self.add(self.r2)
+        self.tp = state.RegisterAlias("tp", self.r2, size=wordsize, offset=0)
+        self.add(self.tp)
+        # Stack pointer
+        self.r3 = state.Register("r3", size=wordsize)
+        self.add(self.r3)
+        self.sp = state.RegisterAlias("sp", self.r3, size=wordsize, offset=0)
+        self.add(self.sp)
+        # Arguments.
+        # a0 and a1 are also the return registers
+        self.r4 = state.Register("r4", size=wordsize)
+        self.add(self.r4)
+        self.a0 = state.RegisterAlias("a0", self.r4, size=wordsize, offset=0)
+        self.add(self.a0)
+        self.v0 = state.RegisterAlias("v0", self.r4, size=wordsize, offset=0)
+        self.add(self.v0)
+        self.r5 = state.Register("r5", size=wordsize)
+        self.add(self.r5)
+        self.a1 = state.RegisterAlias("a1", self.r5, size=wordsize, offset=0)
+        self.add(self.a1)
+        self.v1 = state.RegisterAlias("v1", self.r5, size=wordsize, offset=0)
+        self.add(self.v1)
+        self.r6 = state.Register("r6", size=wordsize)
+        self.add(self.r6)
+        self.a2 = state.RegisterAlias("a2", self.r6, size=wordsize, offset=0)
+        self.add(self.a2)
+        self.r7 = state.Register("r7", size=wordsize)
+        self.add(self.r7)
+        self.a3 = state.RegisterAlias("a3", self.r7, size=wordsize, offset=0)
+        self.add(self.a3)
+        self.r8 = state.Register("r8", size=wordsize)
+        self.add(self.r8)
+        self.a4 = state.RegisterAlias("a4", self.r8, size=wordsize, offset=0)
+        self.add(self.a4)
+        self.r9 = state.Register("r9", size=wordsize)
+        self.add(self.r9)
+        self.a5 = state.RegisterAlias("a5", self.r9, size=wordsize, offset=0)
+        self.add(self.a5)
+        self.r10 = state.Register("r10", size=wordsize)
+        self.add(self.r10)
+        self.a6 = state.RegisterAlias("a6", self.r10, size=wordsize, offset=0)
+        self.add(self.a6)
+        self.r11 = state.Register("r11", size=wordsize)
+        self.add(self.r11)
+        self.a7 = state.RegisterAlias("a7", self.r11, size=wordsize, offset=0)
+        self.add(self.a7)
+        # Temporary registers
+        self.r12 = state.Register("r12", size=wordsize)
+        self.add(self.r12)
+        self.t0 = state.RegisterAlias("t0", self.r12, size=wordsize, offset=0)
+        self.add(self.t0)
+        self.r13 = state.Register("r13", size=wordsize)
+        self.add(self.r13)
+        self.t1 = state.RegisterAlias("t1", self.r13, size=wordsize, offset=0)
+        self.add(self.t1)
+        self.r14 = state.Register("r14", size=wordsize)
+        self.add(self.r14)
+        self.t2 = state.RegisterAlias("t2", self.r14, size=wordsize, offset=0)
+        self.add(self.t2)
+        self.r15 = state.Register("r15", size=wordsize)
+        self.add(self.r15)
+        self.t3 = state.RegisterAlias("t3", self.r15, size=wordsize, offset=0)
+        self.add(self.t3)
+        self.r16 = state.Register("r16", size=wordsize)
+        self.add(self.r16)
+        self.t4 = state.RegisterAlias("t4", self.r16, size=wordsize, offset=0)
+        self.add(self.t4)
+        self.r17 = state.Register("r17", size=wordsize)
+        self.add(self.r17)
+        self.t5 = state.RegisterAlias("t5", self.r17, size=wordsize, offset=0)
+        self.add(self.t5)
+        self.r18 = state.Register("r18", size=wordsize)
+        self.add(self.r18)
+        self.t6 = state.RegisterAlias("t6", self.r18, size=wordsize, offset=0)
+        self.add(self.t6)
+        self.r19 = state.Register("r19", size=wordsize)
+        self.add(self.r19)
+        self.t7 = state.RegisterAlias("t7", self.r19, size=wordsize, offset=0)
+        self.add(self.t7)
+        self.r20 = state.Register("r20", size=wordsize)
+        self.add(self.r20)
+        self.t8 = state.RegisterAlias("t8", self.r20, size=wordsize, offset=0)
+        self.add(self.t8)
+        # Per-CPU Base Address
+        self.r21 = state.Register("r21", size=wordsize)
+        self.add(self.r21)
+        self.u0 = state.RegisterAlias("u0", self.r21, size=wordsize, offset=0)
+        self.add(self.u0)
+        # Frame Pointer
+        self.r22 = state.Register("r22", size=wordsize)
+        self.add(self.r22)
+        self.fp = state.RegisterAlias("fp", self.r22, size=wordsize, offset=0)
+        self.add(self.fp)
+        # Static registers
+        self.r23 = state.Register("r23", size=wordsize)
+        self.add(self.r23)
+        self.s0 = state.RegisterAlias("s0", self.r23, size=wordsize, offset=0)
+        self.add(self.s0)
+        self.r24 = state.Register("r24", size=wordsize)
+        self.add(self.r24)
+        self.s1 = state.RegisterAlias("s1", self.r24, size=wordsize, offset=0)
+        self.add(self.s1)
+        self.r25 = state.Register("r25", size=wordsize)
+        self.add(self.r25)
+        self.s2 = state.RegisterAlias("s2", self.r25, size=wordsize, offset=0)
+        self.add(self.s2)
+        self.r26 = state.Register("r26", size=wordsize)
+        self.add(self.r26)
+        self.s3 = state.RegisterAlias("s3", self.r26, size=wordsize, offset=0)
+        self.add(self.s3)
+        self.r27 = state.Register("r27", size=wordsize)
+        self.add(self.r27)
+        self.s4 = state.RegisterAlias("s4", self.r27, size=wordsize, offset=0)
+        self.add(self.s4)
+        self.r28 = state.Register("r28", size=wordsize)
+        self.add(self.r28)
+        self.s5 = state.RegisterAlias("s5", self.r28, size=wordsize, offset=0)
+        self.add(self.s5)
+        self.r29 = state.Register("r29", size=wordsize)
+        self.add(self.r29)
+        self.s6 = state.RegisterAlias("s6", self.r29, size=wordsize, offset=0)
+        self.add(self.s6)
+        self.r30 = state.Register("r30", size=wordsize)
+        self.add(self.r30)
+        self.s7 = state.RegisterAlias("s7", self.r30, size=wordsize, offset=0)
+        self.add(self.s7)
+        self.r31 = state.Register("r31", size=wordsize)
+        self.add(self.r31)
+        self.s8 = state.RegisterAlias("s8", self.r31, size=wordsize, offset=0)
+        self.add(self.s8)
+        # Floating-point arguments.
+        # fa0 and fa1 are also return values
+        self.f0 = state.Register("f0", size=8)
+        self.add(self.f0)
+        self.fa0 = state.RegisterAlias("fa0", self.f0, size=8, offset=0)
+        self.add(self.fa0)
+        self.f1 = state.Register("f1", size=8)
+        self.add(self.f1)
+        self.fa1 = state.RegisterAlias("fa1", self.f1, size=8, offset=0)
+        self.add(self.fa1)
+        self.f2 = state.Register("f2", size=8)
+        self.add(self.f2)
+        self.fa2 = state.RegisterAlias("fa2", self.f2, size=8, offset=0)
+        self.add(self.fa2)
+        self.f3 = state.Register("f3", size=8)
+        self.add(self.f3)
+        self.fa3 = state.RegisterAlias("fa3", self.f3, size=8, offset=0)
+        self.add(self.fa3)
+        self.f4 = state.Register("f4", size=8)
+        self.add(self.f4)
+        self.fa4 = state.RegisterAlias("fa4", self.f4, size=8, offset=0)
+        self.add(self.fa4)
+        self.f5 = state.Register("f5", size=8)
+        self.add(self.f5)
+        self.fa5 = state.RegisterAlias("fa5", self.f5, size=8, offset=0)
+        self.add(self.fa5)
+        self.f6 = state.Register("f6", size=8)
+        self.add(self.f6)
+        self.fa6 = state.RegisterAlias("fa6", self.f6, size=8, offset=0)
+        self.add(self.fa6)
+        self.f7 = state.Register("f7", size=8)
+        self.add(self.f7)
+        self.fa7 = state.RegisterAlias("fa7", self.f7, size=8, offset=0)
+        self.add(self.fa7)
+        # Floating-point temporary registers
+        self.f8 = state.Register("f8", size=8)
+        self.add(self.f8)
+        self.ft0 = state.RegisterAlias("ft0", self.f8, size=8, offset=0)
+        self.add(self.ft0)
+        self.f9 = state.Register("f9", size=8)
+        self.add(self.f9)
+        self.ft1 = state.RegisterAlias("ft1", self.f9, size=8, offset=0)
+        self.add(self.ft1)
+        self.f10 = state.Register("f10", size=8)
+        self.add(self.f10)
+        self.ft2 = state.RegisterAlias("ft2", self.f10, size=8, offset=0)
+        self.add(self.ft2)
+        self.f11 = state.Register("f11", size=8)
+        self.add(self.f11)
+        self.ft3 = state.RegisterAlias("ft3", self.f11, size=8, offset=0)
+        self.add(self.ft3)
+        self.f12 = state.Register("f12", size=8)
+        self.add(self.f12)
+        self.ft4 = state.RegisterAlias("ft4", self.f12, size=8, offset=0)
+        self.add(self.ft4)
+        self.f13 = state.Register("f13", size=8)
+        self.add(self.f13)
+        self.ft5 = state.RegisterAlias("ft5", self.f13, size=8, offset=0)
+        self.add(self.ft5)
+        self.f14 = state.Register("f14", size=8)
+        self.add(self.f14)
+        self.ft6 = state.RegisterAlias("ft6", self.f14, size=8, offset=0)
+        self.add(self.ft6)
+        self.f15 = state.Register("f15", size=8)
+        self.add(self.f15)
+        self.ft7 = state.RegisterAlias("ft7", self.f15, size=8, offset=0)
+        self.add(self.ft7)
+        self.f16 = state.Register("f16", size=8)
+        self.add(self.f16)
+        self.ft8 = state.RegisterAlias("ft8", self.f16, size=8, offset=0)
+        self.add(self.ft8)
+        self.f17 = state.Register("f17", size=8)
+        self.add(self.f17)
+        self.ft9 = state.RegisterAlias("ft9", self.f17, size=8, offset=0)
+        self.add(self.ft9)
+        self.f18 = state.Register("f18", size=8)
+        self.add(self.f18)
+        self.ft10 = state.RegisterAlias("ft10", self.f18, size=8, offset=0)
+        self.add(self.ft10)
+        self.f19 = state.Register("f19", size=8)
+        self.add(self.f19)
+        self.ft11 = state.RegisterAlias("ft11", self.f19, size=8, offset=0)
+        self.add(self.ft11)
+        self.f20 = state.Register("f20", size=8)
+        self.add(self.f20)
+        self.ft12 = state.RegisterAlias("ft12", self.f20, size=8, offset=0)
+        self.add(self.ft12)
+        self.f21 = state.Register("f21", size=8)
+        self.add(self.f21)
+        self.ft13 = state.RegisterAlias("ft13", self.f21, size=8, offset=0)
+        self.add(self.ft13)
+        self.f22 = state.Register("f22", size=8)
+        self.add(self.f22)
+        self.ft14 = state.RegisterAlias("ft14", self.f22, size=8, offset=0)
+        self.add(self.ft14)
+        self.f23 = state.Register("f23", size=8)
+        self.add(self.f23)
+        self.ft15 = state.RegisterAlias("ft15", self.f23, size=8, offset=0)
+        self.add(self.ft15)
+        # Floating-point static registers
+        self.f24 = state.Register("f24", size=8)
+        self.add(self.f24)
+        self.fs0 = state.RegisterAlias("fs0", self.f24, size=8, offset=0)
+        self.add(self.fs0)
+        self.f25 = state.Register("f25", size=8)
+        self.add(self.f25)
+        self.fs1 = state.RegisterAlias("fs1", self.f25, size=8, offset=0)
+        self.add(self.fs1)
+        self.f26 = state.Register("f26", size=8)
+        self.add(self.f26)
+        self.fs2 = state.RegisterAlias("fs2", self.f26, size=8, offset=0)
+        self.add(self.fs2)
+        self.f27 = state.Register("f27", size=8)
+        self.add(self.f27)
+        self.fs3 = state.RegisterAlias("fs3", self.f27, size=8, offset=0)
+        self.add(self.fs3)
+        self.f28 = state.Register("f28", size=8)
+        self.add(self.f28)
+        self.fs4 = state.RegisterAlias("fs4", self.f28, size=8, offset=0)
+        self.add(self.fs4)
+        self.f29 = state.Register("f29", size=8)
+        self.add(self.f29)
+        self.fs5 = state.RegisterAlias("fs5", self.f29, size=8, offset=0)
+        self.add(self.fs5)
+        self.f30 = state.Register("f30", size=8)
+        self.add(self.f30)
+        self.fs6 = state.RegisterAlias("fs6", self.f30, size=8, offset=0)
+        self.add(self.fs6)
+        self.f31 = state.Register("f31", size=8)
+        self.add(self.f31)
+        self.fs7 = state.RegisterAlias("fs7", self.f31, size=8, offset=0)
+        self.add(self.fs7)
+
+
+class LoongArch64(LoongArch):
+    platform = platforms.Platform(
+        platforms.Architecture.LOONGARCH64, platforms.Byteorder.LITTLE
+    )
+
+    def __init__(self):
+        super().__init__(8)
+
+
+__all__ = ["LoongArch64"]

smallworld/state/cpus/mips.py

@@ -1,5 +1,3 @@
-import typing
-
 from ... import platforms
 from .. import state
 from . import cpu
@@ -12,43 +10,6 @@ class MIPS(cpu.CPU):
     unicorn.mips_const.
     """
 
-    # Excluded registers:
-    # - zero: Hard-wired to zero
-    # - at: Reserved for assembler
-    # - kX: Reserved for kernel; used as general in some ABIs
-    # - fX: Floating-point registers
-    # - acX: Accumulator registers
-    _GENERAL_PURPOSE_REGS = [
-        "v0",
-        "v1",
-        "a0",
-        "a1",
-        "a2",
-        "a3",
-        "t0",
-        "t1",
-        "t2",
-        "t3",
-        "t4",
-        "t5",
-        "t6",
-        "t7",
-        "t8",
-        "t9",
-        "s0",
-        "s1",
-        "s2",
-        "s3",
-        "s4",
-        "s5",
-        "s6",
-        "s7",
-        "s8",
-    ]
-
-    def get_general_purpose_registers(self) -> typing.List[str]:
-        return self._GENERAL_PURPOSE_REGS
-
     def __init__(self):
         super().__init__()
         # NOTE: MIPS registers have both a name and a number.
@@ -304,10 +265,10 @@ class MIPSEL(MIPS):
         # from 32-bit multiplication, amongst others.
         self.ac0 = state.Register("ac0", size=8)
         self.add(self.ac0)
-        self.lo = state.RegisterAlias("lo0", self.ac0, size=4, offset=0)
-        self.add(self.lo)
-        self.hi = state.RegisterAlias("hi0", self.ac0, size=4, offset=4)
-        self.add(self.hi)
+        self.lo0 = state.RegisterAlias("lo0", self.ac0, size=4, offset=0)
+        self.add(self.lo0)
+        self.hi0 = state.RegisterAlias("hi0", self.ac0, size=4, offset=4)
+        self.add(self.hi0)
         self.ac1 = state.Register("ac1", size=8)
         self.add(self.ac1)
         self.lo1 = state.RegisterAlias("lo1", self.ac1, size=4, offset=0)
@@ -346,8 +307,6 @@ class MIPSBE(MIPS):
         # from 32-bit multiplication, amongst others.
         self.ac0 = state.Register("ac0", size=8)
         self.add(self.ac0)
-        # NOTE: Be careful: there is also a 'hi' and 'lo' register;
-        # they do different things.
         self.hi0 = state.RegisterAlias("hi0", self.ac0, size=4, offset=0)
         self.add(self.hi0)
         self.lo0 = state.RegisterAlias("lo0", self.ac0, size=4, offset=4)
@@ -370,5 +329,3 @@ class MIPSBE(MIPS):
         self.add(self.hi3)
         self.lo3 = state.RegisterAlias("lo3", self.ac3, size=4, offset=4)
         self.add(self.lo3)
-        # TODO: MIPS has a boatload of extensions with their own registers.
-        # There isn't a clean join between Sleigh, Unicorn, and MIPS docs.