smallworld-re 1.0.2__py3-none-any.whl → 2.0.0__py3-none-any.whl

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (306) hide show
  1. smallworld/analyses/__init__.py +8 -0
  2. smallworld/analyses/analysis.py +8 -67
  3. smallworld/analyses/code_coverage.py +1 -2
  4. smallworld/analyses/colorizer.py +301 -534
  5. smallworld/analyses/colorizer_def_use.py +217 -0
  6. smallworld/analyses/colorizer_summary.py +173 -83
  7. smallworld/analyses/field_detection/field_analysis.py +7 -8
  8. smallworld/analyses/field_detection/hints.py +1 -1
  9. smallworld/analyses/field_detection/malloc.py +2 -2
  10. smallworld/analyses/trace_execution.py +160 -0
  11. smallworld/analyses/trace_execution_types.py +42 -0
  12. smallworld/analyses/unstable/angr/divergence.py +1 -2
  13. smallworld/analyses/unstable/angr/model.py +5 -6
  14. smallworld/analyses/unstable/angr_nwbt.py +3 -4
  15. smallworld/analyses/unstable/code_coverage.py +2 -3
  16. smallworld/analyses/unstable/code_reachable.py +2 -3
  17. smallworld/analyses/unstable/control_flow_tracer.py +2 -3
  18. smallworld/analyses/unstable/pointer_finder.py +2 -3
  19. smallworld/analyses/unstable/utils/tui.py +71 -0
  20. smallworld/emulators/__init__.py +3 -1
  21. smallworld/emulators/angr/angr.py +30 -9
  22. smallworld/emulators/angr/machdefs/__init__.py +2 -0
  23. smallworld/emulators/angr/machdefs/aarch64.py +1 -1
  24. smallworld/emulators/angr/machdefs/amd64.py +0 -4
  25. smallworld/emulators/angr/machdefs/arm.py +0 -2
  26. smallworld/emulators/angr/machdefs/i386.py +0 -2
  27. smallworld/emulators/angr/machdefs/loongarch.py +340 -0
  28. smallworld/emulators/angr/machdefs/machdef.py +1 -8
  29. smallworld/emulators/angr/machdefs/mips.py +0 -2
  30. smallworld/emulators/angr/machdefs/mips64.py +0 -2
  31. smallworld/emulators/angr/machdefs/ppc.py +1 -2
  32. smallworld/emulators/angr/machdefs/riscv.py +8 -10
  33. smallworld/emulators/angr/machdefs/xtensa.py +7 -4
  34. smallworld/emulators/emulator.py +22 -0
  35. smallworld/emulators/ghidra/__init__.py +37 -0
  36. smallworld/emulators/ghidra/ghidra.py +513 -0
  37. smallworld/emulators/ghidra/machdefs/__init__.py +31 -0
  38. smallworld/emulators/ghidra/machdefs/aarch64.py +289 -0
  39. smallworld/emulators/ghidra/machdefs/amd64.py +185 -0
  40. smallworld/emulators/ghidra/machdefs/arm.py +370 -0
  41. smallworld/emulators/ghidra/machdefs/i386.py +109 -0
  42. smallworld/emulators/ghidra/machdefs/loongarch.py +162 -0
  43. smallworld/emulators/ghidra/machdefs/machdef.py +81 -0
  44. smallworld/emulators/ghidra/machdefs/mips.py +163 -0
  45. smallworld/emulators/ghidra/machdefs/mips64.py +186 -0
  46. smallworld/emulators/ghidra/machdefs/ppc.py +98 -0
  47. smallworld/emulators/ghidra/machdefs/riscv.py +208 -0
  48. smallworld/emulators/ghidra/machdefs/xtensa.py +21 -0
  49. smallworld/emulators/ghidra/typing.py +28 -0
  50. smallworld/emulators/hookable.py +18 -4
  51. smallworld/emulators/panda/machdefs/__init__.py +2 -2
  52. smallworld/emulators/panda/machdefs/aarch64.py +186 -11
  53. smallworld/emulators/panda/machdefs/amd64.py +103 -11
  54. smallworld/emulators/panda/machdefs/arm.py +216 -20
  55. smallworld/emulators/panda/machdefs/i386.py +30 -7
  56. smallworld/emulators/panda/machdefs/machdef.py +9 -16
  57. smallworld/emulators/panda/machdefs/mips.py +49 -5
  58. smallworld/emulators/panda/machdefs/mips64.py +57 -5
  59. smallworld/emulators/panda/machdefs/ppc.py +38 -13
  60. smallworld/emulators/panda/panda.py +146 -44
  61. smallworld/emulators/unicorn/__init__.py +2 -0
  62. smallworld/emulators/unicorn/machdefs/aarch64.py +253 -264
  63. smallworld/emulators/unicorn/machdefs/amd64.py +254 -259
  64. smallworld/emulators/unicorn/machdefs/arm.py +200 -212
  65. smallworld/emulators/unicorn/machdefs/i386.py +84 -90
  66. smallworld/emulators/unicorn/machdefs/machdef.py +2 -23
  67. smallworld/emulators/unicorn/machdefs/mips.py +127 -135
  68. smallworld/emulators/unicorn/unicorn.py +52 -13
  69. smallworld/helpers.py +4 -19
  70. smallworld/hinting/hinting.py +22 -192
  71. smallworld/hinting/hints.py +50 -18
  72. smallworld/instructions/bsid.py +8 -8
  73. smallworld/logging.py +4 -2
  74. smallworld/platforms/__init__.py +12 -0
  75. smallworld/platforms/defs/__init__.py +36 -0
  76. smallworld/platforms/defs/aarch64.py +450 -0
  77. smallworld/platforms/defs/amd64.py +463 -0
  78. smallworld/platforms/defs/arm.py +519 -0
  79. smallworld/platforms/defs/i386.py +258 -0
  80. smallworld/platforms/defs/loongarch.py +270 -0
  81. smallworld/platforms/defs/mips.py +321 -0
  82. smallworld/platforms/defs/mips64.py +313 -0
  83. smallworld/platforms/defs/platformdef.py +97 -0
  84. smallworld/platforms/defs/powerpc.py +259 -0
  85. smallworld/platforms/defs/riscv.py +257 -0
  86. smallworld/platforms/defs/xtensa.py +96 -0
  87. smallworld/{platforms.py → platforms/platforms.py} +3 -0
  88. smallworld/state/cpus/__init__.py +2 -0
  89. smallworld/state/cpus/aarch64.py +0 -9
  90. smallworld/state/cpus/amd64.py +6 -28
  91. smallworld/state/cpus/arm.py +0 -11
  92. smallworld/state/cpus/cpu.py +0 -11
  93. smallworld/state/cpus/i386.py +0 -7
  94. smallworld/state/cpus/loongarch.py +299 -0
  95. smallworld/state/cpus/mips.py +4 -47
  96. smallworld/state/cpus/mips64.py +18 -58
  97. smallworld/state/cpus/powerpc.py +2 -9
  98. smallworld/state/cpus/riscv.py +1 -11
  99. smallworld/state/cpus/xtensa.py +0 -5
  100. smallworld/state/memory/code.py +44 -2
  101. smallworld/state/memory/elf/__init__.py +5 -1
  102. smallworld/state/memory/elf/coredump/__init__.py +3 -0
  103. smallworld/state/memory/elf/coredump/coredump.py +46 -0
  104. smallworld/state/memory/elf/coredump/prstatus/__init__.py +27 -0
  105. smallworld/state/memory/elf/coredump/prstatus/aarch64.py +46 -0
  106. smallworld/state/memory/elf/coredump/prstatus/amd64.py +40 -0
  107. smallworld/state/memory/elf/coredump/prstatus/arm.py +53 -0
  108. smallworld/state/memory/elf/coredump/prstatus/i386.py +30 -0
  109. smallworld/state/memory/elf/coredump/prstatus/mips.py +55 -0
  110. smallworld/state/memory/elf/coredump/prstatus/mips64.py +57 -0
  111. smallworld/state/memory/elf/coredump/prstatus/ppc.py +82 -0
  112. smallworld/state/memory/elf/coredump/prstatus/prstatus.py +129 -0
  113. smallworld/state/memory/elf/elf.py +225 -61
  114. smallworld/state/memory/elf/register_state.py +36 -0
  115. smallworld/state/memory/elf/rela/__init__.py +2 -0
  116. smallworld/state/memory/elf/rela/aarch64.py +3 -1
  117. smallworld/state/memory/elf/rela/amd64.py +4 -2
  118. smallworld/state/memory/elf/rela/arm.py +4 -2
  119. smallworld/state/memory/elf/rela/i386.py +4 -2
  120. smallworld/state/memory/elf/rela/loongarch.py +32 -0
  121. smallworld/state/memory/elf/rela/mips.py +39 -18
  122. smallworld/state/memory/elf/rela/ppc.py +31 -14
  123. smallworld/state/memory/elf/structs.py +3 -0
  124. smallworld/state/memory/heap.py +2 -2
  125. smallworld/state/memory/memory.py +18 -0
  126. smallworld/state/memory/pe/__init__.py +3 -0
  127. smallworld/state/memory/pe/pe.py +361 -0
  128. smallworld/state/memory/pe/structs.py +60 -0
  129. smallworld/state/memory/stack/__init__.py +2 -0
  130. smallworld/state/memory/stack/loongarch.py +26 -0
  131. smallworld/state/models/__init__.py +29 -2
  132. smallworld/state/models/aarch64/__init__.py +1 -0
  133. smallworld/state/models/aarch64/systemv/__init__.py +6 -0
  134. smallworld/state/models/aarch64/systemv/c99/__init__.py +12 -0
  135. smallworld/state/models/aarch64/systemv/c99/signal.py +16 -0
  136. smallworld/state/models/aarch64/systemv/c99/stdio.py +265 -0
  137. smallworld/state/models/aarch64/systemv/c99/stdlib.py +169 -0
  138. smallworld/state/models/aarch64/systemv/c99/string.py +139 -0
  139. smallworld/state/models/aarch64/systemv/c99/time.py +61 -0
  140. smallworld/state/models/aarch64/systemv/posix/__init__.py +6 -0
  141. smallworld/state/models/aarch64/systemv/posix/libgen.py +16 -0
  142. smallworld/state/models/aarch64/systemv/posix/signal.py +157 -0
  143. smallworld/state/models/aarch64/systemv/systemv.py +80 -0
  144. smallworld/state/models/amd64/__init__.py +1 -0
  145. smallworld/state/models/amd64/systemv/__init__.py +6 -0
  146. smallworld/state/models/amd64/systemv/c99/__init__.py +12 -0
  147. smallworld/state/models/amd64/systemv/c99/signal.py +16 -0
  148. smallworld/state/models/amd64/systemv/c99/stdio.py +265 -0
  149. smallworld/state/models/amd64/systemv/c99/stdlib.py +169 -0
  150. smallworld/state/models/amd64/systemv/c99/string.py +139 -0
  151. smallworld/state/models/amd64/systemv/c99/time.py +61 -0
  152. smallworld/state/models/amd64/systemv/posix/__init__.py +6 -0
  153. smallworld/state/models/amd64/systemv/posix/libgen.py +16 -0
  154. smallworld/state/models/amd64/systemv/posix/signal.py +157 -0
  155. smallworld/state/models/amd64/systemv/systemv.py +78 -0
  156. smallworld/state/models/armel/__init__.py +1 -0
  157. smallworld/state/models/armel/systemv/__init__.py +6 -0
  158. smallworld/state/models/armel/systemv/c99/__init__.py +12 -0
  159. smallworld/state/models/armel/systemv/c99/signal.py +16 -0
  160. smallworld/state/models/armel/systemv/c99/stdio.py +265 -0
  161. smallworld/state/models/armel/systemv/c99/stdlib.py +169 -0
  162. smallworld/state/models/armel/systemv/c99/string.py +139 -0
  163. smallworld/state/models/armel/systemv/c99/time.py +61 -0
  164. smallworld/state/models/armel/systemv/posix/__init__.py +6 -0
  165. smallworld/state/models/armel/systemv/posix/libgen.py +16 -0
  166. smallworld/state/models/armel/systemv/posix/signal.py +157 -0
  167. smallworld/state/models/armel/systemv/systemv.py +82 -0
  168. smallworld/state/models/armhf/__init__.py +1 -0
  169. smallworld/state/models/armhf/systemv/__init__.py +6 -0
  170. smallworld/state/models/armhf/systemv/c99/__init__.py +12 -0
  171. smallworld/state/models/armhf/systemv/c99/signal.py +16 -0
  172. smallworld/state/models/armhf/systemv/c99/stdio.py +265 -0
  173. smallworld/state/models/armhf/systemv/c99/stdlib.py +169 -0
  174. smallworld/state/models/armhf/systemv/c99/string.py +139 -0
  175. smallworld/state/models/armhf/systemv/c99/time.py +61 -0
  176. smallworld/state/models/armhf/systemv/posix/__init__.py +6 -0
  177. smallworld/state/models/armhf/systemv/posix/libgen.py +16 -0
  178. smallworld/state/models/armhf/systemv/posix/signal.py +157 -0
  179. smallworld/state/models/armhf/systemv/systemv.py +77 -0
  180. smallworld/state/models/c99/__init__.py +12 -0
  181. smallworld/state/models/c99/fmt_print.py +915 -0
  182. smallworld/state/models/c99/fmt_scan.py +864 -0
  183. smallworld/state/models/c99/math.py +362 -0
  184. smallworld/state/models/c99/signal.py +71 -0
  185. smallworld/state/models/c99/stdio.py +1305 -0
  186. smallworld/state/models/c99/stdlib.py +595 -0
  187. smallworld/state/models/c99/string.py +674 -0
  188. smallworld/state/models/c99/time.py +340 -0
  189. smallworld/state/models/c99/utils.py +89 -0
  190. smallworld/state/models/cstd.py +759 -0
  191. smallworld/state/models/errno.py +581 -0
  192. smallworld/state/models/filedesc.py +515 -0
  193. smallworld/state/models/i386/__init__.py +1 -0
  194. smallworld/state/models/i386/systemv/__init__.py +6 -0
  195. smallworld/state/models/i386/systemv/c99/__init__.py +12 -0
  196. smallworld/state/models/i386/systemv/c99/signal.py +16 -0
  197. smallworld/state/models/i386/systemv/c99/stdio.py +265 -0
  198. smallworld/state/models/i386/systemv/c99/stdlib.py +169 -0
  199. smallworld/state/models/i386/systemv/c99/string.py +139 -0
  200. smallworld/state/models/i386/systemv/c99/time.py +61 -0
  201. smallworld/state/models/i386/systemv/posix/__init__.py +6 -0
  202. smallworld/state/models/i386/systemv/posix/libgen.py +16 -0
  203. smallworld/state/models/i386/systemv/posix/signal.py +157 -0
  204. smallworld/state/models/i386/systemv/systemv.py +71 -0
  205. smallworld/state/models/loongarch64/__init__.py +1 -0
  206. smallworld/state/models/loongarch64/systemv/__init__.py +6 -0
  207. smallworld/state/models/loongarch64/systemv/c99/__init__.py +12 -0
  208. smallworld/state/models/loongarch64/systemv/c99/signal.py +16 -0
  209. smallworld/state/models/loongarch64/systemv/c99/stdio.py +265 -0
  210. smallworld/state/models/loongarch64/systemv/c99/stdlib.py +169 -0
  211. smallworld/state/models/loongarch64/systemv/c99/string.py +139 -0
  212. smallworld/state/models/loongarch64/systemv/c99/time.py +61 -0
  213. smallworld/state/models/loongarch64/systemv/posix/__init__.py +6 -0
  214. smallworld/state/models/loongarch64/systemv/posix/libgen.py +16 -0
  215. smallworld/state/models/loongarch64/systemv/posix/signal.py +157 -0
  216. smallworld/state/models/loongarch64/systemv/systemv.py +83 -0
  217. smallworld/state/models/mips/__init__.py +1 -0
  218. smallworld/state/models/mips/systemv/__init__.py +6 -0
  219. smallworld/state/models/mips/systemv/c99/__init__.py +12 -0
  220. smallworld/state/models/mips/systemv/c99/signal.py +16 -0
  221. smallworld/state/models/mips/systemv/c99/stdio.py +265 -0
  222. smallworld/state/models/mips/systemv/c99/stdlib.py +169 -0
  223. smallworld/state/models/mips/systemv/c99/string.py +139 -0
  224. smallworld/state/models/mips/systemv/c99/time.py +61 -0
  225. smallworld/state/models/mips/systemv/posix/__init__.py +6 -0
  226. smallworld/state/models/mips/systemv/posix/libgen.py +16 -0
  227. smallworld/state/models/mips/systemv/posix/signal.py +157 -0
  228. smallworld/state/models/mips/systemv/systemv.py +78 -0
  229. smallworld/state/models/mips64/__init__.py +1 -0
  230. smallworld/state/models/mips64/systemv/__init__.py +6 -0
  231. smallworld/state/models/mips64/systemv/c99/__init__.py +12 -0
  232. smallworld/state/models/mips64/systemv/c99/signal.py +16 -0
  233. smallworld/state/models/mips64/systemv/c99/stdio.py +265 -0
  234. smallworld/state/models/mips64/systemv/c99/stdlib.py +169 -0
  235. smallworld/state/models/mips64/systemv/c99/string.py +139 -0
  236. smallworld/state/models/mips64/systemv/c99/time.py +61 -0
  237. smallworld/state/models/mips64/systemv/posix/__init__.py +6 -0
  238. smallworld/state/models/mips64/systemv/posix/libgen.py +16 -0
  239. smallworld/state/models/mips64/systemv/posix/signal.py +157 -0
  240. smallworld/state/models/mips64/systemv/systemv.py +98 -0
  241. smallworld/state/models/mips64el/__init__.py +1 -0
  242. smallworld/state/models/mips64el/systemv/__init__.py +6 -0
  243. smallworld/state/models/mips64el/systemv/c99/__init__.py +12 -0
  244. smallworld/state/models/mips64el/systemv/c99/signal.py +16 -0
  245. smallworld/state/models/mips64el/systemv/c99/stdio.py +265 -0
  246. smallworld/state/models/mips64el/systemv/c99/stdlib.py +169 -0
  247. smallworld/state/models/mips64el/systemv/c99/string.py +139 -0
  248. smallworld/state/models/mips64el/systemv/c99/time.py +61 -0
  249. smallworld/state/models/mips64el/systemv/posix/__init__.py +6 -0
  250. smallworld/state/models/mips64el/systemv/posix/libgen.py +16 -0
  251. smallworld/state/models/mips64el/systemv/posix/signal.py +157 -0
  252. smallworld/state/models/mips64el/systemv/systemv.py +96 -0
  253. smallworld/state/models/mipsel/__init__.py +1 -0
  254. smallworld/state/models/mipsel/systemv/__init__.py +6 -0
  255. smallworld/state/models/mipsel/systemv/c99/__init__.py +12 -0
  256. smallworld/state/models/mipsel/systemv/c99/signal.py +16 -0
  257. smallworld/state/models/mipsel/systemv/c99/stdio.py +265 -0
  258. smallworld/state/models/mipsel/systemv/c99/stdlib.py +169 -0
  259. smallworld/state/models/mipsel/systemv/c99/string.py +139 -0
  260. smallworld/state/models/mipsel/systemv/c99/time.py +61 -0
  261. smallworld/state/models/mipsel/systemv/posix/__init__.py +6 -0
  262. smallworld/state/models/mipsel/systemv/posix/libgen.py +16 -0
  263. smallworld/state/models/mipsel/systemv/posix/signal.py +157 -0
  264. smallworld/state/models/mipsel/systemv/systemv.py +78 -0
  265. smallworld/state/models/model.py +27 -2
  266. smallworld/state/models/posix/__init__.py +6 -0
  267. smallworld/state/models/posix/libgen.py +123 -0
  268. smallworld/state/models/posix/signal.py +690 -0
  269. smallworld/state/models/powerpc/__init__.py +1 -0
  270. smallworld/state/models/powerpc/systemv/__init__.py +6 -0
  271. smallworld/state/models/powerpc/systemv/c99/__init__.py +12 -0
  272. smallworld/state/models/powerpc/systemv/c99/signal.py +16 -0
  273. smallworld/state/models/powerpc/systemv/c99/stdio.py +265 -0
  274. smallworld/state/models/powerpc/systemv/c99/stdlib.py +169 -0
  275. smallworld/state/models/powerpc/systemv/c99/string.py +139 -0
  276. smallworld/state/models/powerpc/systemv/c99/time.py +61 -0
  277. smallworld/state/models/powerpc/systemv/posix/__init__.py +6 -0
  278. smallworld/state/models/powerpc/systemv/posix/libgen.py +16 -0
  279. smallworld/state/models/powerpc/systemv/posix/signal.py +157 -0
  280. smallworld/state/models/powerpc/systemv/systemv.py +93 -0
  281. smallworld/state/models/riscv64/__init__.py +1 -0
  282. smallworld/state/models/riscv64/systemv/__init__.py +6 -0
  283. smallworld/state/models/riscv64/systemv/c99/__init__.py +12 -0
  284. smallworld/state/models/riscv64/systemv/c99/signal.py +16 -0
  285. smallworld/state/models/riscv64/systemv/c99/stdio.py +265 -0
  286. smallworld/state/models/riscv64/systemv/c99/stdlib.py +169 -0
  287. smallworld/state/models/riscv64/systemv/c99/string.py +139 -0
  288. smallworld/state/models/riscv64/systemv/c99/time.py +61 -0
  289. smallworld/state/models/riscv64/systemv/posix/__init__.py +6 -0
  290. smallworld/state/models/riscv64/systemv/posix/libgen.py +16 -0
  291. smallworld/state/models/riscv64/systemv/posix/signal.py +157 -0
  292. smallworld/state/models/riscv64/systemv/systemv.py +85 -0
  293. smallworld/state/state.py +65 -24
  294. smallworld/state/unstable/elf.py +16 -31
  295. smallworld/utils.py +6 -1
  296. {smallworld_re-1.0.2.dist-info → smallworld_re-2.0.0.dist-info}/METADATA +76 -43
  297. smallworld_re-2.0.0.dist-info/RECORD +374 -0
  298. {smallworld_re-1.0.2.dist-info → smallworld_re-2.0.0.dist-info}/WHEEL +1 -1
  299. smallworld/state/models/x86/__init__.py +0 -2
  300. smallworld/state/models/x86/microsoftcdecl.py +0 -35
  301. smallworld/state/models/x86/systemv.py +0 -240
  302. smallworld_re-1.0.2.dist-info/RECORD +0 -166
  303. /smallworld/state/models/{posix.py → _posix.py} +0 -0
  304. {smallworld_re-1.0.2.dist-info → smallworld_re-2.0.0.dist-info}/entry_points.txt +0 -0
  305. {smallworld_re-1.0.2.dist-info → smallworld_re-2.0.0.dist-info/licenses}/LICENSE.txt +0 -0
  306. {smallworld_re-1.0.2.dist-info → smallworld_re-2.0.0.dist-info}/top_level.txt +0 -0
smallworld/emulators/unicorn/machdefs/arm.py CHANGED
@@ -1,4 +1,3 @@
1
- import capstone
2
1
  import unicorn
3
2
 
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3
  from ....platforms import Architecture, Byteorder
@@ -11,37 +10,32 @@ class ARMMachineDef(UnicornMachineDef):
11
10
  uc_arch = unicorn.UC_ARCH_ARM
12
11
  uc_mode = unicorn.UC_MODE_ARM
13
12
 
14
- cs_arch = capstone.CS_ARCH_ARM
15
- cs_mode = capstone.CS_MODE_ARM
16
-
17
- pc_reg = "pc"
18
-
19
13
  def __init__(self):
20
14
  self._registers = {
21
- "r0": (unicorn.arm_const.UC_ARM_REG_R0, "r0", 0, 4),
22
- "r1": (unicorn.arm_const.UC_ARM_REG_R1, "r1", 0, 4),
23
- "r2": (unicorn.arm_const.UC_ARM_REG_R2, "r2", 0, 4),
24
- "r3": (unicorn.arm_const.UC_ARM_REG_R3, "r3", 0, 4),
25
- "r4": (unicorn.arm_const.UC_ARM_REG_R4, "r4", 0, 4),
26
- "r5": (unicorn.arm_const.UC_ARM_REG_R5, "r5", 0, 4),
27
- "r6": (unicorn.arm_const.UC_ARM_REG_R6, "r6", 0, 4),
28
- "r7": (unicorn.arm_const.UC_ARM_REG_R7, "r7", 0, 4),
29
- "r8": (unicorn.arm_const.UC_ARM_REG_R8, "r8", 0, 4),
15
+ "r0": unicorn.arm_const.UC_ARM_REG_R0,
16
+ "r1": unicorn.arm_const.UC_ARM_REG_R1,
17
+ "r2": unicorn.arm_const.UC_ARM_REG_R2,
18
+ "r3": unicorn.arm_const.UC_ARM_REG_R3,
19
+ "r4": unicorn.arm_const.UC_ARM_REG_R4,
20
+ "r5": unicorn.arm_const.UC_ARM_REG_R5,
21
+ "r6": unicorn.arm_const.UC_ARM_REG_R6,
22
+ "r7": unicorn.arm_const.UC_ARM_REG_R7,
23
+ "r8": unicorn.arm_const.UC_ARM_REG_R8,
30
24
  # r9 doubles as the Static base pointer
31
- "r9": (unicorn.arm_const.UC_ARM_REG_R9, "r9", 0, 4),
32
- "sb": (unicorn.arm_const.UC_ARM_REG_SB, "r9", 0, 4),
25
+ "r9": unicorn.arm_const.UC_ARM_REG_R9,
26
+ "sb": unicorn.arm_const.UC_ARM_REG_SB,
33
27
  # r10 doubles as the Stack Limit pointer
34
- "r10": (unicorn.arm_const.UC_ARM_REG_R10, "r10", 0, 4),
35
- "sl": (unicorn.arm_const.UC_ARM_REG_SL, "r10", 0, 4),
28
+ "r10": unicorn.arm_const.UC_ARM_REG_R10,
29
+ "sl": unicorn.arm_const.UC_ARM_REG_SL,
36
30
  # r11 doubles as the Frame Pointer, if desired.
37
- "r11": (unicorn.arm_const.UC_ARM_REG_R11, "r11", 0, 4),
38
- "fp": (unicorn.arm_const.UC_ARM_REG_FP, "r11", 0, 4),
31
+ "r11": unicorn.arm_const.UC_ARM_REG_R11,
32
+ "fp": unicorn.arm_const.UC_ARM_REG_FP,
39
33
  # r12 doubles as the Intra-call scratch register
40
- "r12": (unicorn.arm_const.UC_ARM_REG_R12, "r12", 0, 4),
41
- "ip": (unicorn.arm_const.UC_ARM_REG_IP, "r12", 0, 4),
42
- "sp": (unicorn.arm_const.UC_ARM_REG_SP, "sp", 0, 4),
43
- "lr": (unicorn.arm_const.UC_ARM_REG_LR, "lr", 0, 4),
44
- "pc": (unicorn.arm_const.UC_ARM_REG_PC, "pc", 0, 4),
34
+ "r12": unicorn.arm_const.UC_ARM_REG_R12,
35
+ "ip": unicorn.arm_const.UC_ARM_REG_IP,
36
+ "sp": unicorn.arm_const.UC_ARM_REG_SP,
37
+ "lr": unicorn.arm_const.UC_ARM_REG_LR,
38
+ "pc": unicorn.arm_const.UC_ARM_REG_PC,
45
39
  }
46
40
 
47
41
 
@@ -55,18 +49,13 @@ class ARMMachineMixinM:
55
49
  # NOTE: PSR is aliased to CPSR
56
50
  # This is an artifact of the fact that Unicorn
57
51
  # seems to emulate a mash-up of M- and A-series arm.
58
- "psr": (unicorn.arm_const.UC_ARM_REG_CPSR, "psr", 0, 4),
59
- "primask": (unicorn.arm_const.UC_ARM_REG_PRIMASK, "primask", 0, 4),
60
- "basepri": (unicorn.arm_const.UC_ARM_REG_BASEPRI, "basepri", 0, 4),
61
- "faultmask": (
62
- unicorn.arm_const.UC_ARM_REG_FAULTMASK,
63
- "faultmask",
64
- 0,
65
- 4,
66
- ),
67
- "control": (unicorn.arm_const.UC_ARM_REG_CONTROL, "control", 0, 4),
68
- "msp": (unicorn.arm_const.UC_ARM_REG_MSP, "msp", 0, 4),
69
- "psp": (unicorn.arm_const.UC_ARM_REG_PSP, "psp", 0, 4),
52
+ "psr": unicorn.arm_const.UC_ARM_REG_CPSR,
53
+ "primask": unicorn.arm_const.UC_ARM_REG_PRIMASK,
54
+ "basepri": unicorn.arm_const.UC_ARM_REG_BASEPRI,
55
+ "faultmask": unicorn.arm_const.UC_ARM_REG_FAULTMASK,
56
+ "control": unicorn.arm_const.UC_ARM_REG_CONTROL,
57
+ "msp": unicorn.arm_const.UC_ARM_REG_MSP,
58
+ "psp": unicorn.arm_const.UC_ARM_REG_PSP,
70
59
  }
71
60
  )
72
61
 
@@ -78,42 +67,42 @@ class ARMMachineMixinRA:
78
67
  super().__init__()
79
68
  self._registers.update(
80
69
  {
81
- "cpsr": (unicorn.arm_const.UC_ARM_REG_CPSR, "cpsr", 0, 4),
82
- "spsr": (unicorn.arm_const.UC_ARM_REG_SPSR, "spsr", 0, 4),
70
+ "cpsr": unicorn.arm_const.UC_ARM_REG_CPSR,
71
+ "spsr": unicorn.arm_const.UC_ARM_REG_SPSR,
83
72
  # NOTE: None of the banked registers have Unicorn IDs
84
- "sp_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_usr", 0, 4),
85
- "lr_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_usr", 0, 4),
86
- "r8_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "r8_usr", 0, 4),
87
- "r9_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "r9_usr", 0, 4),
88
- "r10_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "r10_usr", 0, 4),
89
- "r11_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "r11_usr", 0, 4),
90
- "r12_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "r12_usr", 0, 4),
91
- "sp_hyp": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_hyp", 0, 4),
92
- "spsr_hyp": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_hyp", 0, 4),
93
- "elr_hyp": (unicorn.arm_const.UC_ARM_REG_INVALID, "elr_hyp", 0, 4),
94
- "sp_svc": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_svc", 0, 4),
95
- "lr_svc": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_svc", 0, 4),
96
- "spsr_svc": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_svc", 0, 4),
97
- "sp_abt": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_abt", 0, 4),
98
- "lr_abt": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_abt", 0, 4),
99
- "spsr_abt": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_abt", 0, 4),
100
- "sp_und": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_und", 0, 4),
101
- "lr_und": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_und", 0, 4),
102
- "spsr_und": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_und", 0, 4),
103
- "sp_mon": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_mon", 0, 4),
104
- "lr_mon": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_mon", 0, 4),
105
- "spsr_mon": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_mon", 0, 4),
106
- "sp_irq": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_irq", 0, 4),
107
- "lr_irq": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_irq", 0, 4),
108
- "spsr_irq": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_irq", 0, 4),
109
- "sp_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_fiq", 0, 4),
110
- "lr_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_fiq", 0, 4),
111
- "spsr_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_fiq", 0, 4),
112
- "r8_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "r8_fiq", 0, 4),
113
- "r9_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "r9_fiq", 0, 4),
114
- "r10_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "r10_fiq", 0, 4),
115
- "r11_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "r11_fiq", 0, 4),
116
- "r12_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "r12_fiq", 0, 4),
73
+ "sp_usr": unicorn.arm_const.UC_ARM_REG_INVALID,
74
+ "lr_usr": unicorn.arm_const.UC_ARM_REG_INVALID,
75
+ "r8_usr": unicorn.arm_const.UC_ARM_REG_INVALID,
76
+ "r9_usr": unicorn.arm_const.UC_ARM_REG_INVALID,
77
+ "r10_usr": unicorn.arm_const.UC_ARM_REG_INVALID,
78
+ "r11_usr": unicorn.arm_const.UC_ARM_REG_INVALID,
79
+ "r12_usr": unicorn.arm_const.UC_ARM_REG_INVALID,
80
+ "sp_hyp": unicorn.arm_const.UC_ARM_REG_INVALID,
81
+ "spsr_hyp": unicorn.arm_const.UC_ARM_REG_INVALID,
82
+ "elr_hyp": unicorn.arm_const.UC_ARM_REG_INVALID,
83
+ "sp_svc": unicorn.arm_const.UC_ARM_REG_INVALID,
84
+ "lr_svc": unicorn.arm_const.UC_ARM_REG_INVALID,
85
+ "spsr_svc": unicorn.arm_const.UC_ARM_REG_INVALID,
86
+ "sp_abt": unicorn.arm_const.UC_ARM_REG_INVALID,
87
+ "lr_abt": unicorn.arm_const.UC_ARM_REG_INVALID,
88
+ "spsr_abt": unicorn.arm_const.UC_ARM_REG_INVALID,
89
+ "sp_und": unicorn.arm_const.UC_ARM_REG_INVALID,
90
+ "lr_und": unicorn.arm_const.UC_ARM_REG_INVALID,
91
+ "spsr_und": unicorn.arm_const.UC_ARM_REG_INVALID,
92
+ "sp_mon": unicorn.arm_const.UC_ARM_REG_INVALID,
93
+ "lr_mon": unicorn.arm_const.UC_ARM_REG_INVALID,
94
+ "spsr_mon": unicorn.arm_const.UC_ARM_REG_INVALID,
95
+ "sp_irq": unicorn.arm_const.UC_ARM_REG_INVALID,
96
+ "lr_irq": unicorn.arm_const.UC_ARM_REG_INVALID,
97
+ "spsr_irq": unicorn.arm_const.UC_ARM_REG_INVALID,
98
+ "sp_fiq": unicorn.arm_const.UC_ARM_REG_INVALID,
99
+ "lr_fiq": unicorn.arm_const.UC_ARM_REG_INVALID,
100
+ "spsr_fiq": unicorn.arm_const.UC_ARM_REG_INVALID,
101
+ "r8_fiq": unicorn.arm_const.UC_ARM_REG_INVALID,
102
+ "r9_fiq": unicorn.arm_const.UC_ARM_REG_INVALID,
103
+ "r10_fiq": unicorn.arm_const.UC_ARM_REG_INVALID,
104
+ "r11_fiq": unicorn.arm_const.UC_ARM_REG_INVALID,
105
+ "r12_fiq": unicorn.arm_const.UC_ARM_REG_INVALID,
117
106
  }
118
107
  )
119
108
 
@@ -125,59 +114,59 @@ class ARMMachineMixinFP:
125
114
  super().__init__()
126
115
  self._registers.update(
127
116
  {
128
- "fpscr": (unicorn.arm_const.UC_ARM_REG_FPSCR, "fpscr", 0, 4),
129
- "fpexc": (unicorn.arm_const.UC_ARM_REG_FPEXC, "fpexc", 0, 4),
130
- "fpsid": (unicorn.arm_const.UC_ARM_REG_FPSID, "fpsid", 0, 4),
131
- "mvfr0": (unicorn.arm_const.UC_ARM_REG_INVALID, "mvfr0", 0, 4),
132
- "mvfr1": (unicorn.arm_const.UC_ARM_REG_INVALID, "mvfr1", 0, 4),
133
- "d0": (unicorn.arm_const.UC_ARM_REG_D0, "d0", 0, 8),
134
- "s0": (unicorn.arm_const.UC_ARM_REG_S0, "d0", 0, 4),
135
- "s1": (unicorn.arm_const.UC_ARM_REG_S1, "d0", 4, 4),
136
- "d1": (unicorn.arm_const.UC_ARM_REG_D1, "d1", 0, 8),
137
- "s2": (unicorn.arm_const.UC_ARM_REG_S2, "d1", 0, 4),
138
- "s3": (unicorn.arm_const.UC_ARM_REG_S3, "d1", 4, 4),
139
- "d2": (unicorn.arm_const.UC_ARM_REG_D2, "d2", 0, 8),
140
- "s4": (unicorn.arm_const.UC_ARM_REG_S4, "d2", 0, 4),
141
- "s5": (unicorn.arm_const.UC_ARM_REG_S5, "d2", 4, 4),
142
- "d3": (unicorn.arm_const.UC_ARM_REG_D3, "d3", 0, 8),
143
- "s6": (unicorn.arm_const.UC_ARM_REG_S6, "d3", 0, 4),
144
- "s7": (unicorn.arm_const.UC_ARM_REG_S7, "d3", 4, 4),
145
- "d4": (unicorn.arm_const.UC_ARM_REG_D4, "d4", 0, 8),
146
- "s8": (unicorn.arm_const.UC_ARM_REG_S8, "d4", 0, 4),
147
- "s9": (unicorn.arm_const.UC_ARM_REG_S9, "d4", 4, 4),
148
- "d5": (unicorn.arm_const.UC_ARM_REG_D5, "d5", 0, 8),
149
- "s10": (unicorn.arm_const.UC_ARM_REG_S10, "d5", 0, 4),
150
- "s11": (unicorn.arm_const.UC_ARM_REG_S11, "d5", 4, 4),
151
- "d6": (unicorn.arm_const.UC_ARM_REG_D6, "d6", 0, 8),
152
- "s12": (unicorn.arm_const.UC_ARM_REG_S12, "d6", 0, 4),
153
- "s13": (unicorn.arm_const.UC_ARM_REG_S13, "d6", 4, 4),
154
- "d7": (unicorn.arm_const.UC_ARM_REG_D7, "d7", 0, 8),
155
- "s14": (unicorn.arm_const.UC_ARM_REG_S14, "d7", 0, 4),
156
- "s15": (unicorn.arm_const.UC_ARM_REG_S15, "d7", 4, 4),
157
- "d8": (unicorn.arm_const.UC_ARM_REG_D8, "d8", 0, 8),
158
- "s16": (unicorn.arm_const.UC_ARM_REG_S16, "d8", 0, 4),
159
- "s17": (unicorn.arm_const.UC_ARM_REG_S17, "d8", 4, 4),
160
- "d9": (unicorn.arm_const.UC_ARM_REG_D9, "d9", 0, 8),
161
- "s18": (unicorn.arm_const.UC_ARM_REG_S18, "d9", 0, 4),
162
- "s19": (unicorn.arm_const.UC_ARM_REG_S19, "d9", 4, 4),
163
- "d10": (unicorn.arm_const.UC_ARM_REG_D10, "d10", 0, 8),
164
- "s20": (unicorn.arm_const.UC_ARM_REG_S20, "d10", 0, 4),
165
- "s21": (unicorn.arm_const.UC_ARM_REG_S21, "d10", 4, 4),
166
- "d11": (unicorn.arm_const.UC_ARM_REG_D11, "d11", 0, 8),
167
- "s22": (unicorn.arm_const.UC_ARM_REG_S22, "d11", 0, 4),
168
- "s23": (unicorn.arm_const.UC_ARM_REG_S23, "d11", 4, 4),
169
- "d12": (unicorn.arm_const.UC_ARM_REG_D12, "d12", 0, 8),
170
- "s24": (unicorn.arm_const.UC_ARM_REG_S24, "d12", 0, 4),
171
- "s25": (unicorn.arm_const.UC_ARM_REG_S25, "d12", 4, 4),
172
- "d13": (unicorn.arm_const.UC_ARM_REG_D13, "d13", 0, 8),
173
- "s26": (unicorn.arm_const.UC_ARM_REG_S26, "d13", 0, 4),
174
- "s27": (unicorn.arm_const.UC_ARM_REG_S27, "d13", 4, 4),
175
- "d14": (unicorn.arm_const.UC_ARM_REG_D14, "d14", 0, 8),
176
- "s28": (unicorn.arm_const.UC_ARM_REG_S28, "d14", 0, 4),
177
- "s29": (unicorn.arm_const.UC_ARM_REG_S29, "d14", 4, 4),
178
- "d15": (unicorn.arm_const.UC_ARM_REG_D15, "d15", 0, 8),
179
- "s30": (unicorn.arm_const.UC_ARM_REG_S30, "d15", 0, 4),
180
- "s31": (unicorn.arm_const.UC_ARM_REG_S31, "d15", 4, 4),
117
+ "fpscr": unicorn.arm_const.UC_ARM_REG_FPSCR,
118
+ "fpexc": unicorn.arm_const.UC_ARM_REG_FPEXC,
119
+ "fpsid": unicorn.arm_const.UC_ARM_REG_FPSID,
120
+ "mvfr0": unicorn.arm_const.UC_ARM_REG_INVALID,
121
+ "mvfr1": unicorn.arm_const.UC_ARM_REG_INVALID,
122
+ "d0": unicorn.arm_const.UC_ARM_REG_D0,
123
+ "s0": unicorn.arm_const.UC_ARM_REG_S0,
124
+ "s1": unicorn.arm_const.UC_ARM_REG_S1,
125
+ "d1": unicorn.arm_const.UC_ARM_REG_D1,
126
+ "s2": unicorn.arm_const.UC_ARM_REG_S2,
127
+ "s3": unicorn.arm_const.UC_ARM_REG_S3,
128
+ "d2": unicorn.arm_const.UC_ARM_REG_D2,
129
+ "s4": unicorn.arm_const.UC_ARM_REG_S4,
130
+ "s5": unicorn.arm_const.UC_ARM_REG_S5,
131
+ "d3": unicorn.arm_const.UC_ARM_REG_D3,
132
+ "s6": unicorn.arm_const.UC_ARM_REG_S6,
133
+ "s7": unicorn.arm_const.UC_ARM_REG_S7,
134
+ "d4": unicorn.arm_const.UC_ARM_REG_D4,
135
+ "s8": unicorn.arm_const.UC_ARM_REG_S8,
136
+ "s9": unicorn.arm_const.UC_ARM_REG_S9,
137
+ "d5": unicorn.arm_const.UC_ARM_REG_D5,
138
+ "s10": unicorn.arm_const.UC_ARM_REG_S10,
139
+ "s11": unicorn.arm_const.UC_ARM_REG_S11,
140
+ "d6": unicorn.arm_const.UC_ARM_REG_D6,
141
+ "s12": unicorn.arm_const.UC_ARM_REG_S12,
142
+ "s13": unicorn.arm_const.UC_ARM_REG_S13,
143
+ "d7": unicorn.arm_const.UC_ARM_REG_D7,
144
+ "s14": unicorn.arm_const.UC_ARM_REG_S14,
145
+ "s15": unicorn.arm_const.UC_ARM_REG_S15,
146
+ "d8": unicorn.arm_const.UC_ARM_REG_D8,
147
+ "s16": unicorn.arm_const.UC_ARM_REG_S16,
148
+ "s17": unicorn.arm_const.UC_ARM_REG_S17,
149
+ "d9": unicorn.arm_const.UC_ARM_REG_D9,
150
+ "s18": unicorn.arm_const.UC_ARM_REG_S18,
151
+ "s19": unicorn.arm_const.UC_ARM_REG_S19,
152
+ "d10": unicorn.arm_const.UC_ARM_REG_D10,
153
+ "s20": unicorn.arm_const.UC_ARM_REG_S20,
154
+ "s21": unicorn.arm_const.UC_ARM_REG_S21,
155
+ "d11": unicorn.arm_const.UC_ARM_REG_D11,
156
+ "s22": unicorn.arm_const.UC_ARM_REG_S22,
157
+ "s23": unicorn.arm_const.UC_ARM_REG_S23,
158
+ "d12": unicorn.arm_const.UC_ARM_REG_D12,
159
+ "s24": unicorn.arm_const.UC_ARM_REG_S24,
160
+ "s25": unicorn.arm_const.UC_ARM_REG_S25,
161
+ "d13": unicorn.arm_const.UC_ARM_REG_D13,
162
+ "s26": unicorn.arm_const.UC_ARM_REG_S26,
163
+ "s27": unicorn.arm_const.UC_ARM_REG_S27,
164
+ "d14": unicorn.arm_const.UC_ARM_REG_D14,
165
+ "s28": unicorn.arm_const.UC_ARM_REG_S28,
166
+ "s29": unicorn.arm_const.UC_ARM_REG_S29,
167
+ "d15": unicorn.arm_const.UC_ARM_REG_D15,
168
+ "s30": unicorn.arm_const.UC_ARM_REG_S30,
169
+ "s31": unicorn.arm_const.UC_ARM_REG_S31,
181
170
  }
182
171
  )
183
172
 
@@ -189,91 +178,91 @@ class ARMMachineMixinVFP:
189
178
  super().__init__()
190
179
  self._registers.update(
191
180
  {
192
- "fpscr": (unicorn.arm_const.UC_ARM_REG_FPSCR, "fpscr", 0, 4),
193
- "fpexc": (unicorn.arm_const.UC_ARM_REG_FPEXC, "fpexc", 0, 4),
194
- "fpsid": (unicorn.arm_const.UC_ARM_REG_FPSID, "fpsid", 0, 4),
195
- "mvfr0": (unicorn.arm_const.UC_ARM_REG_INVALID, "mvfr0", 0, 4),
196
- "mvfr1": (unicorn.arm_const.UC_ARM_REG_INVALID, "mvfr1", 0, 4),
197
- "q0": (unicorn.arm_const.UC_ARM_REG_Q0, "q0", 0, 16),
198
- "d0": (unicorn.arm_const.UC_ARM_REG_D0, "q0", 0, 8),
199
- "s0": (unicorn.arm_const.UC_ARM_REG_S0, "q0", 0, 4),
200
- "s1": (unicorn.arm_const.UC_ARM_REG_S1, "q0", 4, 4),
201
- "d1": (unicorn.arm_const.UC_ARM_REG_D1, "q0", 8, 8),
202
- "s2": (unicorn.arm_const.UC_ARM_REG_S2, "q0", 8, 4),
203
- "s3": (unicorn.arm_const.UC_ARM_REG_S3, "q0", 12, 4),
204
- "q1": (unicorn.arm_const.UC_ARM_REG_Q1, "q1", 0, 16),
205
- "d2": (unicorn.arm_const.UC_ARM_REG_D2, "q1", 0, 8),
206
- "s4": (unicorn.arm_const.UC_ARM_REG_S4, "q1", 0, 4),
207
- "s5": (unicorn.arm_const.UC_ARM_REG_S5, "q1", 4, 4),
208
- "d3": (unicorn.arm_const.UC_ARM_REG_D3, "q1", 8, 8),
209
- "s6": (unicorn.arm_const.UC_ARM_REG_S6, "q1", 8, 4),
210
- "s7": (unicorn.arm_const.UC_ARM_REG_S7, "q1", 12, 4),
211
- "q2": (unicorn.arm_const.UC_ARM_REG_Q2, "q2", 0, 16),
212
- "d4": (unicorn.arm_const.UC_ARM_REG_D4, "q2", 0, 8),
213
- "s8": (unicorn.arm_const.UC_ARM_REG_S8, "q2", 0, 4),
214
- "s9": (unicorn.arm_const.UC_ARM_REG_S9, "q2", 4, 4),
215
- "d5": (unicorn.arm_const.UC_ARM_REG_D5, "q2", 8, 8),
216
- "s10": (unicorn.arm_const.UC_ARM_REG_S10, "q2", 8, 4),
217
- "s11": (unicorn.arm_const.UC_ARM_REG_S11, "q2", 12, 4),
218
- "q3": (unicorn.arm_const.UC_ARM_REG_Q3, "q3", 0, 16),
219
- "d6": (unicorn.arm_const.UC_ARM_REG_D6, "q3", 0, 8),
220
- "s12": (unicorn.arm_const.UC_ARM_REG_S12, "q3", 0, 4),
221
- "s13": (unicorn.arm_const.UC_ARM_REG_S13, "q3", 4, 4),
222
- "d7": (unicorn.arm_const.UC_ARM_REG_D7, "q3", 8, 8),
223
- "s14": (unicorn.arm_const.UC_ARM_REG_S14, "q3", 8, 4),
224
- "s15": (unicorn.arm_const.UC_ARM_REG_S15, "q3", 12, 4),
225
- "q4": (unicorn.arm_const.UC_ARM_REG_Q4, "q4", 0, 16),
226
- "d8": (unicorn.arm_const.UC_ARM_REG_D8, "q4", 0, 8),
227
- "s16": (unicorn.arm_const.UC_ARM_REG_S16, "q4", 0, 4),
228
- "s17": (unicorn.arm_const.UC_ARM_REG_S17, "q4", 4, 4),
229
- "d9": (unicorn.arm_const.UC_ARM_REG_D9, "q4", 8, 8),
230
- "s18": (unicorn.arm_const.UC_ARM_REG_S18, "q4", 8, 4),
231
- "s19": (unicorn.arm_const.UC_ARM_REG_S19, "q4", 12, 4),
232
- "q5": (unicorn.arm_const.UC_ARM_REG_Q5, "q5", 0, 16),
233
- "d10": (unicorn.arm_const.UC_ARM_REG_D10, "q5", 0, 8),
234
- "s20": (unicorn.arm_const.UC_ARM_REG_S20, "q5", 0, 4),
235
- "s21": (unicorn.arm_const.UC_ARM_REG_S21, "q5", 4, 4),
236
- "d11": (unicorn.arm_const.UC_ARM_REG_D11, "q5", 8, 8),
237
- "s22": (unicorn.arm_const.UC_ARM_REG_S22, "q5", 8, 4),
238
- "s23": (unicorn.arm_const.UC_ARM_REG_S23, "q5", 12, 4),
239
- "q6": (unicorn.arm_const.UC_ARM_REG_Q6, "q6", 0, 16),
240
- "d12": (unicorn.arm_const.UC_ARM_REG_D12, "q6", 0, 8),
241
- "s24": (unicorn.arm_const.UC_ARM_REG_S24, "q6", 0, 4),
242
- "s25": (unicorn.arm_const.UC_ARM_REG_S25, "q6", 4, 4),
243
- "d13": (unicorn.arm_const.UC_ARM_REG_D13, "q6", 8, 8),
244
- "s26": (unicorn.arm_const.UC_ARM_REG_S26, "q6", 8, 4),
245
- "s27": (unicorn.arm_const.UC_ARM_REG_S27, "q6", 12, 4),
246
- "q7": (unicorn.arm_const.UC_ARM_REG_Q7, "q7", 0, 16),
247
- "d14": (unicorn.arm_const.UC_ARM_REG_D14, "q7", 0, 8),
248
- "s28": (unicorn.arm_const.UC_ARM_REG_S28, "q7", 0, 4),
249
- "s29": (unicorn.arm_const.UC_ARM_REG_S29, "q7", 4, 4),
250
- "d15": (unicorn.arm_const.UC_ARM_REG_D15, "q7", 8, 8),
251
- "s30": (unicorn.arm_const.UC_ARM_REG_S30, "q7", 8, 4),
252
- "s31": (unicorn.arm_const.UC_ARM_REG_S31, "q7", 12, 4),
253
- "q8": (unicorn.arm_const.UC_ARM_REG_Q8, "q8", 0, 16),
254
- "d16": (unicorn.arm_const.UC_ARM_REG_D16, "q8", 0, 8),
255
- "d17": (unicorn.arm_const.UC_ARM_REG_D17, "q8", 8, 8),
256
- "q9": (unicorn.arm_const.UC_ARM_REG_Q9, "q9", 0, 16),
257
- "d18": (unicorn.arm_const.UC_ARM_REG_D18, "q9", 0, 8),
258
- "d19": (unicorn.arm_const.UC_ARM_REG_D19, "q9", 8, 8),
259
- "q10": (unicorn.arm_const.UC_ARM_REG_Q10, "q10", 0, 16),
260
- "d20": (unicorn.arm_const.UC_ARM_REG_D20, "q10", 0, 8),
261
- "d21": (unicorn.arm_const.UC_ARM_REG_D21, "q10", 8, 8),
262
- "q11": (unicorn.arm_const.UC_ARM_REG_Q11, "q11", 0, 16),
263
- "d22": (unicorn.arm_const.UC_ARM_REG_D22, "q11", 0, 8),
264
- "d23": (unicorn.arm_const.UC_ARM_REG_D23, "q11", 8, 8),
265
- "q12": (unicorn.arm_const.UC_ARM_REG_Q12, "q12", 0, 16),
266
- "d24": (unicorn.arm_const.UC_ARM_REG_D24, "q12", 0, 8),
267
- "d25": (unicorn.arm_const.UC_ARM_REG_D25, "q12", 8, 8),
268
- "q13": (unicorn.arm_const.UC_ARM_REG_Q13, "q13", 0, 16),
269
- "d26": (unicorn.arm_const.UC_ARM_REG_D26, "q13", 0, 8),
270
- "d27": (unicorn.arm_const.UC_ARM_REG_D27, "q13", 8, 8),
271
- "q14": (unicorn.arm_const.UC_ARM_REG_Q14, "q14", 0, 16),
272
- "d28": (unicorn.arm_const.UC_ARM_REG_D28, "q14", 0, 8),
273
- "d29": (unicorn.arm_const.UC_ARM_REG_D29, "q14", 8, 8),
274
- "q15": (unicorn.arm_const.UC_ARM_REG_Q15, "q15", 0, 16),
275
- "d30": (unicorn.arm_const.UC_ARM_REG_D30, "q15", 0, 8),
276
- "d31": (unicorn.arm_const.UC_ARM_REG_D31, "q15", 8, 8),
181
+ "fpscr": unicorn.arm_const.UC_ARM_REG_FPSCR,
182
+ "fpexc": unicorn.arm_const.UC_ARM_REG_FPEXC,
183
+ "fpsid": unicorn.arm_const.UC_ARM_REG_FPSID,
184
+ "mvfr0": unicorn.arm_const.UC_ARM_REG_INVALID,
185
+ "mvfr1": unicorn.arm_const.UC_ARM_REG_INVALID,
186
+ "q0": unicorn.arm_const.UC_ARM_REG_Q0,
187
+ "d0": unicorn.arm_const.UC_ARM_REG_D0,
188
+ "s0": unicorn.arm_const.UC_ARM_REG_S0,
189
+ "s1": unicorn.arm_const.UC_ARM_REG_S1,
190
+ "d1": unicorn.arm_const.UC_ARM_REG_D1,
191
+ "s2": unicorn.arm_const.UC_ARM_REG_S2,
192
+ "s3": unicorn.arm_const.UC_ARM_REG_S3,
193
+ "q1": unicorn.arm_const.UC_ARM_REG_Q1,
194
+ "d2": unicorn.arm_const.UC_ARM_REG_D2,
195
+ "s4": unicorn.arm_const.UC_ARM_REG_S4,
196
+ "s5": unicorn.arm_const.UC_ARM_REG_S5,
197
+ "d3": unicorn.arm_const.UC_ARM_REG_D3,
198
+ "s6": unicorn.arm_const.UC_ARM_REG_S6,
199
+ "s7": unicorn.arm_const.UC_ARM_REG_S7,
200
+ "q2": unicorn.arm_const.UC_ARM_REG_Q2,
201
+ "d4": unicorn.arm_const.UC_ARM_REG_D4,
202
+ "s8": unicorn.arm_const.UC_ARM_REG_S8,
203
+ "s9": unicorn.arm_const.UC_ARM_REG_S9,
204
+ "d5": unicorn.arm_const.UC_ARM_REG_D5,
205
+ "s10": unicorn.arm_const.UC_ARM_REG_S10,
206
+ "s11": unicorn.arm_const.UC_ARM_REG_S11,
207
+ "q3": unicorn.arm_const.UC_ARM_REG_Q3,
208
+ "d6": unicorn.arm_const.UC_ARM_REG_D6,
209
+ "s12": unicorn.arm_const.UC_ARM_REG_S12,
210
+ "s13": unicorn.arm_const.UC_ARM_REG_S13,
211
+ "d7": unicorn.arm_const.UC_ARM_REG_D7,
212
+ "s14": unicorn.arm_const.UC_ARM_REG_S14,
213
+ "s15": unicorn.arm_const.UC_ARM_REG_S15,
214
+ "q4": unicorn.arm_const.UC_ARM_REG_Q4,
215
+ "d8": unicorn.arm_const.UC_ARM_REG_D8,
216
+ "s16": unicorn.arm_const.UC_ARM_REG_S16,
217
+ "s17": unicorn.arm_const.UC_ARM_REG_S17,
218
+ "d9": unicorn.arm_const.UC_ARM_REG_D9,
219
+ "s18": unicorn.arm_const.UC_ARM_REG_S18,
220
+ "s19": unicorn.arm_const.UC_ARM_REG_S19,
221
+ "q5": unicorn.arm_const.UC_ARM_REG_Q5,
222
+ "d10": unicorn.arm_const.UC_ARM_REG_D10,
223
+ "s20": unicorn.arm_const.UC_ARM_REG_S20,
224
+ "s21": unicorn.arm_const.UC_ARM_REG_S21,
225
+ "d11": unicorn.arm_const.UC_ARM_REG_D11,
226
+ "s22": unicorn.arm_const.UC_ARM_REG_S22,
227
+ "s23": unicorn.arm_const.UC_ARM_REG_S23,
228
+ "q6": unicorn.arm_const.UC_ARM_REG_Q6,
229
+ "d12": unicorn.arm_const.UC_ARM_REG_D12,
230
+ "s24": unicorn.arm_const.UC_ARM_REG_S24,
231
+ "s25": unicorn.arm_const.UC_ARM_REG_S25,
232
+ "d13": unicorn.arm_const.UC_ARM_REG_D13,
233
+ "s26": unicorn.arm_const.UC_ARM_REG_S26,
234
+ "s27": unicorn.arm_const.UC_ARM_REG_S27,
235
+ "q7": unicorn.arm_const.UC_ARM_REG_Q7,
236
+ "d14": unicorn.arm_const.UC_ARM_REG_D14,
237
+ "s28": unicorn.arm_const.UC_ARM_REG_S28,
238
+ "s29": unicorn.arm_const.UC_ARM_REG_S29,
239
+ "d15": unicorn.arm_const.UC_ARM_REG_D15,
240
+ "s30": unicorn.arm_const.UC_ARM_REG_S30,
241
+ "s31": unicorn.arm_const.UC_ARM_REG_S31,
242
+ "q8": unicorn.arm_const.UC_ARM_REG_Q8,
243
+ "d16": unicorn.arm_const.UC_ARM_REG_D16,
244
+ "d17": unicorn.arm_const.UC_ARM_REG_D17,
245
+ "q9": unicorn.arm_const.UC_ARM_REG_Q9,
246
+ "d18": unicorn.arm_const.UC_ARM_REG_D18,
247
+ "d19": unicorn.arm_const.UC_ARM_REG_D19,
248
+ "q10": unicorn.arm_const.UC_ARM_REG_Q10,
249
+ "d20": unicorn.arm_const.UC_ARM_REG_D20,
250
+ "d21": unicorn.arm_const.UC_ARM_REG_D21,
251
+ "q11": unicorn.arm_const.UC_ARM_REG_Q11,
252
+ "d22": unicorn.arm_const.UC_ARM_REG_D22,
253
+ "d23": unicorn.arm_const.UC_ARM_REG_D23,
254
+ "q12": unicorn.arm_const.UC_ARM_REG_Q12,
255
+ "d24": unicorn.arm_const.UC_ARM_REG_D24,
256
+ "d25": unicorn.arm_const.UC_ARM_REG_D25,
257
+ "q13": unicorn.arm_const.UC_ARM_REG_Q13,
258
+ "d26": unicorn.arm_const.UC_ARM_REG_D26,
259
+ "d27": unicorn.arm_const.UC_ARM_REG_D27,
260
+ "q14": unicorn.arm_const.UC_ARM_REG_Q14,
261
+ "d28": unicorn.arm_const.UC_ARM_REG_D28,
262
+ "d29": unicorn.arm_const.UC_ARM_REG_D29,
263
+ "q15": unicorn.arm_const.UC_ARM_REG_Q15,
264
+ "d30": unicorn.arm_const.UC_ARM_REG_D30,
265
+ "d31": unicorn.arm_const.UC_ARM_REG_D31,
277
266
  }
278
267
  )
279
268
 
@@ -297,7 +286,6 @@ class ARMv6MThumbMachineDef(ARMv6MMachineDef):
297
286
 
298
287
  arch = Architecture.ARM_V6M_THUMB
299
288
  uc_mode = unicorn.UC_MODE_THUMB
300
- cs_mode = capstone.CS_MODE_THUMB
301
289
 
302
290
 
303
291
  class ARMv7MMachineDef(ARMMachineMixinFP, ARMMachineMixinM, ARMMachineDef):