smallworld-re 1.0.2__py3-none-any.whl → 2.0.0__py3-none-any.whl

smallworld/emulators/ghidra/machdefs/riscv.py

@@ -0,0 +1,208 @@
+from ....platforms import Architecture, Byteorder
+from .machdef import GhidraMachineDef
+
+
+class RISCV64MachineDef(GhidraMachineDef):
+    arch = Architecture.RISCV64
+    byteorder = Byteorder.LITTLE
+    language_id = "RISCV:LE:64:default"
+
+    _registers = {
+        # *** General-Purpose Registers ***
+        # x0 is wired to 0, and aliased as "zero"
+        "x0": "zero",
+        "zero": "zero",
+        # x1 acts as the link register
+        # NOTE:ra is the official name; lr might be an angr invention.
+        "x1": "ra",
+        "ra": "ra",
+        # x2 acts as the stack pointer
+        "x2": "sp",
+        "sp": "sp",
+        # x3 acts as the global pointer
+        "x3": "gp",
+        "gp": "gp",
+        # x4 acts as the thread pointer
+        "x4": "tp",
+        "tp": "tp",
+        # x5 is a temporary register
+        "x5": "t0",
+        "t0": "t0",
+        # x6 is a temporary register
+        "x6": "t1",
+        "t1": "t1",
+        # x7 is a temporary register
+        "x7": "t2",
+        "t2": "t2",
+        # x8 is a callee-saved register
+        "x8": "s0",
+        "s0": "s0",
+        # x9 is a callee-saved register
+        "x9": "s1",
+        "s1": "s1",
+        # x10 is argument 0
+        "x10": "a0",
+        "a0": "a0",
+        # x11 is argument 1
+        "x11": "a1",
+        "a1": "a1",
+        # x12 is argument 2
+        "x12": "a2",
+        "a2": "a2",
+        # x13 is argument 3
+        "x13": "a3",
+        "a3": "a3",
+        # x14 is argument 4
+        "x14": "a4",
+        "a4": "a4",
+        # x15 is argument 5
+        "x15": "a5",
+        "a5": "a5",
+        # x16 is argument 6
+        "x16": "a6",
+        "a6": "a6",
+        # x17 is argument 7
+        "x17": "a7",
+        "a7": "a7",
+        # x18 is a callee-saved register
+        "x18": "s2",
+        "s2": "s2",
+        # x19 is a callee-saved register
+        "x19": "s3",
+        "s3": "s3",
+        # x20 is a callee-saved register
+        "x20": "s4",
+        "s4": "s4",
+        # x21 is a callee-saved register
+        "x21": "s5",
+        "s5": "s5",
+        # x22 is a callee-saved register
+        "x22": "s6",
+        "s6": "s6",
+        # x23 is a callee-saved register
+        "x23": "s7",
+        "s7": "s7",
+        # x24 is a callee-saved register
+        "x24": "s8",
+        "s8": "s8",
+        # x25 is a callee-saved register
+        "x25": "s9",
+        "s9": "s9",
+        # x26 is a callee-saved register
+        "x26": "s10",
+        "s10": "s10",
+        # x27 is a callee-saved register
+        "x27": "s11",
+        "s11": "s11",
+        # x28 is a temporary register
+        "x28": "t3",
+        "t3": "t3",
+        # x29 is a temporary register
+        "x29": "t4",
+        "t4": "t4",
+        # x30 is a temporary register
+        "x30": "t5",
+        "t5": "t5",
+        # x31 is a temporary register
+        "x31": "t6",
+        "t6": "t6",
+        # *** Program Counter ***
+        "pc": "pc",
+        # *** Floating-Point Registers ***
+        # f0 is a temporary register
+        "f0": "ft0",
+        "ft0": "ft0",
+        # f1 is a temporary register
+        "f1": "ft1",
+        "ft1": "ft1",
+        # f2 is a temporary register
+        "f2": "ft2",
+        "ft2": "ft2",
+        # f3 is a temporary register
+        "f3": "ft3",
+        "ft3": "ft3",
+        # f4 is a temporary register
+        "f4": "ft4",
+        "ft4": "ft4",
+        # f5 is a temporary register
+        "f5": "ft5",
+        "ft5": "ft5",
+        # f6 is a temporary register
+        "f6": "ft6",
+        "ft6": "ft6",
+        # f7 is a temporary register
+        "f7": "ft7",
+        "ft7": "ft7",
+        # f8 is a callee saved register
+        "f8": "fs0",
+        "fs0": "fs0",
+        # f9 is a callee saved register
+        "f9": "fs1",
+        "fs1": "fs1",
+        # f10 is argument 0
+        "f10": "fa0",
+        "fa0": "fa0",
+        # f11 is argument 1
+        "f11": "fa1",
+        "fa1": "fa1",
+        # f12 is argument 2
+        "f12": "fa2",
+        "fa2": "fa2",
+        # f13 is argument 3
+        "f13": "fa3",
+        "fa3": "fa3",
+        # f14 is argument 4
+        "f14": "fa4",
+        "fa4": "fa4",
+        # f15 is argument 5
+        "f15": "fa5",
+        "fa5": "fa5",
+        # f16 is argument 6
+        "f16": "fa6",
+        "fa6": "fa6",
+        # f7 is argument 7
+        "f17": "fa7",
+        "fa7": "fa7",
+        # f18 is a callee-saved register
+        "f18": "fs2",
+        "fs2": "fs2",
+        # f19 is a callee-saved register
+        "f19": "fs3",
+        "fs3": "fs3",
+        # f20 is a callee-saved register
+        "f20": "fs4",
+        "fs4": "fs4",
+        # f21 is a callee-saved register
+        "f21": "fs5",
+        "fs5": "fs5",
+        # f22 is a callee-saved register
+        "f22": "fs6",
+        "fs6": "fs6",
+        # f23 is a callee-saved register
+        "f23": "fs7",
+        "fs7": "fs7",
+        # f24 is a callee-saved register
+        "f24": "fs8",
+        "fs8": "fs8",
+        # f25 is a callee-saved register
+        "f25": "fs9",
+        "fs9": "fs9",
+        # f26 is a callee-saved register
+        "f26": "fs10",
+        "fs10": "fs10",
+        # f27 is a callee-saved register
+        "f27": "fs11",
+        "fs11": "fs11",
+        # f28 is a temporary register
+        "f28": "ft8",
+        "ft8": "ft8",
+        # f29 is a temporary register
+        "f29": "ft9",
+        "ft9": "ft9",
+        # f30 is a temporary register
+        "f30": "ft10",
+        "ft10": "ft10",
+        # f31 is a temporary register
+        "f31": "ft11",
+        "ft11": "ft11",
+    }

smallworld/emulators/ghidra/machdefs/xtensa.py

@@ -0,0 +1,21 @@
+import typing
+
+from ....platforms import Architecture, Byteorder
+from .machdef import GhidraMachineDef
+
+
+class XTensaMachineDef(GhidraMachineDef):
+    arch = Architecture.XTENSA
+    _registers: typing.Dict[str, typing.Optional[str]] = {}
+    _registers |= {f"a{i}": f"a{i}" for i in range(0, 16)}
+    _registers |= {"pc": "pc", "sar": "sar", "sp": "a1"}
+
+
+class XTensaELMachineDef(XTensaMachineDef):
+    byteorder = Byteorder.LITTLE
+    language_id = "Xtensa:LE:32:default"
+
+
+class XTensaBEMachineDef(XTensaMachineDef):
+    byteorder = Byteorder.BIG
+    language_id = "Xtensa:BE:32:default"

smallworld/emulators/ghidra/typing.py

@@ -0,0 +1,28 @@
+from ..emulator import (
+    Emulator,
+    FunctionHookable,
+    InstructionHookable,
+    MemoryReadHookable,
+    MemoryWriteHookable,
+)
+
+
+class AbstractGhidraEmulator(
+    Emulator,
+    InstructionHookable,
+    FunctionHookable,
+    MemoryReadHookable,
+    MemoryWriteHookable,
+):
+    """Abstract type for GhidraEmulator
+
+    Normal users of SmallWorld shouldn't need to interact with this class.
+
+    This is for the convenience of the factory function in `__init__.py`.
+    The factory needs to annotate its return type with all the
+    interfaces supported by GhidraEmulator,
+    but it can't use GhidraEmulator in its signature
+    because it's not imported until after the first call to the factory.
+    """
+
+    pass

smallworld/emulators/hookable.py

@@ -142,12 +142,19 @@ class QMemoryReadHookable(MemoryReadHookable):
     #    self.memory_read_hooks.pop(address, None)
 
     def is_memory_read_hooked(
-        self, address: int
+        self, address: int, size: int
     ) -> typing.Optional[
         typing.Callable[[Emulator, int, int, bytes], typing.Optional[bytes]]
     ]:
+        end = address + size
+        access_rng = range(address, end)
         for rng in self.memory_read_hooks:
-            if address in rng:
+            if (
+                address in rng
+                or end - 1 in rng
+                or rng.start in access_rng
+                or rng.stop - 1 in access_rng
+            ):
                 return self.memory_read_hooks[rng]
         return None
 
@@ -203,10 +210,17 @@ class QMemoryWriteHookable(MemoryWriteHookable):
     #        )
     #    self.memory_write_hooks.pop(address, None)
     def is_memory_write_hooked(
-        self, address: int
+        self, address: int, size: int
     ) -> typing.Optional[typing.Callable[[Emulator, int, int, bytes], None]]:
+        end = address + size
+        access_rng = range(address, end)
         for rng in self.memory_write_hooks:
-            if address in rng:
+            if (
+                address in rng
+                or end - 1 in rng
+                or rng.start in access_rng
+                or rng.stop - 1 in access_rng
+            ):
                 return self.memory_write_hooks[rng]
         return None
 

smallworld/emulators/panda/machdefs/__init__.py

@@ -7,7 +7,7 @@ from .arm import (  # ARMv6MMachineDef,; ARMv6MThumbMachineDef,
 from .i386 import i386MachineDef
 from .machdef import PandaMachineDef
 from .mips import MIPSBEMachineDef, MIPSELMachineDef
-from .mips64 import MIPS64BEMachineDef  # , MIPS64ELMachineDef
+from .mips64 import MIPS64BEMachineDef, MIPS64ELMachineDef
 from .ppc import PowerPC32MachineDef  # , PowerPC64MachineDef
 
 __all__ = [
@@ -22,7 +22,7 @@ __all__ = [
     "MIPSBEMachineDef",
     "MIPSELMachineDef",
     "MIPS64BEMachineDef",
-    # "MIPS64ELMachineDef",
+    "MIPS64ELMachineDef",
     "PowerPC32MachineDef",
     # "PowerPC64MachineDef",
 ]

smallworld/emulators/panda/machdefs/aarch64.py

@@ -1,5 +1,3 @@
-import capstone
-
 from ....platforms import Architecture, Byteorder
 from .machdef import PandaMachineDef
 
@@ -8,13 +6,8 @@ class AArch64MachineDef(PandaMachineDef):
     arch = Architecture.AARCH64
     byteorder = Byteorder.LITTLE
 
-    cs_arch = capstone.CS_ARCH_ARM64
-    cs_mode = capstone.CS_MODE_ARM | capstone.CS_MODE_LITTLE_ENDIAN
-
     panda_arch = "aarch64"
 
-    # I'm going to define all the ones we are making possible as of now
-    # I need to submit a PR to change to X86 32 bit and to includ eflags
     def __init__(self):
         self._registers = {
             "x0": "x0",
@@ -35,7 +28,6 @@ class AArch64MachineDef(PandaMachineDef):
             "w7": "x7",
             "x8": "xr",
             "w8": "xr",
-            "xr": "xr",
             "x9": "x9",
             "w9": "x9",
             "x10": "x10",
@@ -52,13 +44,10 @@ class AArch64MachineDef(PandaMachineDef):
             "w15": "x15",
             "x16": "ip0",
             "w16": "ip0",
-            "ip0": "ip0",
             "x17": "ip1",
             "w17": "ip1",
-            "ip1": "ip1",
             "x18": "pr",
             "w18": "pr",
-            "pr": "pr",
             "x19": "x19",
             "w19": "x19",
             "x20": "x20",
@@ -88,6 +77,192 @@ class AArch64MachineDef(PandaMachineDef):
             "pc": "pc",
             "sp": "sp",
             "wsp": "sp",
+            "wzr": None,
+            "xzr": None,
+            "fpcr": None,
+            "fpsr": None,
+            "sp_el0": None,
+            "sp_el1": None,
+            "sp_el2": None,
+            "sp_el3": None,
+            "elr_el1": None,
+            "elr_el2": None,
+            "elr_el3": None,
+            "far_el1": None,
+            "far_el2": None,
+            "far_el3": None,
+            "vbar_el1": None,
+            "vbar_el0": None,
+            "vbar_el2": None,
+            "vbar_el3": None,
+            "cpacr_el1": None,
+            "mair_el1": None,
+            "par_el1": None,
+            "ttbr0_el1": None,
+            "ttbr1_el1": None,
+            "tpidr_el0": None,
+            "tpidr_el1": None,
+            "tpidrro_el0": None,
+            "q0": None,
+            "d0": None,
+            "s0": None,
+            "h0": None,
+            "b0": None,
+            "q1": None,
+            "d1": None,
+            "s1": None,
+            "h1": None,
+            "b1": None,
+            "q2": None,
+            "d2": None,
+            "s2": None,
+            "h2": None,
+            "b2": None,
+            "q3": None,
+            "d3": None,
+            "s3": None,
+            "h3": None,
+            "b3": None,
+            "q4": None,
+            "d4": None,
+            "s4": None,
+            "h4": None,
+            "b4": None,
+            "q5": None,
+            "d5": None,
+            "s5": None,
+            "h5": None,
+            "b5": None,
+            "q6": None,
+            "d6": None,
+            "s6": None,
+            "h6": None,
+            "b6": None,
+            "q7": None,
+            "d7": None,
+            "s7": None,
+            "h7": None,
+            "b7": None,
+            "q8": None,
+            "d8": None,
+            "s8": None,
+            "h8": None,
+            "b8": None,
+            "q9": None,
+            "d9": None,
+            "s9": None,
+            "h9": None,
+            "b9": None,
+            "q10": None,
+            "d10": None,
+            "s10": None,
+            "h10": None,
+            "b10": None,
+            "q11": None,
+            "d11": None,
+            "s11": None,
+            "h11": None,
+            "b11": None,
+            "q12": None,
+            "d12": None,
+            "s12": None,
+            "h12": None,
+            "b12": None,
+            "q13": None,
+            "d13": None,
+            "s13": None,
+            "h13": None,
+            "b13": None,
+            "q14": None,
+            "d14": None,
+            "s14": None,
+            "h14": None,
+            "b14": None,
+            "q15": None,
+            "d15": None,
+            "s15": None,
+            "h15": None,
+            "b15": None,
+            "q16": None,
+            "d16": None,
+            "s16": None,
+            "h16": None,
+            "b16": None,
+            "q17": None,
+            "d17": None,
+            "s17": None,
+            "h17": None,
+            "b17": None,
+            "q18": None,
+            "d18": None,
+            "s18": None,
+            "h18": None,
+            "b18": None,
+            "q19": None,
+            "d19": None,
+            "s19": None,
+            "h19": None,
+            "b19": None,
+            "q20": None,
+            "d20": None,
+            "s20": None,
+            "h20": None,
+            "b20": None,
+            "q21": None,
+            "d21": None,
+            "s21": None,
+            "h21": None,
+            "b21": None,
+            "q22": None,
+            "d22": None,
+            "s22": None,
+            "h22": None,
+            "b22": None,
+            "q23": None,
+            "d23": None,
+            "s23": None,
+            "h23": None,
+            "b23": None,
+            "q24": None,
+            "d24": None,
+            "s24": None,
+            "h24": None,
+            "b24": None,
+            "q25": None,
+            "d25": None,
+            "s25": None,
+            "h25": None,
+            "b25": None,
+            "q26": None,
+            "d26": None,
+            "s26": None,
+            "h26": None,
+            "b26": None,
+            "q27": None,
+            "d27": None,
+            "s27": None,
+            "h27": None,
+            "b27": None,
+            "q28": None,
+            "d28": None,
+            "s28": None,
+            "h28": None,
+            "b28": None,
+            "q29": None,
+            "d29": None,
+            "s29": None,
+            "h29": None,
+            "b29": None,
+            "q30": None,
+            "d30": None,
+            "s30": None,
+            "h30": None,
+            "b30": None,
+            "q31": None,
+            "d31": None,
+            "s31": None,
+            "h31": None,
+            "b31": None,
         }
 
         self._registers = {i: j for i, j in self._registers.items()}

smallworld/emulators/panda/machdefs/amd64.py

@@ -1,5 +1,3 @@
-import capstone
-
 from ....platforms import Architecture, Byteorder
 from .machdef import PandaMachineDef
 
@@ -10,11 +8,8 @@ class AMD64MachineDef(PandaMachineDef):
 
     panda_arch = "x86_64"
 
-    cs_arch = capstone.CS_ARCH_X86
-    cs_mode = capstone.CS_MODE_64
-
     # I'm going to define all the ones we are making possible as of now
-    # I need to submit a PR to change to X86 32 bit and to includ eflags
+    # I need to submit a PR to change to X86 32 bit and to include eflags
     _registers_64 = {
         "rax",
         "rbx",
@@ -34,12 +29,83 @@ class AMD64MachineDef(PandaMachineDef):
         "r14",
         "r15",
     }
-    _registers_general = {"eax", "ebx", "ecx", "edx", "esi", "edi", "esp", "ebp", "eip"}
-    _registers_short = {"ax", "bx", "cx", "dx", "si", "di", "sp", "bp"}
-    _registers_byte = {"al", "bl", "cl", "dl", "ah", "bh", "ch", "dh"}
+    _registers_general = {
+        "eax",
+        "ebx",
+        "ecx",
+        "edx",
+        "esi",
+        "edi",
+        "esp",
+        "ebp",
+        "eip",
+        "r8d",
+        "r9d",
+        "r10d",
+        "r11d",
+        "r12d",
+        "r13d",
+        "r14d",
+        "r15d",
+    }
+    _registers_short = {
+        "ax",
+        "bx",
+        "cx",
+        "dx",
+        "si",
+        "di",
+        "sp",
+        "bp",
+        "r8w",
+        "r9w",
+        "r10w",
+        "r11w",
+        "r12w",
+        "r13w",
+        "r14w",
+        "r15w",
+    }
+    _registers_byte = {
+        "al",
+        "bl",
+        "cl",
+        "dl",
+        "r8b",
+        "r9b",
+        "r10b",
+        "r11b",
+        "r12b",
+        "r13b",
+        "r14b",
+        "r15b",
+        "ah",
+        "bh",
+        "ch",
+        "dh",
+    }
+    _registers_flags = {"rflags", "eflags", "flags"}
     _registers_seg = {"es", "cs", "ss", "ds", "fs", "gs"}
     _registers_control = {"cr0", "cr1", "cr2", "cr3", "cr4"}
+    _registers_debug = {f"dr{i}" for i in range(0, 16)} - {"dr4", "dr5"}
     _registers_mmr = {"gdtr": "gdt", "idtr": "idt", "tr": "tr", "ldtr": "ldt"}
+    _registers_x87 = {
+        "fpr0",
+        "fpr1",
+        "fpr2",
+        "fpr3",
+        "fpr4",
+        "fpr5",
+        "fpr6",
+        "fpr7",
+        "fctrl",
+        "fstat",
+        "ftag",
+        "fip",
+        "fdp",
+        "fop",
+    }
+    _registers_mmx = {"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"}
     _registers_xmm = {
         "xmm0",
         "xmm1",
@@ -58,14 +124,40 @@ class AMD64MachineDef(PandaMachineDef):
         "xmm14",
         "xmm15",
     }
-    _register_pc = {"pc": "rip"}
+    _registers_ymm = {
+        "ymm0",
+        "ymm1",
+        "ymm2",
+        "ymm3",
+        "ymm4",
+        "ymm5",
+        "ymm6",
+        "ymm7",
+        "ymm8",
+        "ymm9",
+        "ymm10",
+        "ymm11",
+        "ymm12",
+        "ymm13",
+        "ymm14",
+        "ymm15",
+    }
+    _registers_pc = {"pc": "rip", "eip": "eip", "ip": None}
+    _registers_absent = {"dil", "sil", "spl", "bpl", "cr8"}
 
     _registers = {}
     _registers = _registers | {i: i for i in _registers_64}
     _registers = _registers | {i: i for i in _registers_general}
+    _registers = _registers | {i: i for i in _registers_short}
     _registers = _registers | {i: i for i in _registers_byte}
+    _registers = _registers | {i: None for i in _registers_flags}
     _registers = _registers | {i: i for i in _registers_seg}
     _registers = _registers | {i: i for i in _registers_control}
+    _registers = _registers | {i: None for i in _registers_debug}
     _registers = _registers | {i: j for i, j in _registers_mmr.items()}
+    _registers = _registers | {i: None for i in _registers_x87}
+    _registers = _registers | {i: None for i in _registers_mmx}
     _registers = _registers | {i: i for i in _registers_xmm}
-    _registers = _registers | {i: j for i, j in _register_pc.items()}
+    _registers = _registers | {i: None for i in _registers_ymm}
+    _registers = _registers | {i: j for i, j in _registers_pc.items()}
+    _registers = _registers | {i: None for i in _registers_absent}