smallworld-re 1.0.2__py3-none-any.whl → 2.0.0__py3-none-any.whl

smallworld/emulators/panda/machdefs/arm.py

@@ -1,13 +1,8 @@
-import capstone
-
 from ....platforms import Architecture, Byteorder
 from .machdef import PandaMachineDef
 
 
 class ARMMachineDef(PandaMachineDef):
-    cs_arch = capstone.CS_ARCH_ARM
-    cs_mode = capstone.CS_MODE_ARM | capstone.CS_MODE_LITTLE_ENDIAN
-
     panda_arch = "arm"
 
     # I'm going to define all the ones we are making possible as of now
@@ -29,11 +24,16 @@ class ARMMachineDef(PandaMachineDef):
             "r12",
             "sp",
             "lr",
-            "ip",
+            "pc",
         }
 
         self._registers = {i: i for i in self._registers}
-        self._registers = self._registers | {"pc": "ip"}
+        self._registers = self._registers | {
+            "sb": "r9",
+            "sl": "r10",
+            "fp": "r11",
+            "ip": "r12",
+        }
 
 
 class ARMMachineMixinM:
@@ -43,15 +43,76 @@ class ARMMachineMixinM:
         super().__init__()
         self._registers_m = {
             # NOTE: None of the expected privileged registers exist
-            # "psr",
-            # "primask",
-            # "basepri",
-            # "faultmask",
-            # "control",
-            # "msp",
-            # "psp",
+            "psr",
+            "primask",
+            "basepri",
+            "faultmask",
+            "control",
+            "msp",
+            "psp",
         }
-        self._registers = self._registers | {i: i for i in self._registers_m}
+        self._registers = self._registers | {i: None for i in self._registers_m}
+
+
+class ARMMachineMixinFP:
+    def __init__(self):
+        super().__init__()
+        self._registers_fp = {
+            "fpscr",
+            "fpexc",
+            "fpsid",
+            "mvfr0",
+            "mvfr1",
+            "d0",
+            "s0",
+            "s1",
+            "d1",
+            "s2",
+            "s3",
+            "d2",
+            "s4",
+            "s5",
+            "d3",
+            "s6",
+            "s7",
+            "d4",
+            "s8",
+            "s9",
+            "d5",
+            "s10",
+            "s11",
+            "d6",
+            "s12",
+            "s13",
+            "d7",
+            "s14",
+            "s15",
+            "d8",
+            "s16",
+            "s17",
+            "d9",
+            "s18",
+            "s19",
+            "d10",
+            "s20",
+            "s21",
+            "d11",
+            "s22",
+            "s23",
+            "d12",
+            "s24",
+            "s25",
+            "d13",
+            "s26",
+            "s27",
+            "d14",
+            "s28",
+            "s29",
+            "d15",
+            "s30",
+            "s31",
+        }
+        self._registers = self._registers | {i: None for i in self._registers_fp}
 
 
 class ARMMachineMixinA:
@@ -62,13 +123,148 @@ class ARMMachineMixinA:
         # TODO: QEMU doesn't quite support what I expect.
         # I expected to see cpsr and spsr.
         # I either got the CPU model wrong, or something else is weird.
+        # (I strongly suspect Panda exposes the bitmasked aliases of cpsr)
         self._registers_a = {
-            "psr",
+            "cpsr": None,
+            "spsr": None,
+            "sp_usr": None,
+            "lr_usr": None,
+            "r8_usr": None,
+            "r9_usr": None,
+            "r10_usr": None,
+            "r11_usr": None,
+            "r12_usr": None,
+            "sp_hyp": None,
+            "spsr_hyp": None,
+            "elr_hyp": None,
+            "sp_svc": None,
+            "lr_svc": None,
+            "spsr_svc": None,
+            "sp_abt": None,
+            "lr_abt": None,
+            "spsr_abt": None,
+            "sp_und": None,
+            "lr_und": None,
+            "spsr_und": None,
+            "sp_mon": None,
+            "lr_mon": None,
+            "spsr_mon": None,
+            "sp_irq": None,
+            "lr_irq": None,
+            "spsr_irq": None,
+            "sp_fiq": None,
+            "lr_fiq": None,
+            "spsr_fiq": None,
+            "r8_fiq": None,
+            "r9_fiq": None,
+            "r10_fiq": None,
+            "r11_fiq": None,
+            "r12_fiq": None,
+        }
+        self._registers = self._registers | {k: v for k, v in self._registers_a.items()}
+
+
+class ARMMachineMixinVFP:
+    def __init__(self):
+        super().__init__()
+        self._registers_vfp = {
+            # *** Floating-point Control Registers ***
+            # Floating-point Status and Control Register
+            "fpscr",
+            # Floating-point Exception Control Register
+            "fpexc",
+            # Floating-point System ID Register
+            "fpsid",
+            # Media and VFP Feature Register 0
+            "mvfr0",
+            # Media and VFP Feature Register 1
+            "mvfr1",
+            # *** Floating-point Registers ****
+            "q0",
+            "d0",
+            "s0",
+            "s1",
+            "d1",
+            "s2",
+            "s3",
+            "q1",
+            "d2",
+            "s4",
+            "s5",
+            "d3",
+            "s6",
+            "s7",
+            "q2",
+            "d4",
+            "s8",
+            "s9",
+            "d5",
+            "s10",
+            "s11",
+            "q3",
+            "d6",
+            "s12",
+            "s13",
+            "d7",
+            "s14",
+            "s15",
+            "q4",
+            "d8",
+            "s16",
+            "s17",
+            "d9",
+            "s18",
+            "s19",
+            "q5",
+            "d10",
+            "s20",
+            "s21",
+            "d11",
+            "s22",
+            "s23",
+            "q6",
+            "d12",
+            "s24",
+            "s25",
+            "d13",
+            "s26",
+            "s27",
+            "q7",
+            "d14",
+            "s28",
+            "s29",
+            "d15",
+            "s30",
+            "s31",
+            "q8",
+            "d16",
+            "d17",
+            "q9",
+            "d18",
+            "d19",
+            "q10",
+            "d20",
+            "d21",
+            "q11",
+            "d22",
+            "d23",
+            "q12",
+            "d24",
+            "d25",
+            "q13",
+            "d26",
+            "d27",
+            "q14",
+            "d28",
+            "d29",
+            "q15",
+            "d30",
+            "d31",
         }
-        self._registers = self._registers | {i: i for i in self._registers_a}
+        self._registers = self._registers | {i: None for i in self._registers_vfp}
 
 
-class ARMv5TMachineDef(ARMMachineDef):
+class ARMv5TMachineDef(ARMMachineMixinM, ARMMachineDef):
     arch = Architecture.ARM_V5T
     byteorder = Byteorder.LITTLE
     cpu = "pxa255"
@@ -77,13 +273,13 @@ class ARMv5TMachineDef(ARMMachineDef):
 # TODO: Something's very weird with Panda's Arm 7 models.
 # cortex-a9 should be an A-series, but it looks more like an M-series.
 # cortex-m4 looks like an M-series, but aborts; I suspect we're missing configuration.
-class ARMv7AMachineDef(ARMMachineMixinA, ARMMachineDef):
+class ARMv7AMachineDef(ARMMachineMixinVFP, ARMMachineMixinA, ARMMachineDef):
     arch = Architecture.ARM_V7A
     byteorder = Byteorder.LITTLE
     cpu = "cortex-a9"
 
 
-class ARMv7MMachineDef(ARMMachineMixinM, ARMMachineDef):
+class ARMv7MMachineDef(ARMMachineMixinFP, ARMMachineMixinM, ARMMachineDef):
     arch = Architecture.ARM_V7M
     byteorder = Byteorder.LITTLE
     cpu = "cortex-m4"

smallworld/emulators/panda/machdefs/i386.py

@@ -1,5 +1,3 @@
-import capstone
-
 from ....platforms import Architecture, Byteorder
 from .machdef import PandaMachineDef
 
@@ -10,26 +8,51 @@ class i386MachineDef(PandaMachineDef):
 
     panda_arch = "i386"
 
-    cs_arch = capstone.CS_ARCH_X86
-    cs_mode = capstone.CS_MODE_32
-
     # I'm going to define all the ones we are making possible as of now
     # I need to submit a PR to change to X86 32 bit and to includ eflags
     _registers_general = {"eax", "ebx", "ecx", "edx", "esi", "edi", "esp", "ebp", "eip"}
     _registers_short = {"ax", "bx", "cx", "dx", "si", "di", "sp", "bp"}
     _registers_byte = {"al", "bl", "cl", "dl", "ah", "bh", "ch", "dh"}
+    _registers_flags = {"eflags", "flags"}
     _registers_seg = {"es", "cs", "ss", "ds", "fs", "gs"}
     _registers_control = {"cr0", "cr1", "cr2", "cr3", "cr4"}
+    _registers_debug = {"dr0", "dr1", "dr2", "dr3", "dr6", "dr7"}
     _registers_mmr = {"gdtr": "gdt", "idtr": "idt", "tr": "tr", "ldtr": "ldt"}
-    _register_pc = {"pc": "eip"}
+    _registers_x87 = {
+        "fpr0",
+        "fpr1",
+        "fpr2",
+        "fpr3",
+        "fpr4",
+        "fpr5",
+        "fpr6",
+        "fpr7",
+        "fctrl",
+        "fstat",
+        "ftag",
+        "fip",
+        "fdp",
+        "fop",
+    }
+    _registers_mmx = {"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"}
+    _registers_xmm = {"xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7"}
+    _registers_pc = {"pc": "eip", "ip": None}
+    _registers_absent = {"dil", "sil", "spl", "bpl", "cr8"}
 
     _registers = {}
     _registers = _registers | {i: i for i in _registers_general}
+    _registers = _registers | {i: i for i in _registers_short}
     _registers = _registers | {i: i for i in _registers_byte}
+    _registers = _registers | {i: None for i in _registers_flags}
     _registers = _registers | {i: i for i in _registers_seg}
     _registers = _registers | {i: i for i in _registers_control}
+    _registers = _registers | {i: None for i in _registers_debug}
     _registers = _registers | {i: j for i, j in _registers_mmr.items()}
-    _registers = _registers | {i: j for i, j in _register_pc.items()}
+    _registers = _registers | {i: None for i in _registers_x87}
+    _registers = _registers | {i: None for i in _registers_mmx}
+    _registers = _registers | {i: None for i in _registers_xmm}
+    _registers = _registers | {i: j for i, j in _registers_pc.items()}
+    _registers = _registers | {i: None for i in _registers_absent}
     # _registers = (
     #    _registers_general | _registers_byte | _registers_seg | _registers_control
     # )

smallworld/emulators/panda/machdefs/machdef.py

@@ -1,7 +1,7 @@
 import abc
 import typing
 
-from .... import platforms, utils
+from .... import exceptions, platforms, utils
 
 
 class PandaMachineDef(metaclass=abc.ABCMeta):
@@ -25,23 +25,16 @@ class PandaMachineDef(metaclass=abc.ABCMeta):
         """The panda architecture to use"""
         raise NotImplementedError("This is an abstract method.")
 
-    @property
-    @abc.abstractmethod
-    def cs_arch(self) -> int:
-        """The capstone architecture to use"""
-        raise NotImplementedError("This is an abstract method.")
-
-    @property
-    @abc.abstractmethod
-    def cs_mode(self) -> int:
-        """The capstone mode to use"""
-        raise NotImplementedError("This is an abstract method.")
-
-    _registers: typing.Dict[str, str] = {}
+    _registers: typing.Dict[str, typing.Optional[str]] = {}
 
     def panda_reg(self, name: str) -> str:
         if name in self._registers:
-            return self._registers[name]
+            res = self._registers[name]
+            if res is None:
+                raise exceptions.UnsupportedRegisterError(
+                    f"Register {name} not recognized by Panda for {self.arch}:{self.byteorder}"
+                )
+            return res
         else:
             raise ValueError(
                 f"Unknown register for {self.arch}:{self.byteorder}: {name}"
@@ -54,7 +47,7 @@ class PandaMachineDef(metaclass=abc.ABCMeta):
         for this arch/mode/byteorder, or return 0,
         which always indicates an invalid register
         """
-        if name in self._registers:
+        if name in self._registers and self._registers[name] is not None:
             return True
         else:
             return False

smallworld/emulators/panda/machdefs/mips.py

@@ -1,12 +1,9 @@
-import capstone
-
 from ....platforms import Architecture, Byteorder
 from .machdef import PandaMachineDef
 
 
 class MIPSMachineDef(PandaMachineDef):
     arch = Architecture.MIPS32
-    cs_arch = capstone.CS_ARCH_MIPS
     cpu = "M14K"
 
     # I'm going to define all the ones we are making possible as of now
@@ -79,16 +76,63 @@ class MIPSMachineDef(PandaMachineDef):
             "ra": "ra",
             "31": "ra",
             "pc": "pc",
+            "f0": None,
+            "f1": None,
+            "f2": None,
+            "f3": None,
+            "f4": None,
+            "f5": None,
+            "f6": None,
+            "f7": None,
+            "f8": None,
+            "f9": None,
+            "f10": None,
+            "f11": None,
+            "f12": None,
+            "f13": None,
+            "f14": None,
+            "f15": None,
+            "f16": None,
+            "f17": None,
+            "f18": None,
+            "f19": None,
+            "f20": None,
+            "f21": None,
+            "f22": None,
+            "f23": None,
+            "f24": None,
+            "f25": None,
+            "f26": None,
+            "f27": None,
+            "f28": None,
+            "f29": None,
+            "f30": None,
+            "f31": None,
+            "fir": None,
+            "fcsr": None,
+            "fexr": None,
+            "fenr": None,
+            "fccr": None,
+            "ac0": None,
+            "lo0": None,
+            "hi0": None,
+            "ac1": None,
+            "lo1": None,
+            "hi1": None,
+            "ac2": None,
+            "lo2": None,
+            "hi2": None,
+            "ac3": None,
+            "lo3": None,
+            "hi3": None,
         }
 
 
 class MIPSELMachineDef(MIPSMachineDef):
     panda_arch = "mipsel"
     byteorder = Byteorder.LITTLE
-    cs_mode = capstone.CS_MODE_MIPS32 | capstone.CS_MODE_LITTLE_ENDIAN
 
 
 class MIPSBEMachineDef(MIPSMachineDef):
     panda_arch = "mips"
     byteorder = Byteorder.BIG
-    cs_mode = capstone.CS_MODE_MIPS32 | capstone.CS_MODE_BIG_ENDIAN

smallworld/emulators/panda/machdefs/mips64.py

@@ -1,15 +1,11 @@
-import capstone
-
 from ....platforms import Architecture, Byteorder
 from .machdef import PandaMachineDef
 
 
 class MIPS64MachineDef(PandaMachineDef):
     arch = Architecture.MIPS64
-    cs_arch = capstone.CS_ARCH_MIPS
 
     # We don't need this
-    panda_arch = "mips64"
 
     # I'm going to define all the ones we are making possible as of now
     # I need to submit a PR to change to X86 32 bit and to includ eflags
@@ -81,11 +77,67 @@ class MIPS64MachineDef(PandaMachineDef):
             "ra": "ra",
             "31": "ra",
             "pc": "pc",
+            "f0": None,
+            "f1": None,
+            "f2": None,
+            "f3": None,
+            "f4": None,
+            "f5": None,
+            "f6": None,
+            "f7": None,
+            "f8": None,
+            "f9": None,
+            "f10": None,
+            "f11": None,
+            "f12": None,
+            "f13": None,
+            "f14": None,
+            "f15": None,
+            "f16": None,
+            "f17": None,
+            "f18": None,
+            "f19": None,
+            "f20": None,
+            "f21": None,
+            "f22": None,
+            "f23": None,
+            "f24": None,
+            "f25": None,
+            "f26": None,
+            "f27": None,
+            "f28": None,
+            "f29": None,
+            "f30": None,
+            "f31": None,
+            "fir": None,
+            "fcsr": None,
+            "fexr": None,
+            "fenr": None,
+            "fccr": None,
+            "ac0": None,
+            "lo0": None,
+            "hi0": None,
+            "ac1": None,
+            "lo1": None,
+            "hi1": None,
+            "ac2": None,
+            "lo2": None,
+            "hi2": None,
+            "ac3": None,
+            "lo3": None,
+            "hi3": None,
         }
 
 
 class MIPS64BEMachineDef(MIPS64MachineDef):
     byteorder = Byteorder.BIG
+    panda_arch = "mips64"
+    machine = "malta"
+    cpu = "MIPS64R2-generic"
+
+
+class MIPS64ELMachineDef(MIPS64MachineDef):
+    byteorder = Byteorder.LITTLE
+    panda_arch = "mips64el"
     machine = "malta"
     cpu = "MIPS64R2-generic"
-    cs_mode = capstone.CS_MODE_MIPS64 | capstone.CS_MODE_BIG_ENDIAN

smallworld/emulators/panda/machdefs/ppc.py

@@ -1,5 +1,3 @@
-import capstone
-
 from ....platforms import Architecture, Byteorder
 from .machdef import PandaMachineDef
 
@@ -7,9 +5,6 @@ from .machdef import PandaMachineDef
 class PowerPCMachineDef(PandaMachineDef):
     byteorder = Byteorder.BIG
 
-    cs_arch = capstone.CS_ARCH_PPC
-    cs_mode = capstone.CS_MODE_32 | capstone.CS_MODE_BIG_ENDIAN
-
     panda_arch = "ppc"
 
     # I'm going to define all the ones we are making possible as of now
@@ -61,19 +56,49 @@ class PowerPCMachineDef(PandaMachineDef):
     }
     _registers_mapping = {
         "r1": "sp",
+        "bp": "r31",
+    }
+    _registers_unsupported = {
+        "f0",
+        "f1",
+        "f2",
+        "f3",
+        "f4",
+        "f5",
+        "f6",
+        "f7",
+        "f8",
+        "f9",
+        "f10",
+        "f11",
+        "f12",
+        "f13",
+        "f14",
+        "f15",
+        "f16",
+        "f17",
+        "f18",
+        "f19",
+        "f20",
+        "f21",
+        "f22",
+        "f23",
+        "f24",
+        "f25",
+        "f26",
+        "f27",
+        "f28",
+        "f29",
+        "f30",
+        "f31",
+        "xer",
+        "fpscr",
     }
     _registers = {i: j for i, j in _registers_mapping.items()}
     _registers = _registers | {i: i for i in _registers_identity}
+    _registers = _registers | {i: None for i in _registers_unsupported}
 
 
 class PowerPC32MachineDef(PowerPCMachineDef):
     arch = Architecture.POWERPC32
-    cs_mode = capstone.CS_MODE_32 | capstone.CS_MODE_BIG_ENDIAN
     cpu = "ppc32"
-
-
-# TODO: Do we have a panda PPC 64 bit cpu?
-class PowerPC64MachineDef(PowerPCMachineDef):
-    arch = Architecture.POWERPC64
-    cs_mode = capstone.CS_MODE_64 | capstone.CS_MODE_BIG_ENDIAN
-    # cpu = "970"