siliconcompiler 0.28.9__py3-none-any.whl → 0.29.0__py3-none-any.whl

siliconcompiler/tools/openroad/antenna_repair.py

@@ -0,0 +1,78 @@
+from siliconcompiler import NodeStatus
+
+from siliconcompiler.tools._common import get_tool_task, has_pre_post_script
+
+from siliconcompiler.tools.openroad._apr import setup as apr_setup
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import \
+    define_ord_params, define_sta_params, define_sdc_params, \
+    define_grt_params, define_dpl_params, define_ant_params
+from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
+from siliconcompiler.tools.openroad._apr import extract_metrics
+
+
+def setup(chip):
+    '''
+    Perform antenna repair
+    '''
+
+    # Generic apr tool setup.
+    apr_setup(chip)
+
+    # Task setup
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'script', 'apr/sc_antenna_repair.tcl',
+             step=step, index=index)
+
+    # Setup task IO
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    # set default values for openroad
+    define_ord_params(chip)
+    define_sta_params(chip)
+    define_sdc_params(chip)
+    define_ant_params(chip)
+    define_grt_params(chip)
+    define_dpl_params(chip)
+
+    set_reports(chip, [
+        'setup',
+        'hold',
+        'unconstrained',
+        'clock_skew',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'optimization_placement',
+        'clock_placement',
+        'clock_trees'
+    ])
+
+
+def pre_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    if not has_pre_post_script(chip) and \
+            chip.get('tool', tool, 'task', task, 'var', 'ant_check',
+                     step=step, index=index)[0] == 'false':
+        chip.set('record', 'status', NodeStatus.SKIPPED, step=step, index=index)
+        chip.logger.warning(f'{step}{index} will be skipped since antenna repair is disabled.')
+        return
+
+    define_ord_files(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    extract_metrics(chip)

siliconcompiler/tools/openroad/clock_tree_synthesis.py

@@ -0,0 +1,64 @@
+from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools.openroad._apr import setup as apr_setup
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import \
+    define_ord_params, define_sta_params, define_sdc_params, \
+    define_cts_params, define_dpl_params, define_rsz_params
+from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
+from siliconcompiler.tools.openroad._apr import extract_metrics
+
+
+def setup(chip):
+    '''
+    Perform clock tree synthesis
+    '''
+
+    # Generic apr tool setup.
+    apr_setup(chip)
+
+    # Task setup
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'script', 'apr/sc_clock_tree_synthesis.tcl',
+             step=step, index=index)
+
+    # Setup task IO
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    # set default values for openroad
+    define_ord_params(chip)
+    define_sta_params(chip)
+    define_sdc_params(chip)
+    define_cts_params(chip)
+    define_dpl_params(chip)
+    define_rsz_params(chip)
+
+    set_reports(chip, [
+        'setup',
+        'hold',
+        'unconstrained',
+        'clock_skew',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'optimization_placement',
+        'clock_placement',
+        'clock_trees'
+    ])
+
+
+def pre_process(chip):
+    define_ord_files(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    extract_metrics(chip)

siliconcompiler/tools/openroad/detailed_placement.py

@@ -0,0 +1,59 @@
+from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools.openroad._apr import setup as apr_setup
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import \
+    define_ord_params, define_sta_params, define_sdc_params, \
+    define_dpl_params, define_dpo_params
+from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
+from siliconcompiler.tools.openroad._apr import extract_metrics
+
+
+def setup(chip):
+    '''
+    Perform detailed placement
+    '''
+
+    # Generic apr tool setup.
+    apr_setup(chip)
+
+    # Task setup
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'script', 'apr/sc_detailed_placement.tcl',
+             step=step, index=index)
+
+    # Setup task IO
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    # set default values for openroad
+    define_ord_params(chip)
+    define_sta_params(chip)
+    define_sdc_params(chip)
+    define_dpl_params(chip)
+    define_dpo_params(chip)
+
+    set_reports(chip, [
+        'setup',
+        'unconstrained',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'optimization_placement'
+    ])
+
+
+def pre_process(chip):
+    define_ord_files(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    extract_metrics(chip)

siliconcompiler/tools/openroad/detailed_route.py

@@ -0,0 +1,62 @@
+from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools.openroad._apr import setup as apr_setup
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import \
+    define_ord_params, define_sta_params, define_sdc_params, \
+    define_drt_params
+from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
+from siliconcompiler.tools.openroad._apr import extract_metrics
+
+
+def setup(chip):
+    '''
+    Perform detailed routing
+    '''
+
+    # Generic apr tool setup.
+    apr_setup(chip)
+
+    # Task setup
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'script', 'apr/sc_detailed_route.tcl',
+             step=step, index=index)
+
+    # Setup task IO
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    # set default values for openroad
+    define_ord_params(chip)
+    define_sta_params(chip)
+    define_sdc_params(chip)
+    define_drt_params(chip)
+
+    set_reports(chip, [
+        'setup',
+        'hold',
+        'unconstrained',
+        'clock_skew',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'optimization_placement',
+        'clock_placement',
+        'clock_trees'
+    ])
+
+
+def pre_process(chip):
+    define_ord_files(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    extract_metrics(chip)

siliconcompiler/tools/openroad/endcap_tapcell_insertion.py

@@ -0,0 +1,52 @@
+from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools.openroad._apr import setup as apr_setup
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import \
+    define_ord_params, define_sta_params, define_sdc_params, \
+    define_tapcell_params, define_tiecell_params
+from siliconcompiler.tools.openroad._apr import build_pex_corners, \
+    define_ord_files, define_tapcell_files
+from siliconcompiler.tools.openroad._apr import extract_metrics
+
+
+def setup(chip):
+    '''
+    Perform endcap and tap cell insertion
+    '''
+
+    # Generic apr tool setup.
+    apr_setup(chip)
+
+    # Task setup
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'script', 'apr/sc_endcap_tapcell_insertion.tcl',
+             step=step, index=index)
+
+    # Setup task IO
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    # set default values for openroad
+    define_ord_params(chip)
+    define_sta_params(chip)
+    define_sdc_params(chip)
+    define_tapcell_params(chip)
+    define_tiecell_params(chip)
+
+    set_reports(chip, [
+        # Images
+        'placement_density'
+    ])
+
+
+def pre_process(chip):
+    define_ord_files(chip)
+    define_tapcell_files(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    extract_metrics(chip)

siliconcompiler/tools/openroad/fillercell_insertion.py

@@ -0,0 +1,58 @@
+from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools.openroad._apr import setup as apr_setup
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import \
+    define_ord_params, define_sta_params, define_sdc_params, \
+    define_dpl_params
+from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
+from siliconcompiler.tools.openroad._apr import extract_metrics
+
+
+def setup(chip):
+    '''
+    Perform filler cell insertion
+    '''
+
+    # Generic apr tool setup.
+    apr_setup(chip)
+
+    # Task setup
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'script', 'apr/sc_fillercell_insertion.tcl',
+             step=step, index=index)
+
+    # Setup task IO
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    # set default values for openroad
+    define_ord_params(chip)
+    define_sta_params(chip)
+    define_sdc_params(chip)
+    define_dpl_params(chip)
+
+    set_reports(chip, [
+        'setup',
+        'hold',
+        'unconstrained',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density'
+    ])
+
+
+def pre_process(chip):
+    define_ord_files(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    extract_metrics(chip)

siliconcompiler/tools/openroad/{dfm.py → fillmetal_insertion.py}

@@ -1,26 +1,44 @@
+from siliconcompiler import NodeStatus
 
-from siliconcompiler.tools.openroad.openroad import setup as setup_tool
-from siliconcompiler.tools.openroad.openroad import build_pex_corners
-from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
-from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
-from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
-from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools._common import get_tool_task, has_pre_post_script
 from siliconcompiler.tools._common.asic import get_mainlib
-from siliconcompiler import NodeStatus
+
+from siliconcompiler.tools.openroad._apr import setup as apr_setup
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import \
+    define_ord_params, define_sta_params, define_sdc_params, \
+    define_fin_params
+from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
+from siliconcompiler.tools.openroad._apr import extract_metrics
 
 
 def setup(chip):
     '''
-    Design for manufacturing step will insert fill if specified
+    Perform fill metal insertion
     '''
 
-    # Generic tool setup.
-    setup_tool(chip)
+    # Generic apr tool setup.
+    apr_setup(chip)
 
+    # Task setup
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'script', 'apr/sc_fillmetal_insertion.tcl',
+             step=step, index=index)
+
+    # Setup task IO
     set_pnr_inputs(chip)
     set_pnr_outputs(chip)
 
-    _set_reports(chip, [
+    # set default values for openroad
+    define_ord_params(chip)
+    define_sta_params(chip)
+    define_sdc_params(chip)
+    define_fin_params(chip)
+
+    set_reports(chip, [
         'setup',
         'hold',
         'unconstrained',
@@ -33,9 +51,9 @@ def setup(chip):
         'placement_density',
         'routing_congestion',
         'power_density',
+        'optimization_placement',
         'clock_placement',
-        'clock_trees',
-        'optimization_placement'
+        'clock_trees'
     ])
 
 
@@ -43,10 +61,7 @@ def pre_process(chip):
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
-    if not chip.find_files('tool', tool, 'task', task, 'prescript',
-                           step=step, index=index) and \
-            not chip.find_files('tool', tool, 'task', task, 'postscript',
-                                step=step, index=index) and \
+    if not has_pre_post_script(chip) and \
             chip.get('tool', tool, 'task', task, 'var', 'fin_add_fill',
                      step=step, index=index) == ["true"]:
         pdk = chip.get('option', 'pdk')
@@ -57,10 +72,11 @@ def pre_process(chip):
         if not chip.find_files('pdk', pdk, 'aprtech', tool, stackup, libtype, 'fill'):
             chip.set('record', 'status', NodeStatus.SKIPPED, step=step, index=index)
             chip.logger.warning(f'{step}{index} will be skipped since there is nothing to do.')
+            return
 
-    or_pre_process(chip)
+    define_ord_files(chip)
     build_pex_corners(chip)
 
 
 def post_process(chip):
-    or_post_process(chip)
+    extract_metrics(chip)

siliconcompiler/tools/openroad/global_placement.py

@@ -0,0 +1,58 @@
+from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools.openroad._apr import setup as apr_setup
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import \
+    define_ord_params, define_sta_params, define_sdc_params, \
+    define_gpl_params, define_grt_params, define_rsz_params
+from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
+from siliconcompiler.tools.openroad._apr import extract_metrics
+
+
+def setup(chip):
+    '''
+    Perform global placement
+    '''
+
+    # Generic apr tool setup.
+    apr_setup(chip)
+
+    # Task setup
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'script', 'apr/sc_global_placement.tcl',
+             step=step, index=index)
+
+    # Setup task IO
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    # set default values for openroad
+    define_ord_params(chip)
+    define_sta_params(chip)
+    define_sdc_params(chip)
+    define_gpl_params(chip)
+    define_grt_params(chip)
+    define_rsz_params(chip)
+
+    set_reports(chip, [
+        'setup',
+        'unconstrained',
+        'power',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density'
+    ])
+
+
+def pre_process(chip):
+    define_ord_files(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    extract_metrics(chip)

siliconcompiler/tools/openroad/global_route.py

@@ -0,0 +1,63 @@
+from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools.openroad._apr import setup as apr_setup
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import \
+    define_ord_params, define_sta_params, define_sdc_params, \
+    define_grt_params, define_drt_params
+from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
+from siliconcompiler.tools.openroad._apr import extract_metrics
+
+
+def setup(chip):
+    '''
+    Perform global routing
+    '''
+
+    # Generic apr tool setup.
+    apr_setup(chip)
+
+    # Task setup
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'script', 'apr/sc_global_route.tcl',
+             step=step, index=index)
+
+    # Setup task IO
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    # set default values for openroad
+    define_ord_params(chip)
+    define_sta_params(chip)
+    define_sdc_params(chip)
+    define_grt_params(chip, load_all=True)
+    define_drt_params(chip)
+
+    set_reports(chip, [
+        'setup',
+        'hold',
+        'unconstrained',
+        'clock_skew',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'optimization_placement',
+        'clock_placement',
+        'clock_trees'
+    ])
+
+
+def pre_process(chip):
+    define_ord_files(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    extract_metrics(chip)

siliconcompiler/tools/openroad/init_floorplan.py

@@ -0,0 +1,103 @@
+from siliconcompiler.tools._common import input_provides, add_common_file, get_tool_task
+from siliconcompiler.tools._common.asic import set_tool_task_var
+
+from siliconcompiler.tools.openroad._apr import setup as apr_setup
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import \
+    define_ord_params, define_sta_params, define_sdc_params, \
+    define_tiecell_params, define_pad_params, define_ppl_params
+from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
+from siliconcompiler.tools.openroad._apr import extract_metrics
+
+
+def setup(chip):
+    '''
+    Perform floorplanning and initial pin placements
+    '''
+
+    # Generic apr tool setup.
+    apr_setup(chip)
+
+    # Task setup
+    design = chip.top()
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'script', 'apr/sc_init_floorplan.tcl',
+             step=step, index=index)
+
+    # Setup task IO
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+    add_common_file(chip, 'sc_pin_constraint', 'tcl/sc_pin_constraints.tcl')
+
+    # set default values for task
+    define_ord_params(chip)
+    define_sta_params(chip)
+    define_sdc_params(chip)
+    define_pad_params(chip)
+    define_ppl_params(chip)
+    define_tiecell_params(chip)
+
+    set_tool_task_var(chip, param_key='ifp_snap_strategy',
+                      default_value='site',
+                      schelp='Snapping strategy to use when placing macros. '
+                             'Allowed values: none, site, manufacturing_grid')
+
+    set_tool_task_var(chip, param_key='remove_synth_buffers',
+                      default_value=True,
+                      schelp='remove buffers inserted by synthesis')
+
+    set_tool_task_var(chip, param_key='remove_dead_logic',
+                      default_value=False,
+                      schelp='remove logic which does not drive a primary output')
+
+    # Handle additional input files
+    if chip.valid('input', 'asic', 'floorplan') and \
+       chip.get('input', 'asic', 'floorplan', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['input', 'asic', 'floorplan']),
+                 step=step, index=index)
+
+    if f'{design}.vg' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.vg',
+                 step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require', 'input,netlist,verilog',
+                 step=step, index=index)
+
+    set_reports(chip, [
+        'check_setup',
+        'setup',
+        'unconstrained',
+        'power'
+    ])
+
+    # Setup required
+    for component in chip.getkeys('constraint', 'component'):
+        for key in chip.getkeys('constraint', 'component', component):
+            if chip.get('constraint', 'component', component, key, step=step, index=index):
+                chip.add('tool', tool, 'task', task, 'require',
+                         ','.join(['constraint', 'component', component, key]),
+                         step=step, index=index)
+    for pin in chip.getkeys('constraint', 'pin'):
+        for key in chip.getkeys('constraint', 'pin', pin):
+            if chip.get('constraint', 'pin', pin, key, step=step, index=index):
+                chip.add('tool', tool, 'task', task, 'require',
+                         ','.join(['constraint', 'pin', pin, key]),
+                         step=step, index=index)
+    for ifp in ('aspectratio', 'density', 'corearea', 'coremargin', 'outline'):
+        if chip.get('constraint', ifp, step=step, index=index):
+            chip.add('tool', tool, 'task', task, 'require',
+                     ','.join(['constraint', ifp]),
+                     step=step, index=index)
+
+
+def pre_process(chip):
+    build_pex_corners(chip)
+    define_ord_files(chip)
+
+
+def post_process(chip):
+    extract_metrics(chip)