siliconcompiler 0.28.9__py3-none-any.whl → 0.29.0__py3-none-any.whl

siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.28.9'
+version = '0.29.0'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

siliconcompiler/apps/sc_remote.py

@@ -5,9 +5,7 @@ import sys
 
 from siliconcompiler import Chip
 from siliconcompiler import SiliconCompilerError
-from siliconcompiler.remote.client import cancel_job, check_progress, delete_job, \
-    remote_ping, remote_run_loop, _remote_ping
-from siliconcompiler.remote.client import configure_server, configure_whitelist, configure_print
+from siliconcompiler.remote.client import Client, ConfigureClient
 from siliconcompiler.scheduler import _finalize_run
 from siliconcompiler.flowgraph import _get_flowgraph_entry_nodes, _get_flowgraph_node_outputs, \
     nodes_to_execute
@@ -108,29 +106,33 @@ To delete a job, use:
 
     if args['configure']:
         if args['list']:
-            configure_print(chip)
+            client = Client(chip)
+            client.print_configuration()
             return 0
 
         if not args['add'] and not args['remove']:
             try:
-                configure_server(chip, server=args['server'])
+                client = ConfigureClient(chip)
+                client.configure_server(server=args['server'])
             except ValueError as e:
                 chip.logger.error(e)
                 return 1
         else:
             try:
-                configure_whitelist(chip, add=args['add'], remove=args['remove'])
+                client = ConfigureClient(chip)
+                client.configure_whitelist(add=args['add'], remove=args['remove'])
             except ValueError as e:
                 chip.logger.error(e)
                 return 1
 
         return 0
 
+    client = Client(chip)
     # Main logic.
     # If no job-related options are specified, fetch and report basic info.
     # Create temporary Chip object and check on the server.
     try:
-        remote_ping(chip)
+        client.check()
     except SiliconCompilerError as e:
         chip.logger.error(f'{e}')
         return 1
@@ -138,7 +140,7 @@ To delete a job, use:
     # If the -cancel flag is specified, cancel the job.
     if args['cancel']:
         try:
-            cancel_job(chip)
+            client.cancel_job()
         except SiliconCompilerError as e:
             chip.logger.error(f'{e}')
             return 1
@@ -146,7 +148,7 @@ To delete a job, use:
     # If the -delete flag is specified, delete the job.
     elif args['delete']:
         try:
-            delete_job(chip)
+            client.delete_job()
         except SiliconCompilerError as e:
             chip.logger.error(f'{e}')
             return 1
@@ -162,10 +164,8 @@ To delete a job, use:
             outputs = _get_flowgraph_node_outputs(chip, flow, entry_node)
             chip.set('option', 'from', list(map(lambda node: node[0], outputs)))
         # Enter the remote run loop.
-        chip._init_logger(step='remote', index='0', in_run=True)
         try:
-            rsp = _remote_ping(chip)
-            remote_run_loop(chip, rsp['progress_interval'])
+            client._run_loop()
         except SiliconCompilerError as e:
             chip.logger.error(f'{e}')
             return 1
@@ -185,8 +185,9 @@ To delete a job, use:
     # If only a manifest is specified, make a 'check_progress/' request and report results:
     elif chip_cfg:
         try:
-            check_progress(chip, [], {})
-        except SiliconCompilerError as e:
+            info = client.check_job_status()
+            client._report_job_status(info)
+        except Exception as e:
             chip.logger.error(f'{e}')
             return 1
 

siliconcompiler/apps/sc_show.py

@@ -19,10 +19,10 @@ def main():
     Examples:
 
     sc-show
-    (displays build/adder/job0/write_gds/0/outputs/adder.gds)
+    (displays build/adder/job0/write.gds/0/outputs/adder.gds)
 
     sc-show -design adder
-    (displays build/adder/job0/write_gds/0/outputs/adder.gds)
+    (displays build/adder/job0/write.gds/0/outputs/adder.gds)
 
     sc-show -design adder -arg_step floorplan
     (displays build/adder/job0/floorplan/0/outputs/adder.def)
@@ -31,13 +31,13 @@ def main():
     (displays build/adder/job0/place/1/outputs/adder.def)
 
     sc-show -design adder -jobname rtl2gds
-    (displays build/adder/rtl2gds/write_gds/0/outputs/adder.gds)
+    (displays build/adder/rtl2gds/write.gds/0/outputs/adder.gds)
 
     sc-show -cfg build/adder/rtl2gds/adder.pkg.json
-    (displays build/adder/rtl2gds/write_gds/0/outputs/adder.gds)
+    (displays build/adder/rtl2gds/write.gds/0/outputs/adder.gds)
 
     sc-show -design adder -ext odb
-    (displays build/adder/job0/write_data/0/outputs/adder.odb)
+    (displays build/adder/job0/write.views/0/outputs/adder.odb)
 
     sc-show build/adder/job0/route/1/outputs/adder.def
     (displays build/adder/job0/route/1/outputs/adder.def)

siliconcompiler/apps/utils/replay.py

@@ -0,0 +1,136 @@
+# Copyright 2024 Silicon Compiler Authors. All Rights Reserved.
+
+# Standard Modules
+import os
+import stat
+import sys
+
+import siliconcompiler
+from siliconcompiler.apps._common import UNSET_DESIGN
+from siliconcompiler import SiliconCompilerError
+from siliconcompiler import utils
+
+
+###########################
+def main():
+    progname = "summarize"
+    description = """
+    ------------------------------------------------------------
+    Utility script to print job record information from a manifest
+    needed to replay that manifest.
+    ------------------------------------------------------------
+    """
+    # Create a base chip class.
+    chip = siliconcompiler.Chip(UNSET_DESIGN)
+
+    # Read command-line inputs and generate Chip objects to run the flow on.
+    try:
+        generation_arg = {
+            'metavar': '<path>',
+            'help': '(optional) Path to generate replay files to, if specified.',
+            'sc_print': True
+        }
+        args = chip.create_cmdline(
+            progname,
+            description=description,
+            switchlist=['-cfg',
+                        '-jobname',
+                        '-loglevel'],
+            additional_args={
+                '-path': generation_arg
+            })
+    except SiliconCompilerError:
+        return 1
+    except Exception as e:
+        chip.logger.error(e)
+        return 1
+
+    design = chip.get('design')
+    if design == UNSET_DESIGN:
+        chip.logger.error('Design not loaded')
+        return 1
+
+    # Print Job Summary
+    jobname = chip.get('option', 'jobname')
+    pythonpackages = chip.get('record', 'pythonpackage', job=jobname)
+
+    pythonversion = set()
+    nodes = set()
+    for version, step, index in chip.schema._getvals('history', jobname, 'record', 'pythonversion'):
+        pythonversion.add(version)
+        nodes.add((step, index))
+
+    if len(pythonversion) > 1:
+        chip.logger.warning(f"More than one python version detected: {', '.join(pythonversion)}")
+    pythonversion = list(pythonversion)[0]
+
+    tools = {}
+    tool_versions = []
+    for step, index in nodes:
+        toolpath = chip.get('record', 'toolpath', job=jobname, step=step, index=index)
+        toolversion = chip.get('record', 'toolversion', job=jobname, step=step, index=index)
+
+        if toolpath is None:
+            continue
+
+        tools.setdefault(toolpath, set()).add(toolversion)
+        if toolversion:
+            tool = chip.get('flowgraph', chip.get('option', 'flow'), step, index, 'tool')
+            tool_versions.append(
+                ((step, index), tool, toolversion)
+            )
+
+    print("SUMMARY       :")
+    print(f"design        : {chip.design}")
+    print(f"pythonversion : {pythonversion}")
+
+    print("Python packages requires:")
+    for pkg in sorted(pythonpackages):
+        print(f"  {pkg}")
+
+    print("Tool requirements:")
+    tool_len = max([len(os.path.basename(tool)) for tool, _ in tools.items()])
+    for tool, version in tools.items():
+        print(f"  {os.path.basename(tool):<{tool_len}}: {', '.join(version)}")
+
+    if 'path' in args and args['path']:
+        path = args['path']
+        os.makedirs(path, exist_ok=True)
+        with open(os.path.join(path, 'requirements.txt'), 'w', encoding='utf-8') as wf:
+            wf.write(utils.get_file_template('replay/requirements.txt').render(
+                design=chip.design,
+                source=', '.join(chip.find_files('option', 'cfg')),
+                jobname=jobname,
+                pkgs=pythonpackages
+            ))
+
+        scripts = []
+        scripts.append(os.path.join(path, 'setup.sh'))
+        with open(scripts[-1], 'w', encoding='utf-8') as wf:
+            wf.write(utils.get_file_template('replay/setup.sh').render(
+                design=chip.design,
+                source=', '.join(chip.find_files('option', 'cfg')),
+                jobname=jobname,
+                pythonversion=pythonversion
+            ))
+
+        scripts.append(os.path.join(path, 'run.py'))
+        with open(scripts[-1], 'w', encoding='utf-8') as wf:
+            wf.write(utils.get_file_template('replay/run.py.j2').render(
+                design=chip.design,
+                source=', '.join(chip.find_files('option', 'cfg')),
+                cfgs=chip.find_files('option', 'cfg'),
+                jobname=jobname,
+                tool_versions=sorted(tool_versions)
+            ))
+
+        for script in scripts:
+            permissions = stat.S_IMODE(os.lstat(script).st_mode)
+            os.chmod(script, permissions | stat.S_IXUSR)
+
+    return 0
+
+
+#########################
+if __name__ == "__main__":
+    sys.exit(main())

siliconcompiler/core.py

@@ -2058,19 +2058,11 @@ class Chip:
         dot.attr(bgcolor=background)
 
         subgraphs = {
-            "graphs": {
-                "sc-inputs": {
-                    "graphs": {},
-                    "nodes": []
-                }
-            },
+            "graphs": {},
             "nodes": []
         }
         for node, info in nodes.items():
-            if info['is_input']:
-                subgraph_temp = subgraphs["graphs"]["sc-inputs"]
-            else:
-                subgraph_temp = subgraphs
+            subgraph_temp = subgraphs
 
             for key in node.split(".")[0:-1]:
                 if key not in subgraph_temp["graphs"]:
@@ -2079,6 +2071,15 @@ class Chip:
                         "nodes": []
                     }
                 subgraph_temp = subgraph_temp["graphs"][key]
+
+            if info['is_input']:
+                if "sc-inputs" not in subgraph_temp["graphs"]:
+                    subgraph_temp["graphs"]["sc-inputs"] = {
+                        "graphs": {},
+                        "nodes": []
+                    }
+                subgraph_temp = subgraph_temp["graphs"]["sc-inputs"]
+
             subgraph_temp["nodes"].append(node)
 
         with dot.subgraph(name='inputs') as input_graph:
@@ -2131,7 +2132,8 @@ class Chip:
             for subgraph in graph_info["graphs"]:
                 child_prefix = prefix
                 if get_node_count(graph_info["graphs"][subgraph]) > 1:
-                    child_prefix = f"{child_prefix}{subgraph}."
+                    if subgraph != "sc-inputs":
+                        child_prefix = f"{child_prefix}{subgraph}."
                     graph = graphviz.Digraph(name=f"cluster_{graph_idx}")
                     graph_idx += 1
 
@@ -3126,7 +3128,7 @@ class Chip:
             extension (str): extension of file to show
 
         Examples:
-            >>> show('build/oh_add/job0/write_gds/0/outputs/oh_add.gds')
+            >>> show('build/oh_add/job0/write.gds/0/outputs/oh_add.gds')
             Displays gds file with a viewer assigned by showtool
         '''
 

siliconcompiler/flows/_common.py

@@ -22,17 +22,17 @@ def _make_docs(chip):
 
 def __get_frontends(allow_system_verilog):
     systemverilog_frontend = [
-        ('import', surelog_parse)
+        ('import.verilog', surelog_parse)
     ]
     if not allow_system_verilog:
-        systemverilog_frontend.append(('convert', sv2v_convert))
+        systemverilog_frontend.append(('import.convert', sv2v_convert))
 
     return {
         "verilog": systemverilog_frontend,
-        "chisel": [('import', chisel_convert)],
-        "c": [('import', bambu_convert)],
-        "bluespec": [('import', bluespec_convert)],
-        "vhdl": [('import', ghdl_convert)]
+        "chisel": [('import.chisel', chisel_convert)],
+        "c": [('import.c', bambu_convert)],
+        "bluespec": [('import.bluespec', bluespec_convert)],
+        "vhdl": [('import.vhdl', ghdl_convert)]
     }
 
 
@@ -45,21 +45,19 @@ def setup_multiple_frontends(flow, allow_system_verilog=False):
 
     concat_nodes = []
     flowname = flow.design
-    for frontend, pipe in __get_frontends(allow_system_verilog).items():
+    for _, pipe in __get_frontends(allow_system_verilog).items():
         prev_step = None
         for step, task in pipe:
-            step_name = f'{step}_{frontend}'
-
-            flow.node(flowname, step_name, task)
+            flow.node(flowname, step, task)
             if prev_step:
-                flow.edge(flowname, prev_step, step_name)
+                flow.edge(flowname, prev_step, step)
 
-            prev_step = step_name
+            prev_step = step
 
         if prev_step:
             concat_nodes.append(prev_step)
 
-    final_node = 'combine'
+    final_node = 'import.combine'
     flow.node(flowname, final_node, concatenate)
     for node in concat_nodes:
         flow.edge(flowname, node, final_node)

siliconcompiler/flows/asicflow.py

@@ -4,13 +4,22 @@ from siliconcompiler.flows._common import setup_multiple_frontends
 from siliconcompiler.flows._common import _make_docs
 
 from siliconcompiler.tools.yosys import syn_asic
-from siliconcompiler.tools.openroad import floorplan
-from siliconcompiler.tools.openroad import physyn
-from siliconcompiler.tools.openroad import place
-from siliconcompiler.tools.openroad import cts
-from siliconcompiler.tools.openroad import route
-from siliconcompiler.tools.openroad import dfm
-from siliconcompiler.tools.openroad import export as openroad_export
+from siliconcompiler.tools.openroad import init_floorplan
+from siliconcompiler.tools.openroad import macro_placement
+from siliconcompiler.tools.openroad import endcap_tapcell_insertion
+from siliconcompiler.tools.openroad import power_grid
+from siliconcompiler.tools.openroad import pin_placement
+from siliconcompiler.tools.openroad import global_placement
+from siliconcompiler.tools.openroad import repair_design
+from siliconcompiler.tools.openroad import detailed_placement
+from siliconcompiler.tools.openroad import clock_tree_synthesis
+from siliconcompiler.tools.openroad import repair_timing
+from siliconcompiler.tools.openroad import fillercell_insertion
+from siliconcompiler.tools.openroad import global_route
+from siliconcompiler.tools.openroad import antenna_repair
+from siliconcompiler.tools.openroad import detailed_route
+from siliconcompiler.tools.openroad import fillmetal_insertion
+from siliconcompiler.tools.openroad import write_data
 from siliconcompiler.tools.klayout import export as klayout_export
 
 from siliconcompiler.tools.builtin import minimum
@@ -70,33 +79,53 @@ def setup(flowname='asicflow',
     flow = siliconcompiler.Flow(flowname)
 
     # Linear flow, up until branch to run parallel verification steps.
-    longpipe = ['syn',
-                'synmin',
-                'floorplan',
-                'floorplanmin',
-                'place',
-                'placemin',
-                'cts',
-                'ctsmin',
-                'route',
-                'routemin',
-                'dfm']
+    longpipe = [
+        'syn',
+        'syn.min',
+        'floorplan.init',
+        'floorplan.macro_placement',
+        'floorplan.tapcell',
+        'floorplan.power_grid',
+        'floorplan.pin_placement',
+        'floorplan.min',
+        'place.global',
+        'place.repair_design',
+        'place.detailed',
+        'place.min',
+        'cts.clock_tree_synthesis',
+        'cts.repair_timing',
+        'cts.fillcell',
+        'cts.min',
+        'route.global',
+        'route.antenna_repair',
+        'route.detailed',
+        'route.min',
+        'dfm.metal_fill'
+    ]
 
     # step --> task
     tasks = {
         'syn': syn_asic,
-        'synmin': minimum,
-        'floorplan': floorplan,
-        'floorplanmin': minimum,
-        'physyn': physyn,
-        'physynmin': minimum,
-        'place': place,
-        'placemin': minimum,
-        'cts': cts,
-        'ctsmin': minimum,
-        'route': route,
-        'routemin': minimum,
-        'dfm': dfm
+        'syn.min': minimum,
+        'floorplan.init': init_floorplan,
+        'floorplan.macro_placement': macro_placement,
+        'floorplan.tapcell': endcap_tapcell_insertion,
+        'floorplan.power_grid': power_grid,
+        'floorplan.pin_placement': pin_placement,
+        'floorplan.min': minimum,
+        'place.global': global_placement,
+        'place.repair_design': repair_design,
+        'place.detailed': detailed_placement,
+        'place.min': minimum,
+        'cts.clock_tree_synthesis': clock_tree_synthesis,
+        'cts.repair_timing': repair_timing,
+        'cts.fillcell': fillercell_insertion,
+        'cts.min': minimum,
+        'route.global': global_route,
+        'route.antenna_repair': antenna_repair,
+        'route.detailed': detailed_route,
+        'route.min': minimum,
+        'dfm.metal_fill': fillmetal_insertion
     }
 
     np = {
@@ -114,7 +143,8 @@ def setup(flowname='asicflow',
     for step in longpipe:
         task = tasks[step]
         if task == minimum:
-            if prevstep in np and np[prevstep] > 1:
+            np_step = prevstep.split('.')[0]
+            if np_step in np and np[np_step] > 1:
                 flowpipe.append(step)
         else:
             flowpipe.append(step)
@@ -126,24 +156,30 @@ def setup(flowname='asicflow',
 
     # Programmatically build linear portion of flowgraph and fanin/fanout args
     prevstep = setup_multiple_frontends(flow)
+    prev_fanout = 1
     for step, task in flowtasks:
         fanout = 1
-        if step in np:
-            fanout = np[step]
+        np_step = step.split('.')[0]
+        if np_step in np and task != minimum:
+            fanout = np[np_step]
+
         # create nodes
         for index in range(fanout):
             # nodes
             flow.node(flowname, step, task, index=index)
 
+        # create edges
+        for index in range(fanout):
             # edges
+            fanin = prev_fanout
             if task == minimum:
-                fanin = 1
-                if prevstep in np:
-                    fanin = np[prevstep]
                 for i in range(fanin):
                     flow.edge(flowname, prevstep, step, tail_index=i)
             elif prevstep:
-                flow.edge(flowname, prevstep, step, head_index=index)
+                if fanin == fanout:
+                    flow.edge(flowname, prevstep, step, tail_index=index, head_index=index)
+                else:
+                    flow.edge(flowname, prevstep, step, head_index=index)
 
             # metrics
             goal_metrics = ()
@@ -151,7 +187,11 @@ def setup(flowname='asicflow',
             if task in (syn_asic, ):
                 goal_metrics = ('errors',)
                 weight_metrics = ()
-            elif task in (floorplan, physyn, place, cts, route, dfm):
+            elif task in (init_floorplan, macro_placement, endcap_tapcell_insertion,
+                          power_grid, pin_placement, global_placement, repair_design,
+                          detailed_placement, clock_tree_synthesis, repair_timing,
+                          fillercell_insertion, global_route, antenna_repair, detailed_route,
+                          fillmetal_insertion):
                 goal_metrics = ('errors', 'setupwns', 'setuptns')
                 weight_metrics = ('cellarea', 'peakpower', 'leakagepower')
 
@@ -160,12 +200,13 @@ def setup(flowname='asicflow',
             for metric in weight_metrics:
                 flow.set('flowgraph', flowname, step, str(index), 'weight', metric, 1.0)
         prevstep = step
+        prev_fanout = fanout
 
     # add write information steps
-    flow.node(flowname, 'write_gds', klayout_export)
-    flow.edge(flowname, prevstep, 'write_gds')
-    flow.node(flowname, 'write_data', openroad_export)
-    flow.edge(flowname, prevstep, 'write_data')
+    flow.node(flowname, 'write.gds', klayout_export)
+    flow.edge(flowname, prevstep, 'write.gds')
+    flow.node(flowname, 'write.views', write_data)
+    flow.edge(flowname, prevstep, 'write.views')
 
     return flow
 

siliconcompiler/remote/__init__.py

@@ -34,3 +34,14 @@ class JobStatus():
     TIMEOUT = "timeout"
 
     UNKNOWN = "unknown"
+
+
+from siliconcompiler.remote.client import Client, ConfigureClient # noqa E402
+
+
+__all__ = [
+    "NodeStatus",
+    "JobStatus",
+    "Client",
+    "ConfigureClient"
+]