siliconcompiler 0.28.9__py3-none-any.whl → 0.29.0__py3-none-any.whl

siliconcompiler/tools/yosys/syn_fpga.tcl

@@ -125,6 +125,30 @@ if { [string match {ice*} $sc_partname] } {
     yosys proc
     yosys flatten
 
+    # Note there are two possibilities for how macro mapping might be done:
+    # using the extract command (to pattern match user RTL against
+    # the techmap) or using the techmap command.  The latter is better
+    # for mapping simple multipliers; the former is better (for now)
+    # for mapping more complex DSP blocks (MAC, pipelined blocks, etc).
+    # and is also more easily extensible to arbitrary hard macros.
+    # Run separate passes of both to get best of both worlds
+
+    # An extract pass needs to happen prior to other optimizations,
+    # otherwise yosys can transform its internal model into something
+    # that doesn't match the patterns defined in the extract library
+    if { [sc_cfg_exists fpga $sc_partname file yosys_extractlib] } {
+        set sc_syn_extractlibs \
+            [sc_cfg_get fpga $sc_partname file yosys_extractlib]
+
+        foreach extractlib $sc_syn_extractlibs {
+            yosys log "Run extract with $extractlib"
+            yosys extract -map $extractlib
+        }
+    }
+
+    # Other hard macro passes can happen after the generic optimization
+    # passes take place.
+
     #Generic optimization passes; this is a fusion of the VTR reference
     #flow and the Yosys synth_ice40 flow
     yosys opt_expr
@@ -141,28 +165,12 @@ if { [string match {ice*} $sc_partname] } {
     yosys opt_expr
     yosys opt_clean
 
+    # Here is a remaining customization pass for DSP tech mapping
+
     #Map DSP blocks before doing anything else,
     #so that we don't convert any math blocks
     #into other primitives
 
-    # Note there are two possibilities for how mapping might be done:
-    # using the extract command (to pattern match user RTL against
-    # the techmap) or using the techmap command.  The latter is better
-    # for mapping simple multipliers; the former is better (for now)
-    # for mapping more complex DSP blocks (MAC, pipelined blocks, etc).
-    # and also more extensible to arbitrary hard macros.  Run separate
-    # passes of both to get best of both worlds
-
-    if { [sc_cfg_exists fpga $sc_partname file yosys_extractlib] } {
-        set sc_syn_extractlibs \
-            [sc_cfg_get fpga $sc_partname file yosys_extractlib]
-
-        foreach extractlib $sc_syn_extractlibs {
-            yosys log "Run extract with $extractlib"
-            yosys extract -map $extractlib
-        }
-    }
-
     if { [sc_cfg_exists fpga $sc_partname file yosys_dsp_techmap] } {
         set sc_syn_dsp_library \
             [sc_cfg_get fpga $sc_partname file yosys_dsp_techmap]

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "8300b5293dec4c0a0ef26cd2ba7ca6101714e155",
+    "git-commit": "8495fc80c78f4ab98bebd8cf2050fa63bc0b93c1",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -36,7 +36,7 @@
     "auto-update": false
   },
   "klayout": {
-    "version": "0.29.8",
+    "version": "0.29.10",
     "git-url": "https://github.com/KLayout/klayout.git",
     "docker-skip": true,
     "auto-update": true,
@@ -45,7 +45,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "7808819c48c167978aeb5ef34c6e5ed416e90875",
+    "git-commit": "5a636724d783edd403ac4618d6cc4def72e39cbc",
     "auto-update": true
   },
   "verilator": {
@@ -91,7 +91,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "0.47",
+    "git-commit": "v0.48",
     "version-prefix": "",
     "auto-update": true
   },

{siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.0.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.28.9
+Version: 0.29.0
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -26,34 +26,35 @@ Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
 Requires-Dist: aiohttp==3.10.11; python_version <= "3.8"
-Requires-Dist: aiohttp==3.11.2; python_version >= "3.9"
+Requires-Dist: aiohttp==3.11.10; python_version >= "3.9"
 Requires-Dist: requests==2.32.3
 Requires-Dist: PyYAML==6.0.2
 Requires-Dist: pandas>=1.1.5
 Requires-Dist: Jinja2>=2.11.3
 Requires-Dist: graphviz==0.20.3
 Requires-Dist: distro==1.9.0
-Requires-Dist: packaging<24,>=21.3
+Requires-Dist: packaging<25,>=21.3
 Requires-Dist: psutil>=5.8.0
 Requires-Dist: Pillow==10.4.0; python_version <= "3.8"
 Requires-Dist: Pillow==11.0.0; python_version >= "3.9"
 Requires-Dist: GitPython==3.1.43
-Requires-Dist: lambdapdk>=0.1.38
+Requires-Dist: lambdapdk>=0.1.40
 Requires-Dist: PyGithub==2.5.0
 Requires-Dist: urllib3>=1.26.0
 Requires-Dist: fasteners==0.19
-Requires-Dist: fastjsonschema==2.20.0
+Requires-Dist: fastjsonschema==2.21.1
 Requires-Dist: docker==7.1.0
 Requires-Dist: importlib_metadata; python_version < "3.10"
 Requires-Dist: sc-surelog==1.84.1
-Requires-Dist: orjson==3.10.11
-Requires-Dist: streamlit==1.40.1; python_full_version != "3.9.7"
+Requires-Dist: orjson==3.10.12
+Requires-Dist: streamlit==1.40.1; python_version <= "3.8"
+Requires-Dist: streamlit==1.40.2; python_version >= "3.9" and python_full_version != "3.9.7"
 Requires-Dist: streamlit_agraph==0.0.45; python_full_version != "3.9.7"
 Requires-Dist: streamlit-antd-components==0.3.2; python_full_version != "3.9.7"
 Requires-Dist: streamlit_javascript==0.1.5; python_full_version != "3.9.7"
 Requires-Dist: streamlit-autorefresh==1.0.1; python_full_version != "3.9.7"
 Provides-Extra: test
-Requires-Dist: pytest==8.3.3; extra == "test"
+Requires-Dist: pytest==8.3.4; extra == "test"
 Requires-Dist: pytest-xdist==3.6.1; extra == "test"
 Requires-Dist: pytest-timeout==2.3.1; extra == "test"
 Requires-Dist: pytest-asyncio==0.24.0; extra == "test"
@@ -61,9 +62,10 @@ Requires-Dist: pytest-cov==5.0.0; python_version <= "3.8" and extra == "test"
 Requires-Dist: pytest-cov==6.0.0; python_version >= "3.9" and extra == "test"
 Requires-Dist: responses==0.25.3; extra == "test"
 Requires-Dist: PyVirtualDisplay==3.0; extra == "test"
-Requires-Dist: flake8==7.1.1; extra == "test"
-Requires-Dist: tclint==0.4.2; extra == "test"
-Requires-Dist: codespell==2.3.0; extra == "test"
+Provides-Extra: lint
+Requires-Dist: flake8==7.1.1; extra == "lint"
+Requires-Dist: tclint==0.5.0; extra == "lint"
+Requires-Dist: codespell==2.3.0; extra == "lint"
 Provides-Extra: docs
 Requires-Dist: Sphinx==8.1.3; extra == "docs"
 Requires-Dist: pip-licenses==5.0.0; extra == "docs"
@@ -73,7 +75,7 @@ Provides-Extra: profile
 Requires-Dist: gprof2dot==2024.6.6; extra == "profile"
 Provides-Extra: examples
 Requires-Dist: migen==0.9.2; extra == "examples"
-Requires-Dist: lambdalib==0.3.1; extra == "examples"
+Requires-Dist: lambdalib==0.3.2; extra == "examples"
 
 ![SiliconCompiler](https://raw.githubusercontent.com/siliconcompiler/siliconcompiler/main/docs/_static/sc_logo_with_text.png)
 

{siliconcompiler-0.28.9.dist-info → siliconcompiler-0.29.0.dist-info}/RECORD

@@ -1,8 +1,8 @@
 siliconcompiler/__init__.py,sha256=Ke_Bcryj9N6MoUq_5z_IDW3qMrUzR-3-kJVsvUenYzY,511
 siliconcompiler/__main__.py,sha256=JwWkcvaNngqgMWprEQ1cFy2Wdq9GMvk46UGTHyh_qvM,170
 siliconcompiler/_common.py,sha256=c6r0SbI2xTpNOZayFsyCDo0riJGNJSPN-0zW8R7rDBI,1488
-siliconcompiler/_metadata.py,sha256=ISw0dgmSuNTS8xpsds6hA2uMv313WiLdIUnkF-qEI30,1264
-siliconcompiler/core.py,sha256=_T1eEY7lUsrbaEBUaG1WSAzY2JFxyz5tXEKxvoCGZaI,135718
+siliconcompiler/_metadata.py,sha256=FWWPgsF9yds5x4TtUHjoCr0fI4uNpjHLReHLkws--Ck,1264
+siliconcompiler/core.py,sha256=jmrE-o9IDB8aj7i4oQxuD8ikVMybopaLhzmtZA6-MBY,135846
 siliconcompiler/flowgraph.py,sha256=WLcbBWFj5DdYRRIxNy_Djm2v4yN9WELQM_ypNPB5QVM,21963
 siliconcompiler/issue.py,sha256=9ZpdEBh8QB56-bZ1YXRnjqgg9hwnFty2u1o5oI66W7M,11125
 siliconcompiler/package.py,sha256=nGFzYI63dwO6ULEyEGHu_Pd-8QYMWu8BtpzgwEmppag,14111
@@ -14,10 +14,11 @@ siliconcompiler/apps/sc.py,sha256=7wKQ89DZLVXMNbjAgIu9F8Erb_NmrBkV4lJNjBUt8_c,32
 siliconcompiler/apps/sc_dashboard.py,sha256=kGyMYbgKgZMBUrTyft6mEvRnmcrKA7JunrkWZ8VwSwM,3478
 siliconcompiler/apps/sc_install.py,sha256=aFCFXaXarREvt_rTAcOZoqDwj-Df620dLBxO2Fda9so,6273
 siliconcompiler/apps/sc_issue.py,sha256=PUXFWne6MWY0Ntak3PnMZ84tpEZ5S1Pta5B3AkxMdoY,6404
-siliconcompiler/apps/sc_remote.py,sha256=M7wH7lULkeDSEiVkvTY2xmuAK8lJ-3eVM6fC3bqj4s8,7331
+siliconcompiler/apps/sc_remote.py,sha256=jsQWEqZnoKrJI9FcA2ILZYJ8F7uvLuwYI4N23dRwVRs,7241
 siliconcompiler/apps/sc_server.py,sha256=d3SCfKtNneIBiAk7Udc5SqXvSIoFSK40iHWcKuY7unk,894
-siliconcompiler/apps/sc_show.py,sha256=KZGm6nd2On3a15u-OPQnLxNetiHndJKqzWMZG2_Q_1g,4652
+siliconcompiler/apps/sc_show.py,sha256=H0_evnBqr02FJVlIaFIva4RrYZ6M2otlWTaTCqFQPlg,4653
 siliconcompiler/apps/smake.py,sha256=jj69IuMLf4jblpVGeLT3GAvC-zDLHwPq16YPKtHosdA,7124
+siliconcompiler/apps/utils/replay.py,sha256=zCoGx9WJa61Yi9yDp6qNS-YzpTvU6zQLChBoMWWXViA,4611
 siliconcompiler/apps/utils/summarize.py,sha256=mcViWpuS8UI2JqOF-QD99YAl0tjiy6_TbVl_coRCmNI,1291
 siliconcompiler/checklists/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/checklists/oh_tapeout.py,sha256=xBXAHOVNslFUlOfVTLLoPEJazczP8MTsa5EGo5GYQk0,1441
@@ -28,8 +29,8 @@ siliconcompiler/data/RobotoMono/LICENSE.txt,sha256=Pd-b5cKP4n2tFDpdx27qJSIq0d1ok
 siliconcompiler/data/RobotoMono/RobotoMono-Regular.ttf,sha256=w8iOaiprWYm5hBNPzFHOaddn_RgCWHLoz0FsBMTaryA,86908
 siliconcompiler/data/RobotoMono/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/flows/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
-siliconcompiler/flows/_common.py,sha256=-T3OPvzgOpzVdHdgQANtPm5h7zzgghhKd4XJH4EKqcE,2133
-siliconcompiler/flows/asicflow.py,sha256=AbnwSersQ4EsBaAvnH3sz44Tj62aroZSGZaTgVSmO6g,6084
+siliconcompiler/flows/_common.py,sha256=hcKVUPRK74t6JYU23UnY4qkFnu1-uauLwzsZjqzaYu0,2110
+siliconcompiler/flows/asicflow.py,sha256=Hj0goWMxYGSqLmX_07z_uFePJvWcDGhY0afTeJblz7E,8113
 siliconcompiler/flows/asictopflow.py,sha256=UosrdJhh_NVyjigzz2KGhqcy2UBotkwTUUnCdOVaZXg,1155
 siliconcompiler/flows/drcflow.py,sha256=CinpSA2eHtqSlOIxTeXSoyV_TstFZ7uZ1VA9qAHihh8,230
 siliconcompiler/flows/dvflow.py,sha256=uchIXjAmKTQljkoBUMl9UWFvzwsON4vFWTBGCxPpKE4,3064
@@ -59,8 +60,8 @@ siliconcompiler/pdks/gf180.py,sha256=yT_tQmfXTMuU-NngX1lakxPXVxZxwdl_FwNP-Rxx2rU
 siliconcompiler/pdks/ihp130.py,sha256=grtX2Z2nQiQqtXGwkYcux3CrUM7EZp18F-s_yLxW0J4,204
 siliconcompiler/pdks/interposer.py,sha256=FwkgfEPg2dnfYoyeRgAanwhZkGqSSMZfpwnOSovzZ0s,208
 siliconcompiler/pdks/skywater130.py,sha256=6UxJaWDQfs180tbKAfhLT2jfO6yTa41cdFrBKxCfniU,204
-siliconcompiler/remote/__init__.py,sha256=2tRoHeocMaOltgsablWrX31KESPgP3In0oEJvaZDEY8,810
-siliconcompiler/remote/client.py,sha256=5wPYCPmYqXH3jJ5qWt7Lbkrkkin4b09PoHA96W2Ae8I,31938
+siliconcompiler/remote/__init__.py,sha256=MoYnC1lkgbT5hN5Qi-0gTItaTWI2U1E8OuleffdTDSQ,977
+siliconcompiler/remote/client.py,sha256=vndAQRgveaCCvnlM8QjQX30ioy4rA5MI2p5ACZOy_sw,32695
 siliconcompiler/remote/schema.py,sha256=fTnerloQXqUgCB5VNWGRfzPiraSG1Ve-b_mw7siAdnQ,4224
 siliconcompiler/remote/server.py,sha256=wJb3qSjBzAFKnp9rdkMBiXdp7Aex6xSXVLXaUzw6Rpg,19657
 siliconcompiler/remote/server_schema/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
@@ -80,9 +81,9 @@ siliconcompiler/remote/server_schema/responses/get_results.json,sha256=h4XraLW4h
 siliconcompiler/remote/server_schema/responses/remote_run.json,sha256=FWW_0m46qwIJHiTriISzChKHJF6G9RIwP0rmp1OjIuA,475
 siliconcompiler/report/__init__.py,sha256=ADa-8Jwy4fl2Wtg0ejy4Tvil805uwA4WWTdK125JKcs,388
 siliconcompiler/report/html_report.py,sha256=Wh5X7iQpfIEHcs-WrVE9dtDf-gkz3GhT_yf8kVG0O3o,2597
-siliconcompiler/report/report.py,sha256=OPJhuKAnUzP-dm-6CG6Fy45Gm_rbMapey2WKuJiouYI,14924
+siliconcompiler/report/report.py,sha256=tngpaUczWiyXCYbgbSfQL1wbPn08qgUG3usHXvTwxGg,15004
 siliconcompiler/report/summary_image.py,sha256=tKuoLiG6Whvnc8LHeSzU4FookpBkYYCMWUGb-ux2i8k,3570
-siliconcompiler/report/summary_table.py,sha256=Y5ByOCJQtNOXIz5n9VU_CBHOTdSE0g8ClmfflWkQcXU,3386
+siliconcompiler/report/summary_table.py,sha256=j7MrwGacCemAWNOtyHiYop9XRQPzIEWHyRl4dfS1yI8,3386
 siliconcompiler/report/utils.py,sha256=70klZsAKwhW55kOxBBdV9zzOU-NorMk6y6riMyKXo7c,6423
 siliconcompiler/report/dashboard/__init__.py,sha256=bvSfStUvkMa1zW1R5WtzzzKKAMm9FCNiPbIIFXOotJ0,5554
 siliconcompiler/report/dashboard/state.py,sha256=qBAmLpKb0xXqf2vRbBBgYs8P71v3MGIL6z0WHoAED-Y,5924
@@ -97,7 +98,7 @@ siliconcompiler/report/dashboard/layouts/vertical_flowgraph_node_tab.py,sha256=0
 siliconcompiler/report/dashboard/layouts/vertical_flowgraph_sac_tabs.py,sha256=g6lrnXJVEkTh7OQY1xCgl_q0So0XewItuY0sjnjaBCA,4086
 siliconcompiler/report/dashboard/utils/__init__.py,sha256=mkcBAlfPovfgoRv9nPbtgQSeFglwlxlSIXsEQmdsDz8,2540
 siliconcompiler/report/dashboard/utils/file_utils.py,sha256=5MKAyf7TGXQIc3yxwbP1H6xi0NGwUfzu2j3LOv1Yei0,3333
-siliconcompiler/scheduler/__init__.py,sha256=bkJ5S06BNXsdfjx5nPcgak_9FT8XHxgsnLIYvee5uvk,84997
+siliconcompiler/scheduler/__init__.py,sha256=E_eBUuM6FXwX2BIfey-LJpigF-j_kaPN2OAqAlb2eS4,86247
 siliconcompiler/scheduler/docker_runner.py,sha256=bzGIqYpdtxoM_A4ko_LEADYAbHY89jiKHplVB1Zzh_k,8065
 siliconcompiler/scheduler/run_node.py,sha256=IWodOtT6b_MO5oXpEiF0th1Q3v7AD66jE182lY-aGv4,5063
 siliconcompiler/scheduler/send_messages.py,sha256=Pq0Bt7LknGsQZk_bSkL0rRdpUNGz_WzS1A3UyDpBp_0,6614
@@ -105,11 +106,11 @@ siliconcompiler/scheduler/slurm.py,sha256=CAuN5xmiWhk_k3CW6yMe5iukex4CWxp5Ox6_qA
 siliconcompiler/scheduler/validation/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/scheduler/validation/email_credentials.json,sha256=hkJs0U2h2Bgm1zxeXvanIJ-prPhpn_aU6e3qwIs7qA0,1997
 siliconcompiler/schema/__init__.py,sha256=Gdny2AwDdg-X3RvghOHQYl3aG2alvMuK5CsSkFGKuYU,120
-siliconcompiler/schema/schema_cfg.py,sha256=K1xySfHNenZk33NJnQcqsv-xfByxshwLf4xPQCU0vR8,183674
-siliconcompiler/schema/schema_obj.py,sha256=85NFfP1P4Gjoxw2dFMWM7B6cHx94bY2sqkGuj8nCFMo,75000
+siliconcompiler/schema/schema_cfg.py,sha256=8PZakYMN4lvCXtC0dtFZiD24-TqeQaMbLnYU1pe2sW8,184229
+siliconcompiler/schema/schema_obj.py,sha256=HUiBiEPh-HS69CIR6GTvuHpLG_po7lKVWMjL23wxJVo,75474
 siliconcompiler/schema/utils.py,sha256=V8xDBpQ3gIiEpuzme15h7xEz601uGi8tNi0QyK175qk,4018
 siliconcompiler/sphinx_ext/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
-siliconcompiler/sphinx_ext/dynamicgen.py,sha256=ffucph_vUglkhs3NyK-Ml_2pHZ25aSbOdmZghg0I-J0,35219
+siliconcompiler/sphinx_ext/dynamicgen.py,sha256=7BlYoNPhJ_SkEteZp87edaXfgQ7PhebeL7EgB7KQmz8,35290
 siliconcompiler/sphinx_ext/schemagen.py,sha256=5gQzx5dfCJ2ysMXkmsS7xcOmvj5ZkrXa0c_V-d6uHgc,7677
 siliconcompiler/sphinx_ext/utils.py,sha256=JNktfS5nYZE_DnXRX_fwOBkc5kWgLkB0Urxbe_lvPNc,4079
 siliconcompiler/targets/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
@@ -117,7 +118,7 @@ siliconcompiler/targets/asap7_demo.py,sha256=RBCjAx3laq2xUT7w--b9oIVx8r87QyKfBRX
 siliconcompiler/targets/asic_demo.py,sha256=jRvbDhMZDGf-8AQ241vu8qLgloxPUToAn01Ybaaj_wo,1094
 siliconcompiler/targets/fpgaflow_demo.py,sha256=0fqCaXa8_gicQCiz4m_mhI8_JY1qQlBO3mH45-YzMGA,1288
 siliconcompiler/targets/freepdk45_demo.py,sha256=O983Nwrs9h_HHlHtlUUrP0cPgdf3IlME1yWXCRgdL_A,1953
-siliconcompiler/targets/gf180_demo.py,sha256=oTs07GFFyQT0LaE7jVdoLSBuGqpOGLyL-ThQ25ZpCkc,3075
+siliconcompiler/targets/gf180_demo.py,sha256=-GiyRNVnoouILXV7_mCANSsOT6gmlmFKqn0JOJ_vS9g,3062
 siliconcompiler/targets/ihp130_demo.py,sha256=3nCxfM0-XpZWjhE1yQezZKBGJwtf6AjpeinPM4z6wv0,2688
 siliconcompiler/targets/interposer_demo.py,sha256=f9vH4NXhU2GUkPm8NJbo_MrTRJIPEr1hzQlkQwBbvOU,2234
 siliconcompiler/targets/skywater130_demo.py,sha256=ct-kdVuZm2idynFm8eEZlL2S4-rfzWe16in8lOZPqrU,2689
@@ -128,6 +129,9 @@ siliconcompiler/templates/email/summary.j2,sha256=OLdrWEvg_VxefqSlJ8QDsO-NIuk4Ab
 siliconcompiler/templates/issue/README.txt,sha256=2vFnTt8Npy73GPrWwjeJ53H9tOhwmHb7WxNXXrDgizY,671
 siliconcompiler/templates/issue/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/templates/issue/run.sh,sha256=pwWNRym9P06jtns7_acKTu1zrTEjK4dA9EDV_eKdLds,147
+siliconcompiler/templates/replay/requirements.txt,sha256=Fy85pcZE9V7BHSDOgGf9ZVkRGmoY4SY92neRp7ka7WU,127
+siliconcompiler/templates/replay/run.py.j2,sha256=okWgvlHVpwzqeGk3qAY6x-AWNowBBAor4IVBWJSkwtg,538
+siliconcompiler/templates/replay/setup.sh,sha256=N_1Imrke8wZL_kup258pLbY3BTjixjfx557KL4NVdXc,470
 siliconcompiler/templates/report/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/templates/report/bootstrap.min.css,sha256=YvdLHPgkqJ8DVUxjjnGVlMMJtNimJ6dYkowFFvp4kKs,163873
 siliconcompiler/templates/report/bootstrap.min.js,sha256=cMPWkL3FzjuaFSfEYESYmjF25hCIL6mfRSPnW8OVvM4,59219
@@ -138,8 +142,8 @@ siliconcompiler/templates/slurm/run.sh,sha256=uXs91H0vjLB8G8vaezxXSr3XNR2EUiXH1d
 siliconcompiler/templates/tcl/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/templates/tcl/manifest.tcl.j2,sha256=XT2pKuPSaa2GPJj1IpEl3Al5N70yqQS8jZecmpyeV4o,3547
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@@ -153,7 +157,7 @@ siliconcompiler/tools/bluespec/convert.py,sha256=eDptNYocnia6YIAdySkDZmLhM-vYvAe
 siliconcompiler/tools/builtin/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
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 siliconcompiler/tools/builtin/builtin.py,sha256=SfkmFaqLE8U-sjimVBtIgR8INRenV0eW0buTTgeTDPI,831
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 siliconcompiler/tools/builtin/join.py,sha256=-RLK7PG15wfHpqtm-MAV4xzxNjEm1-ieKFvBJN8zBYM,554
 siliconcompiler/tools/builtin/maximum.py,sha256=L9pz8s_uZWHPt_IQavuEQXaTyrI3fI2f-aLqLlk-odI,1295
 siliconcompiler/tools/builtin/minimum.py,sha256=8qA8DsXy3mXm20P1euEQfXlDGjMEwvzDHIqF-fhDTao,1659
@@ -211,43 +215,66 @@ siliconcompiler/tools/netgen/sc_lvs.tcl,sha256=EKDVaYZZMi__ga-t8x-SWEyDG9Zat0wyZ
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 siliconcompiler/tools/openroad/templates/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/tools/openroad/templates/pex.tcl,sha256=t-54kEYkIFkC5hIiMWw6IZD9guRwG90zT4Mt9erYUnY,299
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 siliconcompiler/tools/opensta/report_libraries.py,sha256=9DPPQyh7QEEJi1HZR0m086WZPbB22h5aG-yTuHNW_uE,828
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@@ -302,17 +329,17 @@ siliconcompiler/tools/yosys/sc_lec.tcl,sha256=U86yboSq1TKiHKG2hjYUeO9wsCGvHLeQ6y
 siliconcompiler/tools/yosys/sc_screenshot.tcl,sha256=-7Bb-HhJsZjSdSIlYCTZnZgigwBoN_1FNik9Ba_flos,2853
 siliconcompiler/tools/yosys/sc_syn.tcl,sha256=ZtLbH-x9tPdZgHwcCLWZ4qQ4zqh1imLluj2LyW86P4k,2321
 siliconcompiler/tools/yosys/screenshot.py,sha256=Octzl15bG8LmXdyU-hv9QsP9GTrhoLYzdvi_yTRzXXo,5629
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 siliconcompiler/tools/yosys/syn_fpga.py,sha256=rF4TMBUhmtiWwdx1KJeW-cNiAnkTXmo_0htyuUE7plY,5427
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 siliconcompiler/tools/yosys/syn_strategies.tcl,sha256=YJ5bXCdUNDZZ4EY4wBGS-9m0EeNlANBIO9e5a_6A0KA,5329
 siliconcompiler/tools/yosys/yosys.py,sha256=77GTkg_ifbkJI5D2aRbj6rl1YNSDhZ139OWfXHag5VQ,4986
 siliconcompiler/tools/yosys/techmaps/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/tools/yosys/techmaps/lcu_kogge_stone.v,sha256=M4T-ygiKmlsprl5eGGLaV5w6HVqlEepn0wlUDmOkapg,773
 siliconcompiler/tools/yosys/templates/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/tools/yosys/templates/abc.const,sha256=TAq9ThdLMYCJGrtToEU0gWcLuEtjE4Gk8huBbTm1v-I,116
-siliconcompiler/toolscripts/_tools.json,sha256=jeawsNVi9BJWSeMiIxX0_0mDjv0-WddcU5a_Rm5uPIw,3959
+siliconcompiler/toolscripts/_tools.json,sha256=nc4Ro0ey2i10zpCRSjn1roD8QiwcnY4rRwkkn4GC3GY,3961
 siliconcompiler/toolscripts/_tools.py,sha256=P30KY_xbbjl8eHGsPAxDcAzWvJJpiL07ZfGZZDQbdR8,7174
 siliconcompiler/toolscripts/rhel8/install-chisel.sh,sha256=lPORZN7vlBX6sJSv01JOIiDE9-_7GcCZGA7EP5ri3MQ,525
 siliconcompiler/toolscripts/rhel8/install-ghdl.sh,sha256=xCLeEUuJVI_6PVEvnTwBsTWoEHiQg0TY3x-tJXfg6Zk,459
@@ -412,9 +439,9 @@ siliconcompiler/toolscripts/ubuntu24/install-yosys.sh,sha256=zpyt0MVI7tY8kGY2GII
 siliconcompiler/utils/__init__.py,sha256=6u8A5atgPW7cbC1xrerU67rlOM0FitCgxFIu5F_n5zo,14126
 siliconcompiler/utils/asic.py,sha256=cMLs7dneSmh5BlHS0-bZ1tLUpvghTw__gNaUCMpyBds,4986
 siliconcompiler/utils/showtools.py,sha256=qc5HLqCQxUITdhp9rESf0w_blAkKVYL6JpkXQdrew00,1406
-siliconcompiler-0.28.9.dist-info/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
-siliconcompiler-0.28.9.dist-info/METADATA,sha256=cIK1Z_MCUEI3Zz4VBwApsmfv94-s7Y23x6jvoZ-zKUY,10831
-siliconcompiler-0.28.9.dist-info/WHEEL,sha256=PZUExdf71Ui_so67QXpySuHtCi3-J3wvF4ORK6k_S8U,91
-siliconcompiler-0.28.9.dist-info/entry_points.txt,sha256=TZVS-8akO-8Z1Z1oMjgWryzk_F9dAW74d2ArJV843pg,501
-siliconcompiler-0.28.9.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
-siliconcompiler-0.28.9.dist-info/RECORD,,
+siliconcompiler-0.29.0.dist-info/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
+siliconcompiler-0.29.0.dist-info/METADATA,sha256=aCX3gJqoYrOrEmkz4LHcAVR2foZwz_ainn-xVzSkM1o,10939
+siliconcompiler-0.29.0.dist-info/WHEEL,sha256=PZUExdf71Ui_so67QXpySuHtCi3-J3wvF4ORK6k_S8U,91
+siliconcompiler-0.29.0.dist-info/entry_points.txt,sha256=TZVS-8akO-8Z1Z1oMjgWryzk_F9dAW74d2ArJV843pg,501
+siliconcompiler-0.29.0.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
+siliconcompiler-0.29.0.dist-info/RECORD,,

siliconcompiler/tools/openroad/cts.py

@@ -1,45 +0,0 @@
-
-from siliconcompiler.tools.openroad.openroad import setup as setup_tool
-from siliconcompiler.tools.openroad.openroad import build_pex_corners
-from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
-from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
-from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
-
-
-def setup(chip):
-    '''
-    Perform clock tree synthesis and timing repair
-    '''
-
-    # Generic tool setup.
-    setup_tool(chip)
-
-    set_pnr_inputs(chip)
-    set_pnr_outputs(chip)
-
-    _set_reports(chip, [
-        'setup',
-        'hold',
-        'unconstrained',
-        'clock_skew',
-        'power',
-        'drv_violations',
-        'fmax',
-
-        # Images
-        'placement_density',
-        'routing_congestion',
-        'power_density',
-        'clock_placement',
-        'clock_trees',
-        'optimization_placement'
-    ])
-
-
-def pre_process(chip):
-    or_pre_process(chip)
-    build_pex_corners(chip)
-
-
-def post_process(chip):
-    or_post_process(chip)

siliconcompiler/tools/openroad/floorplan.py

@@ -1,75 +0,0 @@
-from siliconcompiler.tools._common import input_provides, add_common_file, get_tool_task
-from siliconcompiler.tools._common.asic import set_tool_task_var
-from siliconcompiler.tools.openroad.openroad import setup as setup_tool
-from siliconcompiler.tools.openroad.openroad import build_pex_corners
-from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
-from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
-from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
-
-
-def setup(chip):
-    '''
-    Perform floorplanning, pin placements, macro placements and power grid generation
-    '''
-
-    # Generic tool setup.
-    setup_tool(chip)
-
-    tool = 'openroad'
-    design = chip.top()
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
-
-    if chip.valid('input', 'asic', 'floorplan') and \
-       chip.get('input', 'asic', 'floorplan', step=step, index=index):
-        chip.add('tool', tool, 'task', task, 'require',
-                 ",".join(['input', 'asic', 'floorplan']),
-                 step=step, index=index)
-
-    if f'{design}.vg' in input_provides(chip, step, index):
-        chip.add('tool', tool, 'task', task, 'input', design + '.vg',
-                 step=step, index=index)
-    else:
-        chip.add('tool', tool, 'task', task, 'require', 'input,netlist,verilog',
-                 step=step, index=index)
-
-    set_pnr_inputs(chip)
-    set_pnr_outputs(chip)
-
-    if chip.valid('tool', tool, 'task', task, 'file', 'padring') and \
-       chip.get('tool', tool, 'task', task, 'file', 'padring',
-                step=step, index=index):
-        chip.add('tool', tool, 'task', task, 'require',
-                 ','.join(['tool', tool, 'task', task, 'file', 'padring']),
-                 step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'file', 'padring',
-             'script to insert the padring',
-             field='help')
-
-    set_tool_task_var(chip, param_key='remove_synth_buffers',
-                      default_value=True,
-                      schelp='remove buffers inserted by synthesis')
-
-    snap = chip.get('tool', tool, 'task', task, 'var', 'ifp_snap_strategy',
-                    step=step, index=index)[0]
-    snaps_allowed = ('none', 'site', 'manufacturing_grid')
-    if snap not in snaps_allowed:
-        chip.error(f'{snap} is not a supported snapping strategy. Allowed values: {snaps_allowed}')
-
-    add_common_file(chip, 'sc_pin_constraint', 'tcl/sc_pin_constraints.tcl')
-
-    _set_reports(chip, [
-        'setup',
-        'unconstrained',
-        'power'
-    ])
-
-
-def pre_process(chip):
-    or_pre_process(chip)
-    build_pex_corners(chip)
-
-
-def post_process(chip):
-    or_post_process(chip)

siliconcompiler/tools/openroad/physyn.py

@@ -1,27 +0,0 @@
-
-from siliconcompiler.tools.openroad.openroad import setup as setup_tool
-from siliconcompiler.tools.openroad.openroad import build_pex_corners
-from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
-from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
-from siliconcompiler.tools.openroad.openroad import set_pnr_inputs, set_pnr_outputs
-
-
-def setup(chip):
-    '''
-    Not implemented yet
-    '''
-
-    # Generic tool setup.
-    setup_tool(chip)
-
-    set_pnr_inputs(chip)
-    set_pnr_outputs(chip)
-
-
-def pre_process(chip):
-    or_pre_process(chip)
-    build_pex_corners(chip)
-
-
-def post_process(chip):
-    or_post_process(chip)

siliconcompiler/tools/openroad/place.py

@@ -1,41 +0,0 @@
-
-from siliconcompiler.tools.openroad.openroad import setup as setup_tool
-from siliconcompiler.tools.openroad.openroad import build_pex_corners
-from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
-from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
-from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
-
-
-def setup(chip):
-    '''
-    Perform global and detail placements along with design violation repairs
-    '''
-
-    # Generic tool setup.
-    setup_tool(chip)
-
-    set_pnr_inputs(chip)
-    set_pnr_outputs(chip)
-
-    _set_reports(chip, [
-        'setup',
-        'unconstrained',
-        'power',
-        'drv_violations',
-        'fmax',
-
-        # Images
-        'placement_density',
-        'routing_congestion',
-        'power_density',
-        'optimization_placement'
-    ])
-
-
-def pre_process(chip):
-    or_pre_process(chip)
-    build_pex_corners(chip)
-
-
-def post_process(chip):
-    or_post_process(chip)