angr 9.2.117__py3-none-win_amd64.whl → 9.2.119__py3-none-win_amd64.whl

angr/storage/memory_mixins/__init__.pyi

@@ -1,8 +1,7 @@
 import claripy
-from typing import Union, Optional, List
 from angr.state_plugins.sim_action_object import SimActionObject
 
-_Coerce = Union[int, claripy.ast.bv.BV, SimActionObject]
+_Coerce = int | claripy.ast.bv.BV | SimActionObject
 
 class DefaultMemory:
     SUPPORTS_CONCRETE_LOAD: bool
@@ -11,24 +10,24 @@ class DefaultMemory:
     def store(
         self,
         addr: _Coerce,
-        data: Union[_Coerce, bytes],
-        size: Optional[_Coerce] = None,
-        condition: Optional[claripy.ast.bool.Bool] = None,
+        data: _Coerce | bytes,
+        size: _Coerce | None = None,
+        condition: claripy.ast.bool.Bool | None = None,
         **kwargs,
     ) -> None: ...
     def load(
         self,
         addr: _Coerce,
-        size: Optional[_Coerce] = None,
-        condition: Optional[claripy.ast.bool.Bool] = None,
-        fallback: Optional[_Coerce] = None,
+        size: _Coerce | None = None,
+        condition: claripy.ast.bool.Bool | None = None,
+        fallback: _Coerce | None = None,
         **kwargs,
     ) -> claripy.ast.bv.BV: ...
     def find(
-        self, addr: _Coerce, what: _Coerce, max_search: int, default: Optional[_Coerce] = None, **kwargs
+        self, addr: _Coerce, what: _Coerce, max_search: int, default: _Coerce | None = None, **kwargs
     ) -> claripy.ast.bv.BV: ...
     def copy_contents(
-        self, dst: _Coerce, src: _Coerce, size: _Coerce, condition: Optional[claripy.ast.bool.Bool] = None, **kwargs
+        self, dst: _Coerce, src: _Coerce, size: _Coerce, condition: claripy.ast.bool.Bool | None = None, **kwargs
     ) -> None: ...
     def copy(self, memo: dict) -> DefaultMemory: ...
     @property
@@ -37,11 +36,11 @@ class DefaultMemory:
     def variable_key_prefix(self) -> str: ...
     def merge(
         self,
-        others: List[DefaultMemory],
-        merge_conditions: List[claripy.ast.bool.Bool],
-        common_ancestor: Optional[DefaultMemory] = ...,
+        others: list[DefaultMemory],
+        merge_conditions: list[claripy.ast.bool.Bool],
+        common_ancestor: DefaultMemory | None = ...,
     ) -> bool: ...
-    def permissions(self, addr: _Coerce, permissions: Optional[_Coerce] = ..., **kwargs) -> None: ...
+    def permissions(self, addr: _Coerce, permissions: _Coerce | None = ..., **kwargs) -> None: ...
     def map_region(self, addr: _Coerce, length: int, permissions: _Coerce, init_zero: bool = ..., **kwargs) -> None: ...
     def unmap_region(self, addr: _Coerce, length: int, **kwargs) -> None: ...
     def concrete_load(self, addr: _Coerce, size: int, writing: bool = ..., **kwargs) -> memoryview: ...

angr/storage/memory_mixins/actions_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import claripy
 
 from ...state_plugins.sim_action import SimActionData, SimActionObject
@@ -45,7 +46,7 @@ class ActionsMixinHigh(MemoryMixin):
             self.state, region_type, kind, addr=addr, data=data, size=ref_size, condition=condition, fallback=fallback
         )
 
-        action.added_constraints = claripy.true
+        action.added_constraints = claripy.true()
         return action
 
     def _add_constraints(self, c, action=None, **kwargs):

angr/storage/memory_mixins/address_concretization_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import claripy
 
 from . import MemoryMixin
@@ -183,7 +184,7 @@ class AddressConcretizationMixin(MemoryMixin):
                 return a
 
         # well, we tried
-        raise SimMemoryAddressError("Unable to concretize address for %s with the provided strategies." % action)
+        raise SimMemoryAddressError(f"Unable to concretize address for {action} with the provided strategies.")
 
     def concretize_write_addr(self, addr, strategies=None, condition=None):
         """
@@ -197,7 +198,7 @@ class AddressConcretizationMixin(MemoryMixin):
 
         if isinstance(addr, int):
             return [addr]
-        elif not self.state.solver.symbolic(addr):
+        if not self.state.solver.symbolic(addr):
             return [self.state.solver.eval(addr)]
 
         strategies = self.write_strategies if strategies is None else strategies
@@ -214,7 +215,7 @@ class AddressConcretizationMixin(MemoryMixin):
 
         if isinstance(addr, int):
             return [addr]
-        elif not self.state.solver.symbolic(addr):
+        if not self.state.solver.symbolic(addr):
             return [self.state.solver.eval(addr)]
 
         strategies = self.read_strategies if strategies is None else strategies
@@ -254,8 +255,7 @@ class AddressConcretizationMixin(MemoryMixin):
 
         if read_value is None:
             return sub_value
-        else:
-            return claripy.If(addr == concrete_addr, sub_value, read_value)
+        return claripy.If(addr == concrete_addr, sub_value, read_value)
 
     def load(self, addr, size=None, condition=None, **kwargs):
         if type(size) is not int:
@@ -264,7 +264,7 @@ class AddressConcretizationMixin(MemoryMixin):
         # Fast path
         if type(addr) is int:
             return self._load_one_addr(addr, True, addr, condition, size, read_value=None, **kwargs)
-        elif not self.state.solver.symbolic(addr):
+        if not self.state.solver.symbolic(addr):
             return self._load_one_addr(
                 self.state.solver.eval(addr), True, addr, condition, size, read_value=None, **kwargs
             )
@@ -277,8 +277,7 @@ class AddressConcretizationMixin(MemoryMixin):
         except SimMemoryError:
             if options.CONSERVATIVE_READ_STRATEGY in self.state.options:
                 return self._default_value(None, size, name="symbolic_read_unconstrained", **kwargs)
-            else:
-                raise
+            raise
 
         # quick optimization so as to not involve the solver if not necessary
         trivial = len(concrete_addrs) == 1 and (addr == concrete_addrs[0]).is_true()
@@ -289,10 +288,8 @@ class AddressConcretizationMixin(MemoryMixin):
             self._add_constraints(conditional_constraint, condition=condition, **kwargs)
 
         # quick optimization to not introduce the DUMMY value if there's only one loop
-        if len(concrete_addrs) == 1:
-            read_value = None
-        else:
-            read_value = DUMMY_SYMBOLIC_READ_VALUE  # this is a sentinel value and should never be touched
+        # DUMMY_SYMBOLIC_READ_VALUE is a sentinel value and should never be touched
+        read_value = None if len(concrete_addrs) == 1 else DUMMY_SYMBOLIC_READ_VALUE
 
         for concrete_addr in concrete_addrs:
             # perform each of the loads
@@ -317,7 +314,7 @@ class AddressConcretizationMixin(MemoryMixin):
         if type(addr) is int:
             self._store_one_addr(addr, data, True, addr, condition, size, **kwargs)
             return
-        elif not self.state.solver.symbolic(addr):
+        if not self.state.solver.symbolic(addr):
             self._store_one_addr(self.state.solver.eval(addr), data, True, addr, condition, size, **kwargs)
             return
 
@@ -330,8 +327,7 @@ class AddressConcretizationMixin(MemoryMixin):
         except SimMemoryError:
             if options.CONSERVATIVE_WRITE_STRATEGY in self.state.options:
                 return  # not completed
-            else:
-                raise
+            raise
 
         # quick optimization so as to not involve the solver if not necessary
         trivial = len(concrete_addrs) == 1 and (addr == concrete_addrs[0]).is_true()

angr/storage/memory_mixins/bvv_conversion_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 import claripy
 
@@ -50,25 +51,23 @@ class DataNormalizationMixin(MemoryMixin):
             thing = thing.encode("utf-8")
         if type(thing) in (bytes, bytearray, memoryview):
             return claripy.BVV(thing)
-        elif type(thing) is int:
+        if type(thing) is int:
             if bits is None:
                 l.warning("Unknown size for memory data %#x. Default to arch.bits.", thing)
                 bits = self.state.arch.bits
             return claripy.BVV(thing, bits)
-        elif type(thing) is float:
+        if type(thing) is float:
             if bits == 32:
                 return claripy.FPV(thing, claripy.FSORT_FLOAT).raw_to_bv()
-            elif bits == 64:
+            if bits == 64:
                 return claripy.FPV(thing, claripy.FSORT_DOUBLE).raw_to_bv()
-            else:
-                raise TypeError("Passed float size which is not a float or a double", size)
+            raise TypeError("Passed float size which is not a float or a double", size)
+        try:
+            raw_to_bv = thing.raw_to_bv
+        except AttributeError:
+            raise TypeError("Bad value passed to memory", thing) from None
         else:
-            try:
-                raw_to_bv = thing.raw_to_bv
-            except AttributeError:
-                raise TypeError("Bad value passed to memory", thing) from None
-            else:
-                return raw_to_bv()
+            return raw_to_bv()
 
 
 from ...errors import SimMemoryError

angr/storage/memory_mixins/clouseau_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from . import MemoryMixin
 
 

angr/storage/memory_mixins/conditional_store_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import claripy
 
 from . import MemoryMixin

angr/storage/memory_mixins/convenient_mappings_mixin.py

@@ -1,4 +1,5 @@
 # pylint:disable=arguments-differ,assignment-from-no-return,isinstance-second-argument-not-valid-type
+from __future__ import annotations
 import logging
 
 import claripy
@@ -62,7 +63,7 @@ class ConvenientMappingsMixin(MemoryMixin):
                         self._updated_mappings.remove((v, id(self._name_mapping)))
 
                 if options.REVERSE_MEMORY_HASH_MAP in self.state.options:
-                    h = old_obj.cache_key
+                    h = old_obj.hash()
                     self._mark_updated_mapping(self._hash_mapping, h)
                     self._hash_mapping[h].difference_update(range(addr, addr + size))
                     if len(self._hash_mapping[h]) == 0:
@@ -81,7 +82,7 @@ class ConvenientMappingsMixin(MemoryMixin):
 
         if options.REVERSE_MEMORY_HASH_MAP in self.state.options:
             # add the new variables to the hash->addrs mapping
-            h = data.cache_key
+            h = data.hash()
             self._mark_updated_mapping(self._hash_mapping, h)
             if h not in self._hash_mapping:
                 self._hash_mapping[h] = set()
@@ -147,7 +148,7 @@ class ConvenientMappingsMixin(MemoryMixin):
                         self._name_mapping.pop(v, None)
 
             if options.REVERSE_MEMORY_HASH_MAP in self.state.options:
-                h = hash(old_obj)
+                h = old_obj.hash()
                 self._mark_updated_mapping(self._hash_mapping, h)
                 self._hash_mapping[h].discard(actual_addr)
                 if len(self._hash_mapping[h]) == 0:
@@ -165,7 +166,7 @@ class ConvenientMappingsMixin(MemoryMixin):
 
         if options.REVERSE_MEMORY_HASH_MAP in self.state.options:
             # add the new variables to the hash->addrs mapping
-            h = hash(new_obj)
+            h = new_obj.hash()
             self._mark_updated_mapping(self._hash_mapping, h)
             if h not in self._hash_mapping:
                 self._hash_mapping[h] = set()
@@ -207,10 +208,8 @@ class ConvenientMappingsMixin(MemoryMixin):
         for e in self._hash_mapping[h]:
             try:
                 present = self.load(e, size=1)
-                if h == present.cache_key or (
-                    present.op == "Extract"
-                    and present.args[0] - present.args[1] == 7
-                    and h == present.args[2].cache_key
+                if h == present.hash() or (
+                    present.op == "Extract" and present.args[0] - present.args[1] == 7 and h == present.args[2].hash()
                 ):
                     yield e
                 else:

angr/storage/memory_mixins/default_filler_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 
 import claripy
@@ -25,11 +26,14 @@ class DefaultFillerMixin(MemoryMixin):
 
         bits = size * self.state.arch.byte_width
 
-        if type(addr) is int:
-            if self.category == "mem" and options.ZERO_FILL_UNCONSTRAINED_MEMORY in self.state.options:
-                return claripy.BVV(0, bits)
-            elif self.category == "reg" and options.ZERO_FILL_UNCONSTRAINED_REGISTERS in self.state.options:
-                return claripy.BVV(0, bits)
+        if (
+            type(addr) is int
+            and self.category == "mem"
+            and options.ZERO_FILL_UNCONSTRAINED_MEMORY in self.state.options
+            or self.category == "reg"
+            and options.ZERO_FILL_UNCONSTRAINED_REGISTERS in self.state.options
+        ):
+            return claripy.BVV(0, bits)
 
         if self.category == "reg" and type(addr) is int and addr == self.state.arch.ip_offset:
             # short-circuit this pathological case
@@ -101,14 +105,9 @@ class DefaultFillerMixin(MemoryMixin):
                     name = "reg_" + reg_str
 
         if name is None:
-            if type(addr) is int:
-                name = f"{self.id}_{addr:x}"
-            else:
-                name = self.category
-
-        r = self.state.solver.Unconstrained(name, bits, key=key, inspect=inspect, events=events)
+            name = f"{self.id}_{addr:x}" if type(addr) is int else self.category
 
-        return r
+        return self.state.solver.Unconstrained(name, bits, key=key, inspect=inspect, events=events)
 
 
 class SpecialFillerMixin(MemoryMixin):
@@ -139,8 +138,7 @@ class ExplicitFillerMixin(MemoryMixin):
     def _default_value(self, addr, size, inspect=True, events=True, **kwargs):
         if self._uninitialized_read_handler is not None:
             return self._uninitialized_read_handler(addr, size, inspect=inspect, events=events)
-        else:
-            return super()._default_value(addr, size, inspect=inspect, events=events, **kwargs)
+        return super()._default_value(addr, size, inspect=inspect, events=events, **kwargs)
 
     def copy(self, memo):
         o = super().copy(memo)

angr/storage/memory_mixins/dirty_addrs_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from . import MemoryMixin
 
 

angr/storage/memory_mixins/hex_dumper_mixin.py

@@ -1,7 +1,9 @@
+from __future__ import annotations
 import string
 
 from ...errors import SimValueError
 from . import MemoryMixin
+import contextlib
 
 
 class HexDumperMixin(MemoryMixin):
@@ -40,10 +42,7 @@ class HexDumperMixin(MemoryMixin):
         :param disable_actions: whether or not to disable SimActions for the memory load
         :return: hex dump as a string
         """
-        if endianness == "Iend_BE":
-            end = 1
-        else:
-            end = -1
+        end = 1 if endianness == "Iend_BE" else -1
         if extra_constraints is None:
             extra_constraints = []
 
@@ -55,7 +54,7 @@ class HexDumperMixin(MemoryMixin):
         i = start
         dump_str = ""
         for line in raw_mem.chop(line_size * self.state.arch.byte_width):
-            dump = "%x:" % i
+            dump = f"{i:x}:"
             group_str = ""
             for word in line.chop(word_size * self.state.arch.byte_width):
                 word_bytes = ""
@@ -63,13 +62,11 @@ class HexDumperMixin(MemoryMixin):
                 for byte_ in word.chop(self.state.arch.byte_width)[::end]:
                     byte_value = None
                     if not self.state.solver.symbolic(byte_) or solve:
-                        try:
+                        with contextlib.suppress(SimValueError):
                             byte_value = self.state.solver.eval_one(byte_, extra_constraints=extra_constraints)
-                        except SimValueError:
-                            pass
 
                     if byte_value is not None:
-                        word_bytes += "%02x" % byte_value
+                        word_bytes += f"{byte_value:02x}"
                         if chr(byte_value) in string.printable[:-5]:
                             word_str += chr(byte_value)
                         else:

angr/storage/memory_mixins/javavm_memory/__init__.py

@@ -1 +1,2 @@
+from __future__ import annotations
 from .javavm_memory_mixin import JavaVmMemoryMixin

angr/storage/memory_mixins/javavm_memory/javavm_memory_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import binascii
 import logging
 import os
@@ -64,11 +65,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         return binascii.hexlify(os.urandom(4))
 
     def store(self, addr, data, frame=0):  # pylint: disable=arguments-differ
-        if type(addr) is SimSootValue_Local:
-            cstack = self._stack[-1 + (-1 * frame)]
-            cstack.store(addr.id, data, type_=addr.type)
-
-        elif type(addr) is SimSootValue_ParamRef:
+        if type(addr) is SimSootValue_Local or type(addr) is SimSootValue_ParamRef:
             cstack = self._stack[-1 + (-1 * frame)]
             cstack.store(addr.id, data, type_=addr.type)
 
@@ -78,10 +75,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         elif type(addr) is SimSootValue_StaticFieldRef:
             self.vm_static_table.store(addr.id, data, type_=addr.type)
 
-        elif type(addr) is SimSootValue_InstanceFieldRef:
-            self.heap.store(addr.id, data, type_=addr.type)
-
-        elif type(addr) is SimSootValue_StringRef:
+        elif type(addr) is SimSootValue_InstanceFieldRef or type(addr) is SimSootValue_StringRef:
             self.heap.store(addr.id, data, type_=addr.type)
 
         else:
@@ -92,14 +86,14 @@ class JavaVmMemoryMixin(MemoryMixin):
             cstack = self._stack[-1 + (-1 * frame)]
             return cstack.load(addr.id, none_if_missing=none_if_missing)
 
-        elif type(addr) is SimSootValue_ArrayRef:
+        if type(addr) is SimSootValue_ArrayRef:
             return self.load_array_element(addr.base, addr.index)
 
-        elif type(addr) is SimSootValue_ParamRef:
+        if type(addr) is SimSootValue_ParamRef:
             cstack = self._stack[-1 + (-1 * frame)]
             return cstack.load(addr.id, none_if_missing=none_if_missing)
 
-        elif type(addr) is SimSootValue_StaticFieldRef:
+        if type(addr) is SimSootValue_StaticFieldRef:
             value = self.vm_static_table.load(addr.id, none_if_missing=none_if_missing)
             if value is None:
                 # initialize field
@@ -108,7 +102,7 @@ class JavaVmMemoryMixin(MemoryMixin):
                 self.store(addr, value)
             return value
 
-        elif type(addr) is SimSootValue_InstanceFieldRef:
+        if type(addr) is SimSootValue_InstanceFieldRef:
             value = self.heap.load(addr.id, none_if_missing=none_if_missing)
             if value is None:
                 # initialize field
@@ -117,12 +111,11 @@ class JavaVmMemoryMixin(MemoryMixin):
                 self.store(addr, value)
             return value
 
-        elif type(addr) is SimSootValue_StringRef:
+        if type(addr) is SimSootValue_StringRef:
             return self.heap.load(addr.id, none_if_missing=none_if_missing)
 
-        else:
-            l.error("Unknown addr type %s", addr)
-            return None
+        l.error("Unknown addr type %s", addr)
+        return None
 
     def push_stack_frame(self):
         from .. import KeyValueMemory
@@ -176,7 +169,7 @@ class JavaVmMemoryMixin(MemoryMixin):
             start_idx_options = []
             for concrete_start_idx in concrete_start_idxes:
                 start_idx_options.append(concrete_start_idx == start_idx)
-                # we store elements condtioned with the start index:
+                # we store elements conditioned with the start index:
                 # => if concrete_start_idx == start_idx
                 #    then store the value
                 #    else keep the current value
@@ -299,7 +292,7 @@ class JavaVmMemoryMixin(MemoryMixin):
             if idxes:
                 return idxes
 
-        raise SimMemoryAddressError("Unable to concretize index %s" % idx)
+        raise SimMemoryAddressError(f"Unable to concretize index {idx}")
 
     def concretize_store_idx(self, idx, strategies=None):
         """
@@ -313,7 +306,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         """
         if isinstance(idx, int):
             return [idx]
-        elif not self.state.solver.symbolic(idx):
+        if not self.state.solver.symbolic(idx):
             return [self.state.solver.eval(idx)]
 
         strategies = self.store_strategies if strategies is None else strategies
@@ -331,7 +324,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         """
         if isinstance(idx, int):
             return [idx]
-        elif not self.state.solver.symbolic(idx):
+        if not self.state.solver.symbolic(idx):
             return [self.state.solver.eval(idx)]
 
         strategies = self.load_strategies if strategies is None else strategies
@@ -374,7 +367,7 @@ class JavaVmMemoryMixin(MemoryMixin):
 
     @MemoryMixin.memo
     def copy(self, memo):
-        o: "JavaVmMemoryMixin" = super().copy(memo)
+        o: JavaVmMemoryMixin = super().copy(memo)
         o._stack = [stack_frame.copy() for stack_frame in self._stack]
         o.heap = self.heap.copy()
         o.vm_static_table = self.vm_static_table.copy()
@@ -393,4 +386,4 @@ class JavaVmMemoryMixin(MemoryMixin):
         self, addr, what, max_search=None, max_symbolic_bytes=None, default=None
     ):  # pylint: disable=unused-argument
         l.warning("Find is not implemented for JavaVM memory!")
-        return None
+        return

angr/storage/memory_mixins/keyvalue_memory/__init__.py

@@ -1 +1,2 @@
+from __future__ import annotations
 from .keyvalue_memory_mixin import KeyValueMemoryMixin

angr/storage/memory_mixins/keyvalue_memory/keyvalue_memory_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from .. import MemoryMixin
 
 
@@ -28,7 +29,7 @@ class KeyValueMemoryMixin(MemoryMixin):
 
     @MemoryMixin.memo
     def copy(self, memo):
-        o: "KeyValueMemoryMixin" = super().copy(memo)
+        o: KeyValueMemoryMixin = super().copy(memo)
         o._store = self._store.copy()
         return o
 

angr/storage/memory_mixins/label_merger_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from collections.abc import Iterable
 
 from . import MemoryMixin
@@ -27,5 +28,4 @@ class LabelMergerMixin(MemoryMixin):
         return new_label
 
     def copy(self, memo=None):
-        copied = super().copy(memo)
-        return copied
+        return super().copy(memo)

angr/storage/memory_mixins/multi_value_merger_mixin.py

@@ -1,4 +1,5 @@
 # pylint:disable=missing-class-docstring
+from __future__ import annotations
 from typing import Any
 from collections.abc import Iterable, Callable
 
@@ -40,16 +41,16 @@ class MultiValueMergerMixin(MemoryMixin):
                 ret_val = self._top_func(merged_size * self.state.arch.byte_width)
             else:
                 # strip annotations from each value and see how many raw values there are in total
-                # We have to use cache_key to determine uniqueness here, because if __hash__ collides,
+                # We have to use hash manually to determine uniqueness here, because if __hash__ collides,
                 # python implicitly calls __eq__ to determine if the two objects are actually the same
                 # and that just results in a new AST for a BV. Python then tries to convert that AST to a bool
                 # which fails with the safeguard in claripy.ast.bool.Bool.__bool__.
-                stripped_values_set = {v.clear_annotations().cache_key for v in values_set}
-                if len(stripped_values_set) > 1:
+                stripped_values_dict = {v.hash(): v for v in values_set}
+                if len(stripped_values_dict) > 1:
                     ret_val = self._top_func(merged_size * self.state.arch.byte_width)
                 else:
-                    # Get the AST back from the cache_key
-                    ret_val = next(iter(stripped_values_set)).ast
+                    # Get the AST back from the hash dict
+                    ret_val = stripped_values_dict[next(iter(stripped_values_dict))]
 
             # migrate annotations
             annotations = []

angr/storage/memory_mixins/name_resolution_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import claripy
 from archinfo.arch_arm import is_arm_arch
 from . import MemoryMixin
@@ -22,20 +23,19 @@ class NameResolutionMixin(MemoryMixin):
                     return (((stn_map[name] + self.load("ftop")) & 7) << 3) + self.state.arch.registers["fpu_regs"][
                         0
                     ], 8
-                elif name in tag_map:
+                if name in tag_map:
                     return ((tag_map[name] + self.load("ftop")) & 7) + self.state.arch.registers["fpu_tags"][0], 1
-                elif name in ("flags", "eflags", "rflags"):
+                if name in ("flags", "eflags", "rflags"):
                     # we tweak the state to convert the vex condition registers into the flags register
                     if not is_write:  # this work doesn't need to be done if we're just gonna overwrite it
                         self.store("cc_dep1", _get_flags(self.state))  # constraints cannot be added by this
                     self.store("cc_op", 0)  # OP_COPY
                     return self.state.arch.registers["cc_dep1"]
-            if is_arm_arch(self.state.arch):
-                if name == "flags":
-                    if not is_write:
-                        self.store("cc_dep1", _get_flags(self.state))
-                    self.store("cc_op", 0)
-                    return self.state.arch.registers["cc_dep1"]
+            if is_arm_arch(self.state.arch) and name == "flags":
+                if not is_write:
+                    self.store("cc_dep1", _get_flags(self.state))
+                self.store("cc_op", 0)
+                return self.state.arch.registers["cc_dep1"]
 
             if name == "sp" and "sp" not in self.state.arch.registers:
                 sp_reg_name = self.state.arch.register_names[self.state.arch.sp_offset]
@@ -45,10 +45,9 @@ class NameResolutionMixin(MemoryMixin):
                 return self.state.arch.registers[lr_reg_name]
 
             return self.state.arch.registers[name]
-        elif name[0] == "*":
+        if name[0] == "*":
             return self.state.registers.load(name[1:]), None
-        else:
-            raise SimMemoryError("Trying to address memory with a register name.")
+        raise SimMemoryError("Trying to address memory with a register name.")
 
     def store(self, addr, data, size=None, **kwargs):
         if isinstance(addr, str):
@@ -56,15 +55,13 @@ class NameResolutionMixin(MemoryMixin):
             if isinstance(data, claripy.ast.BV) and len(data) < named_size * self.state.arch.byte_width:
                 data = data.zero_extend(named_size * self.state.arch.byte_width - len(data))
             return super().store(named_addr, data, size=named_size if size is None else size, **kwargs)
-        else:
-            return super().store(addr, data, size=size, **kwargs)
+        return super().store(addr, data, size=size, **kwargs)
 
     def load(self, addr, size=None, **kwargs):
         if isinstance(addr, str):
             named_addr, named_size = self._resolve_location_name(addr, is_write=False)
             return super().load(named_addr, size=named_size if size is None else size, **kwargs)
-        else:
-            return super().load(addr, size=size, **kwargs)
+        return super().load(addr, size=size, **kwargs)
 
 
 from ...errors import SimMemoryError