angr 9.2.117__py3-none-win_amd64.whl → 9.2.119__py3-none-win_amd64.whl

angr/simos/linux.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import os
 import logging
 import struct
@@ -94,11 +95,10 @@ class SimLinux(SimUserland):
 
             # TODO: what the hell is this
             _rtld_global_ro = self.project.loader.find_symbol("_rtld_global_ro")
-            if _rtld_global_ro is not None:
-                if isinstance(self.project.arch, ArchAMD64):
-                    self.project.loader.memory.pack_word(
-                        _rtld_global_ro.rebased_addr + 0x0D0, 2
-                    )  # cpu features: kind = amd
+            if _rtld_global_ro is not None and isinstance(self.project.arch, ArchAMD64):
+                self.project.loader.memory.pack_word(
+                    _rtld_global_ro.rebased_addr + 0x0D0, 2
+                )  # cpu features: kind = amd
 
             try:
                 tls_obj = self.project.loader.tls.new_thread()
@@ -150,37 +150,39 @@ class SimLinux(SimUserland):
 
         super().configure_project(syscall_abis)
 
-        if not self._is_core:
-            # Only set up ifunc resolution if we are using the ELF backend on AMD64
-            if isinstance(self.project.loader.main_object, MetaELF):
-                if isinstance(self.project.arch, (ArchAMD64, ArchX86)):
-                    for binary in self.project.loader.all_objects:
-                        if not isinstance(binary, MetaELF):
+        # Only set up ifunc resolution if we are using the ELF backend on AMD64
+        if (
+            not self._is_core
+            and isinstance(self.project.loader.main_object, MetaELF)
+            and isinstance(self.project.arch, (ArchAMD64, ArchX86))
+        ):
+            for binary in self.project.loader.all_objects:
+                if not isinstance(binary, MetaELF):
+                    continue
+                for reloc in binary.relocs:
+                    if reloc.symbol is None or reloc.resolvedby is None:
+                        continue
+                    try:
+                        if reloc.resolvedby.subtype != ELFSymbolType.STT_GNU_IFUNC:
                             continue
-                        for reloc in binary.relocs:
-                            if reloc.symbol is None or reloc.resolvedby is None:
-                                continue
-                            try:
-                                if reloc.resolvedby.subtype != ELFSymbolType.STT_GNU_IFUNC:
-                                    continue
-                            except ValueError:  # base class Symbol throws this, meaning we don't have an ELFSymbol, etc
-                                continue
-                            gotaddr = reloc.rebased_addr
-                            gotvalue = self.project.loader.memory.unpack_word(gotaddr)
-                            if self.project.is_hooked(gotvalue):
-                                continue
-                            if self.project._eager_ifunc_resolution:
-                                # Resolve it!
-                                resolver = self.project.factory.callable(gotvalue, "void *x()", concrete_only=True)
-                                result = resolver().concrete_value
-                                self.project.loader.memory.pack_word(gotaddr, result)
-                            else:
-                                # Replace it with an ifunc-resolve simprocedure!
-                                proc = P["linux_loader"]["IFuncResolver"](
-                                    display_name="IFuncResolver." + reloc.symbol.name,
-                                    funcaddr=gotvalue,
-                                )
-                                self.project.hook(gotvalue, proc, replace=True)
+                    except ValueError:  # base class Symbol throws this, meaning we don't have an ELFSymbol, etc
+                        continue
+                    gotaddr = reloc.rebased_addr
+                    gotvalue = self.project.loader.memory.unpack_word(gotaddr)
+                    if self.project.is_hooked(gotvalue):
+                        continue
+                    if self.project._eager_ifunc_resolution:
+                        # Resolve it!
+                        resolver = self.project.factory.callable(gotvalue, "void *x()", concrete_only=True)
+                        result = resolver().concrete_value
+                        self.project.loader.memory.pack_word(gotaddr, result)
+                    else:
+                        # Replace it with an ifunc-resolve simprocedure!
+                        proc = P["linux_loader"]["IFuncResolver"](
+                            display_name="IFuncResolver." + reloc.symbol.name,
+                            funcaddr=gotvalue,
+                        )
+                        self.project.hook(gotvalue, proc, replace=True)
 
     def syscall_abi(self, state):
         if state.arch.name != "AMD64":
@@ -191,10 +193,9 @@ class SimLinux(SimUserland):
             jk = state.history.parent.jumpkind
         if jk == "Ijk_Sys_int128":
             return "i386"
-        elif jk == "Ijk_Sys_syscall":
+        if jk == "Ijk_Sys_syscall":
             return "amd64"
-        else:
-            raise AngrSyscallError("Unknown syscall jumpkind %s" % jk)
+        raise AngrSyscallError(f"Unknown syscall jumpkind {jk}")
 
     # pylint: disable=arguments-differ
     def state_blank(
@@ -237,29 +238,23 @@ class SimLinux(SimUserland):
                 fs[name] = fs[name].encode("utf-8")
             if type(fs[name]) is bytes:
                 fs[name] = claripy.BVV(fs[name])
-            if isinstance(fs[name], claripy.Bits):
+            if isinstance(fs[name], claripy.ast.Bits):
                 fs[name] = SimFile(name, content=fs[name])
             if not isinstance(fs[name], SimFileBase):
-                raise TypeError("Provided fs initializer with unusable type %r" % type(fs[name]))
+                raise TypeError(f"Provided fs initializer with unusable type {type(fs[name])!r}")
 
         mounts = {}
         if concrete_fs:
             if fs:
                 raise TypeError("Providing both fs and concrete_fs doesn't make sense")
-            if chroot is not None:
-                chroot = os.path.abspath(chroot)
-            else:
-                chroot = os.path.sep
+            chroot = os.path.abspath(chroot) if chroot is not None else os.path.sep
             mounts[pathsep] = SimHostFilesystem(chroot)
             if cwd is None:
                 cwd = os.getcwd()
 
                 if chroot != os.path.sep:
                     # try to translate the cwd into the chroot
-                    if cwd.startswith(chroot):
-                        cwd = cwd[len(chroot) :]
-                    else:
-                        cwd = os.path.sep
+                    cwd = cwd[len(chroot) :] if cwd.startswith(chroot) else os.path.sep
                 cwd = cwd.encode()
         else:
             if cwd is None:
@@ -305,7 +300,7 @@ class SimLinux(SimUserland):
         # Prepare the auxiliary vector and add it to the end of the string table
         # TODO: Actually construct a real auxiliary vector
         # current vector is an AT_RANDOM entry where the "random" value is 0xaec0aec0aec0...
-        aux = [(25, b"\xAE\xC0" * 8)]
+        aux = [(25, b"\xae\xc0" * 8)]
         for a, b in aux:
             table.add_pointer(a)
             if isinstance(b, bytes):
@@ -324,10 +319,7 @@ class SimLinux(SimUserland):
 
         # Put argc on stack and fix the stack pointer
         newsp = argv - state.arch.bytes
-        if len(argc) < state.arch.bits:
-            argc_bvv = claripy.ZeroExt(state.arch.bits - len(argc), argc)
-        else:
-            argc_bvv = argc
+        argc_bvv = claripy.ZeroExt(state.arch.bits - len(argc), argc) if len(argc) < state.arch.bits else argc
         state.memory.store(newsp, argc_bvv, endness=state.arch.memory_endness)
         state.regs.sp = newsp
 
@@ -355,11 +347,10 @@ class SimLinux(SimUserland):
                 byte = state.mem[progname_cur].byte.resolved
                 if byte.symbolic:
                     break
-                else:
-                    if state.solver.eval(byte) == ord("/"):
-                        progname = progname_cur + 1
-                    elif state.solver.eval(byte) == 0:
-                        break
+                if state.solver.eval(byte) == ord("/"):
+                    progname = progname_cur + 1
+                elif state.solver.eval(byte) == 0:
+                    break
 
                 progname_cur += 1
 
@@ -441,10 +432,9 @@ class SimLinux(SimUserland):
                 AT.from_mva(pseudo_toc, self.project.loader.extern_object).to_rva(), pseudo_hookaddr
             )
             return pseudo_hookaddr, pseudo_toc
-        else:
-            if basic_addr is None:
-                basic_addr = self.project.loader.extern_object.get_pseudo_addr(symbol_name)
-            return basic_addr, basic_addr
+        if basic_addr is None:
+            basic_addr = self.project.loader.extern_object.get_pseudo_addr(symbol_name)
+        return basic_addr, basic_addr
 
     def initialize_segment_register_x64(self, state, concrete_target):
         """
@@ -489,7 +479,7 @@ class SimLinux(SimUserland):
         # register used to read the value of the segment register
         exfiltration_reg = "rax"
         # instruction to inject for reading the value at segment value = offset
-        read_fs0_x64 = b"\x64\x48\x8B\x04\x25\x00\x00\x00\x00\x90\x90\x90\x90"  # mov rax, fs:[0]
+        read_fs0_x64 = b"\x64\x48\x8b\x04\x25\x00\x00\x00\x00\x90\x90\x90\x90"  # mov rax, fs:[0]
 
         return concrete_target.execute_shellcode(read_fs0_x64, exfiltration_reg)
 
@@ -504,7 +494,7 @@ class SimLinux(SimUserland):
         # register used to read the value of the segment register
         exfiltration_reg = "eax"
         # instruction to inject for reading the value at segment value = offset
-        read_gs0_x64 = b"\x65\xA1\x00\x00\x00\x00\x90\x90\x90\x90"  # mov eax, gs:[0]
+        read_gs0_x64 = b"\x65\xa1\x00\x00\x00\x00\x90\x90\x90\x90"  # mov eax, gs:[0]
         return concrete_target.execute_shellcode(read_gs0_x64, exfiltration_reg)
 
     def get_segment_register_name(self):

angr/simos/simos.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 import struct
 
@@ -26,7 +27,7 @@ class SimOS:
     A class describing OS/arch-level configuration.
     """
 
-    def __init__(self, project: "angr.Project", name=None):
+    def __init__(self, project: angr.Project, name=None):
         self.arch = project.arch
         self.project = project
         self.name = name
@@ -62,11 +63,8 @@ class SimOS:
                 resolver_addr, concrete_only=True, base_state=base_state, prototype=prototype
             )
             try:
-                if isinstance(self.arch, ArchS390X):
-                    # On s390x ifunc resolvers expect hwcaps.
-                    val = resolver(0)
-                else:
-                    val = resolver()
+                # On s390x ifunc resolvers expect hwcaps.
+                val = resolver(0) if isinstance(self.arch, ArchS390X) else resolver()
             except AngrCallableMultistateError:
                 _l.error("Resolver at %#x failed to resolve! (multivalued)", resolver_addr)
                 return None
@@ -79,16 +77,12 @@ class SimOS:
         self.project.loader.perform_irelative_relocs(irelative_resolver)
 
     def _weak_hook_symbol(self, name, hook, scope=None):
-        if scope is None:
-            sym = self.project.loader.find_symbol(name)
-        else:
-            sym = scope.get_symbol(name)
+        sym = self.project.loader.find_symbol(name) if scope is None else scope.get_symbol(name)
 
         if sym is not None:
             addr, _ = self.prepare_function_symbol(name, basic_addr=sym.rebased_addr)
-            if self.project.is_hooked(addr):
-                if not self.project.hooked_by(addr).is_stub:
-                    return
+            if self.project.is_hooked(addr) and not self.project.hooked_by(addr).is_stub:
+                return
             self.project.hook(addr, hook)
 
     def state_blank(
@@ -146,10 +140,8 @@ class SimOS:
                         perms |= 4  # PROT_EXEC
                     permission_map[(seg.min_addr, seg.max_addr)] = perms
             kwargs["permissions_map"] = permission_map
-        if self.project.loader.main_object.execstack:
-            stack_perms = 1 | 2 | 4  # RWX
-        else:
-            stack_perms = 1 | 2  # RW
+        # RWX or RW
+        stack_perms = 1 | 2 | 4 if self.project.loader.main_object.execstack else 1 | 2
 
         state = SimState(self.project, stack_end=stack_end, stack_size=stack_size, stack_perms=stack_perms, **kwargs)
 
@@ -157,7 +149,7 @@ class SimOS:
             if type(stdin) is type:
                 stdin = stdin(name="stdin", has_end=False)
             else:
-                if isinstance(stdin, claripy.Bits):
+                if isinstance(stdin, claripy.ast.Bits):
                     num_bytes = len(stdin) // self.project.arch.byte_width
                 else:
                     num_bytes = len(stdin)
@@ -178,7 +170,7 @@ class SimOS:
             for reg in state.arch.default_symbolic_registers:
                 state.registers.store(
                     reg,
-                    claripy.BVS(
+                    state.solver.BVS(
                         initial_prefix + "_" + reg, state.arch.bits, explicit_name=True, key=("reg", reg), eternal=True
                     ),
                 )
@@ -197,7 +189,7 @@ class SimOS:
                     # Backward compatibility
                     region_base = 0
                 else:
-                    raise AngrSimOSError('You must specify the base address for memory region "%s". ' % mem_region)
+                    raise AngrSimOSError(f'You must specify the base address for memory region "{mem_region}". ')
 
             # special case for stack_end overriding sp default
             if actual_stack_end is not None and state.arch.registers[reg][0] == state.arch.sp_offset:
@@ -343,7 +335,7 @@ class SimOS:
         return None
 
     def syscall_cc(self, state) -> angr.calling_conventions.SimCCSyscall | None:
-        raise NotImplementedError()
+        raise NotImplementedError
 
     def is_syscall_addr(self, addr):
         return False
@@ -415,8 +407,7 @@ class SimOS:
         fs = selector
         selector = self._create_selector(4, S_GDT | S_PRIV_0)
         gs = selector
-        global_descriptor_table = GlobalDescriptorTable(GDT_ADDR, GDT_LIMIT, table, gdt, cs, ds, es, ss, fs, gs)
-        return global_descriptor_table
+        return GlobalDescriptorTable(GDT_ADDR, GDT_LIMIT, table, gdt, cs, ds, es, ss, fs, gs)
 
     @staticmethod
     def _create_selector(idx, flags):

angr/simos/snimmuc_nxp.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from typing import TYPE_CHECKING
 
 from io import BytesIO
@@ -16,17 +17,13 @@ class SimSnimmucNxp(SimOS):
     This class implements the "OS" for a bare-metal firmware used at an imaginary company.
     """
 
-    def __init__(self, project: "Project", name=None, **kwargs):  # pylint:disable=unused-argument
+    def __init__(self, project: Project, name=None, **kwargs):  # pylint:disable=unused-argument
         super().__init__(project, name=name)
 
     def configure_project(self):
         # pattern match the entry point to figure out if we support parsing this binary
         entry_bytes = self.project.loader.memory.load(self.project.entry, 3 * 4)
-        if not entry_bytes == (
-            b"\x94\x21\xff\xf0"  #  stwu   r1, -10(r1)
-            b"\x7c\x08\x02\xa6"  #  mfspr  r0, lr
-            b"\x90\x01\x00\x14"  #  stw    r0, 4(r1)
-        ):
+        if entry_bytes != b"\x94!\xff\xf0" b"|\x08\x02\xa6" b"\x90\x01\x00\x14":
             return
 
         entry_block = self.project.factory.block(self.project.entry)

angr/simos/userland.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 
 from ..calling_conventions import SYSCALL_CC, SimCCSyscall
@@ -74,14 +75,13 @@ class SimUserland(SimOS):
         sym_num = cc.syscall_num(state)
         try:
             num = state.solver.eval_one(sym_num)
-        except SimSolverError:
+        except SimSolverError as err:
             if allow_unsupported:
                 num = self.unknown_syscall_number
             else:
                 if not state.solver.satisfiable():
-                    raise AngrUnsupportedSyscallError("The program state is not satisfiable")
-                else:
-                    raise AngrUnsupportedSyscallError("Got a symbolic syscall number")
+                    raise AngrUnsupportedSyscallError("The program state is not satisfiable") from err
+                raise AngrUnsupportedSyscallError("Got a symbolic syscall number") from err
 
         proc = self.syscall_from_number(num, allow_unsupported=allow_unsupported, abi=abi)
         proc.cc = cc
@@ -91,7 +91,7 @@ class SimUserland(SimOS):
         """
         Optionally, override this function to determine which abi is being used for the state's current syscall.
         """
-        return None
+        return
 
     def is_syscall_addr(self, addr):
         """
@@ -146,7 +146,7 @@ class SimUserland(SimOS):
 
         if self.syscall_library is None:
             if not allow_unsupported:
-                raise AngrUnsupportedSyscallError("%s does not have a library of syscalls implemented" % self.name)
+                raise AngrUnsupportedSyscallError(f"{self.name} does not have a library of syscalls implemented")
             proc = P["stubs"]["syscall"]()
         elif not allow_unsupported and not self.syscall_library.has_implementation(number, self.arch, abilist):
             raise AngrUnsupportedSyscallError("No implementation for syscall %d" % number)

angr/simos/windows.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import enum
 import os
 import logging
@@ -79,8 +80,7 @@ class SimWindows(SimOS):
         sym = self.project.loader.find_symbol(name)
         if sym is None:
             return self.project.loader.extern_object.get_pseudo_addr(name)
-        else:
-            return sym.rebased_addr
+        return sym.rebased_addr
 
     # pylint: disable=arguments-differ
     def state_entry(self, args=None, env=None, argc=None, **kwargs):
@@ -269,7 +269,7 @@ class SimWindows(SimOS):
                                 init_order.append(depo)
 
                 fuck_load(self.project.loader.main_object)
-                load_order = [self.project.loader.main_object] + init_order
+                load_order = [self.project.loader.main_object, *init_order]
 
                 def link(a, b):
                     state.mem[a].dword = b
@@ -309,9 +309,12 @@ class SimWindows(SimOS):
         if engine is not self.project.factory.default_engine:
             raise exception
         # don't bother handling symbolic-address exceptions
-        if type(exception) is SimSegfaultException:
-            if exception.original_addr is not None and exception.original_addr.symbolic:
-                raise exception
+        if (
+            type(exception) is SimSegfaultException
+            and exception.original_addr is not None
+            and exception.original_addr.symbolic
+        ):
+            raise exception
 
         _l.debug("Handling exception from block at %#x: %r", successors.addr, exception)
 
@@ -380,12 +383,12 @@ class SimWindows(SimOS):
         tib_addr = exc_state.regs._fs.concat(claripy.BVV(0, 16))
         if exc_state.solver.is_true(exc_state.mem[tib_addr].long.resolved == -1):
             _l.debug("... no handlers registered")
-            exception.args = ("Unhandled exception: %r" % exception,)
+            exception.args = (f"Unhandled exception: {exception!r}",)
             raise exception
         # catch nested exceptions here with magic value
         if exc_state.solver.is_true(exc_state.mem[tib_addr].long.resolved == 0xBADFACE):
             _l.debug("... nested exception")
-            exception.args = ("Unhandled exception: %r" % exception,)
+            exception.args = (f"Unhandled exception: {exception!r}",)
             raise exception
 
         # serialize the thread context and set up the exception record...
@@ -419,7 +422,7 @@ class SimWindows(SimOS):
 
         # let's go let's go!
         # we want to use a true guard here. if it's not true, then it's already been added in windup.
-        successors.add_successor(exc_state, self._exception_handler, claripy.true, "Ijk_Exception")
+        successors.add_successor(exc_state, self._exception_handler, claripy.true(), "Ijk_Exception")
         successors.processed = True
 
     # these two methods load and store register state from a struct CONTEXT
@@ -508,7 +511,7 @@ class SimWindows(SimOS):
         """
         exfiltration_reg = "eax"
         # instruction to inject for reading the value at segment value = offset
-        read_fs0_x86 = b"\x64\xA1\x18\x00\x00\x00\x90\x90\x90\x90"  # mov eax, fs:[0x18]
+        read_fs0_x86 = b"\x64\xa1\x18\x00\x00\x00\x90\x90\x90\x90"  # mov eax, fs:[0x18]
         return concrete_target.execute_shellcode(read_fs0_x86, exfiltration_reg)
 
     @staticmethod
@@ -522,7 +525,7 @@ class SimWindows(SimOS):
         """
         exfiltration_reg = "rax"
         # instruction to inject for reading the value at segment value = offset
-        read_gs0_x64 = b"\x65\x48\x8B\x04\x25\x30\x00\x00\x00\x90\x90\x90\x90"  # mov rax, gs:[0x30]
+        read_gs0_x64 = b"\x65\x48\x8b\x04\x25\x30\x00\x00\x00\x90\x90\x90\x90"  # mov rax, gs:[0x30]
         return concrete_target.execute_shellcode(read_gs0_x64, exfiltration_reg)
 
     def get_segment_register_name(self):

angr/slicer.py

@@ -1,4 +1,5 @@
 # pylint:disable=no-self-use
+from __future__ import annotations
 import pyvex
 
 from .errors import SimSlicerError
@@ -118,7 +119,7 @@ class SimSlicer:
         :return:
         """
 
-        funcname = "_forward_handler_stmt_%s" % type(stmt).__name__
+        funcname = f"_forward_handler_stmt_{type(stmt).__name__}"
 
         if hasattr(self, funcname):
             getattr(self, funcname)(stmt, state)
@@ -144,7 +145,7 @@ class SimSlicer:
         :return:
         """
 
-        funcname = "_forward_handler_expr_%s" % type(expr).__name__
+        funcname = f"_forward_handler_expr_{type(expr).__name__}"
 
         if hasattr(self, funcname):
             return getattr(self, funcname)(expr, state)
@@ -154,10 +155,12 @@ class SimSlicer:
     def _forward_handler_expr_Get(self, expr, state):
         reg = expr.offset
 
-        if state.options["mock_sp"] and reg == self._arch.sp_offset:
-            return state.regs[reg]
-
-        elif state.options["mock_bp"] and reg == self._arch.bp_offset:
+        if (
+            state.options["mock_sp"]
+            and reg == self._arch.sp_offset
+            or state.options["mock_bp"]
+            and reg == self._arch.bp_offset
+        ):
             return state.regs[reg]
 
         return None
@@ -174,7 +177,7 @@ class SimSlicer:
         return expr.con.value
 
     def _forward_handler_expr_Binop(self, expr, state):
-        funcname = "_forward_handler_expr_binop_%s" % expr.op.strip("Iop_")
+        funcname = "_forward_handler_expr_binop_{}".format(expr.op.strip("Iop_"))
 
         if hasattr(self, funcname):
             op0_val = self._forward_handler_expr(expr.args[0], state)
@@ -224,7 +227,7 @@ class SimSlicer:
     #
 
     def _backward_handler_stmt(self, stmt, state):
-        funcname = "_backward_handler_stmt_%s" % type(stmt).__name__
+        funcname = f"_backward_handler_stmt_{type(stmt).__name__}"
 
         in_slice = False
         if hasattr(self, funcname):
@@ -262,8 +265,7 @@ class SimSlicer:
 
             return True
 
-        else:
-            return False
+        return False
 
     def _backward_handler_stmt_Store(self, stmt, state):
         addr = stmt.addr
@@ -301,7 +303,7 @@ class SimSlicer:
     #
 
     def _backward_handler_expr(self, expr, state):
-        funcname = "_backward_handler_expr_%s" % type(expr).__name__
+        funcname = f"_backward_handler_expr_{type(expr).__name__}"
         if hasattr(self, funcname):
             getattr(self, funcname)(expr, state)
 

angr/state_hierarchy.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 import weakref
 import itertools
@@ -52,8 +53,7 @@ class StateHierarchy:
             self._weakref_cache[id(obj)] = ref
             self._reverse_weakref_cache[ref] = id(obj)
             return ref
-        else:
-            return self._weakref_cache[id(obj)]
+        return self._weakref_cache[id(obj)]
 
     def dead_ref(self, ref):
         if self._defer_cleanup:
@@ -195,7 +195,7 @@ class StateHierarchy:
                 root = lineage[bad]
                 l.debug("... returning %d (%s)", bad, root)
                 return root
-            elif lineage[cur]().reachable():
+            if lineage[cur]().reachable():
                 l.debug("... %d is reachable", cur)
                 good = cur
             else:
@@ -213,7 +213,7 @@ class StateHierarchy:
                 n()._satisfiable = False
                 try:
                     if n().state is not None:
-                        n().state.add_constraints(claripy.false)
+                        n().state.add_constraints(claripy.false())
                 except ReferenceError:
                     pass
             self._graph.remove_nodes_from(all_children)

angr/state_plugins/__init__.py

@@ -1,4 +1,5 @@
 # pylint:disable=wildcard-import
+from __future__ import annotations
 from .plugin import *
 from .libc import *
 from .inspect import *