angr 9.2.117__py3-none-win_amd64.whl → 9.2.119__py3-none-win_amd64.whl

angr/state_plugins/uc_manager.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 
 import claripy
@@ -9,6 +10,8 @@ l = logging.getLogger(name=__name__)
 
 
 class SimUCManager(SimStatePlugin):
+    _uc_alloc_depth: dict[claripy.ast.Base, int]
+
     def __init__(self, man=None):
         SimStatePlugin.__init__(self)
 
@@ -32,6 +35,8 @@ class SimUCManager(SimStatePlugin):
         # The maximum allocation depth
         self._max_alloc_depth = 20
 
+        self._uc_alloc_depth = {}
+
     def assign(self, dst_addr_ast):
         """
         Assign a new region for under-constrained symbolic execution.
@@ -40,17 +45,17 @@ class SimUCManager(SimStatePlugin):
         :return: as ast of memory address that points to a new region
         """
 
-        if dst_addr_ast.uc_alloc_depth > self._max_alloc_depth:
+        dst_uc_alloc_depth = self._uc_alloc_depth[dst_addr_ast]
+        if dst_uc_alloc_depth > self._max_alloc_depth:
             raise SimUCManagerAllocationError(
-                "Current allocation depth %d is greater than the cap (%d)"
-                % (dst_addr_ast.uc_alloc_depth, self._max_alloc_depth)
+                "Current allocation depth %d is greater than the cap (%d)" % (dst_uc_alloc_depth, self._max_alloc_depth)
             )
 
         abs_addr = self._region_base + self._pos
         ptr = claripy.BVV(abs_addr, self.state.arch.bits)
         self._pos += self._region_size
 
-        self._alloc_depth_map[(abs_addr - self._region_base) // self._region_size] = dst_addr_ast.uc_alloc_depth
+        self._alloc_depth_map[(abs_addr - self._region_base) // self._region_size] = dst_uc_alloc_depth
 
         l.debug("Assigned new memory region %s", ptr)
         return ptr
@@ -59,13 +64,15 @@ class SimUCManager(SimStatePlugin):
     def copy(self, memo):  # pylint: disable=unused-argument
         return SimUCManager(man=self)
 
-    def get_alloc_depth(self, addr):
-        block_pos = (addr - self._region_base) // self._region_size
+    def get_alloc_depth(self, addr: int | claripy.ast.Base) -> int | None:
+        if isinstance(addr, claripy.ast.Base):
+            return self._uc_alloc_depth.get(addr, None)
 
-        if block_pos not in self._alloc_depth_map:
-            return None
+        block_pos = (addr - self._region_base) // self._region_size
+        return self._alloc_depth_map.get(block_pos, None)
 
-        return self._alloc_depth_map[block_pos]
+    def set_alloc_depth(self, addr: claripy.ast.Base, depth: int):
+        self._uc_alloc_depth[addr] = depth
 
     def is_bounded(self, ast):
         """

angr/state_plugins/unicorn_engine.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import binascii
 import copy
 import ctypes
@@ -302,10 +303,7 @@ class Uniwrapper(unicorn.Uc if unicorn is not None else object):
         self.wrapped_mapped = set()
         self.wrapped_hooks = set()
         self.id = None
-        if thumb:
-            uc_mode = arch.uc_mode_thumb
-        else:
-            uc_mode = arch.uc_mode
+        uc_mode = arch.uc_mode_thumb if thumb else arch.uc_mode
         unicorn.Uc.__init__(self, arch.uc_arch, uc_mode)
 
     def hook_add(self, htype, callback, user_data=None, begin=1, end=0, arg1=0):
@@ -839,7 +837,7 @@ class Unicorn(SimStatePlugin):
 
     def _setup_unicorn(self):
         if self.state.arch.uc_mode is None:
-            raise SimUnicornUnsupport("unsupported architecture %r" % self.state.arch)
+            raise SimUnicornUnsupport(f"unsupported architecture {self.state.arch!r}")
 
     def set_last_block_details(self, details):
         _UC_NATIVE.set_last_block_details(self._uc_state, details["addr"], details["curr_count"], details["tot_count"])
@@ -868,9 +866,7 @@ class Unicorn(SimStatePlugin):
             )
         elif arch == "i386":
             self.uc.hook_add(unicorn.UC_HOOK_INTR, self._hook_intr_x86, None, 1, 0)
-        elif arch == "mips":
-            self.uc.hook_add(unicorn.UC_HOOK_INTR, self._hook_intr_mips, None, 1, 0)
-        elif arch == "mipsel":
+        elif arch == "mips" or arch == "mipsel":
             self.uc.hook_add(unicorn.UC_HOOK_INTR, self._hook_intr_mips, None, 1, 0)
         elif arch == "arm":
             # EDG says: Unicorn's ARM support has no concept of interrupts.
@@ -935,8 +931,7 @@ class Unicorn(SimStatePlugin):
         if sysno in self.syscall_hooks:
             self.syscall_hooks[sysno](self.state)
             return True
-        else:
-            return False
+        return False
 
     def _handle_syscall(self, uc, user_data):  # pylint:disable=unused-argument
         # unicorn does not support syscall, we should giveup emulation
@@ -956,16 +951,13 @@ class Unicorn(SimStatePlugin):
     def _symbolic_passthrough(self, d):
         if not d.symbolic:
             return d
-        elif options.UNICORN_AGGRESSIVE_CONCRETIZATION in self.state.options:
+        if options.UNICORN_AGGRESSIVE_CONCRETIZATION in self.state.options:
             return self._concretize(d)
-        elif len(d.variables & self.never_concretize) > 0:
+        if len(d.variables & self.never_concretize) > 0:
             return d
-        elif d.variables.issubset(self.always_concretize):
-            return self._concretize(d)
-        elif self.state.solver.eval(self.state.ip) in self.concretize_at:
+        if d.variables.issubset(self.always_concretize) or self.state.solver.eval(self.state.ip) in self.concretize_at:
             return self._concretize(d)
-        else:
-            return d
+        return d
 
     def _report_symbolic_blocker(self, d, from_where):
         if options.UNICORN_THRESHOLD_CONCRETIZATION in self.state.options:
@@ -1001,10 +993,9 @@ class Unicorn(SimStatePlugin):
         if len(d.annotations):
             l.debug("Blocking annotated AST.")
             return None
-        elif not d.symbolic:
+        if not d.symbolic:
             return d
-        else:
-            l.debug("Processing AST with variables %s.", d.variables)
+        l.debug("Processing AST with variables %s.", d.variables)
 
         dd = self._symbolic_passthrough(d)
 
@@ -1012,12 +1003,11 @@ class Unicorn(SimStatePlugin):
             if d.symbolic:
                 l.debug("... concretized")
             return dd
-        elif from_where == "reg" and options.UNICORN_SYM_REGS_SUPPORT in self.state.options:
+        if from_where == "reg" and options.UNICORN_SYM_REGS_SUPPORT in self.state.options:
             l.debug("... allowing symbolic register")
             return dd
-        else:
-            l.debug("... denied")
-            return None
+        l.debug("... denied")
+        return None
 
     def _hook_mem_unmapped(self, uc, access, address, size, value, user_data):  # pylint:disable=unused-argument
         """
@@ -1033,7 +1023,7 @@ class Unicorn(SimStatePlugin):
                 if pageno >= needed_pages:
                     break
                 if options.UNICORN_ZEROPAGE_GUARD in self.state.options:
-                    self.error = "accessing zero page (%#x)" % access
+                    self.error = f"accessing zero page ({access:#x})"
                     l.warning(self.error)
 
                     _UC_NATIVE.stop(self._uc_state, STOP.STOP_ZEROPAGE)
@@ -1287,9 +1277,9 @@ class Unicorn(SimStatePlugin):
 
         # Initialize list of artificial VEX registers
         artificial_regs_list = (ctypes.c_uint64(offset) for offset in self.state.arch.artificial_registers_offsets)
-        artifical_regs_count = len(self.state.arch.artificial_registers_offsets)
-        artificial_regs_array = (ctypes.c_uint64 * artifical_regs_count)(*artificial_regs_list)
-        _UC_NATIVE.set_artificial_registers(self._uc_state, artificial_regs_array, artifical_regs_count)
+        artificial_regs_count = len(self.state.arch.artificial_registers_offsets)
+        artificial_regs_array = (ctypes.c_uint64 * artificial_regs_count)(*artificial_regs_list)
+        _UC_NATIVE.set_artificial_registers(self._uc_state, artificial_regs_array, artificial_regs_count)
 
         # Initialize VEX register offset to unicorn register ID mappings and VEX register offset to name map
         vex_reg_offsets = []
@@ -1639,10 +1629,7 @@ class Unicorn(SimStatePlugin):
                         mantissa = 0
                     elif exponent == 0x7FF:  # nan or infinity
                         exponent = 0x7FFF
-                        if mantissa != 0:
-                            mantissa = 0x8000000000000000
-                        else:
-                            mantissa = 0xFFFFFFFFFFFFFFFF
+                        mantissa = 9223372036854775808 if mantissa != 0 else 18446744073709551615
 
                     if sign:
                         exponent |= 0x8000
@@ -1742,10 +1729,7 @@ class Unicorn(SimStatePlugin):
         handling symbolic exits in native interface
         """
 
-        if succ_state:
-            state = succ_state
-        else:
-            state = self.state
+        state = succ_state if succ_state else self.state
 
         # first, get the ignore list (in case of symbolic registers)
         saved_registers = []
@@ -1857,7 +1841,7 @@ class Unicorn(SimStatePlugin):
 
     def _check_registers(self, report=True):
         """check if this state might be used in unicorn (has no concrete register)"""
-        for r in self.state.arch.uc_regs.keys():
+        for r in self.state.arch.uc_regs:
             v = getattr(self.state.regs, r)
             processed_v = self._process_value(v, "reg")
             if processed_v is None or processed_v.symbolic:

angr/state_plugins/view.py

@@ -1,5 +1,7 @@
-from typing import TYPE_CHECKING
+from __future__ import annotations
+
 import logging
+from typing import ClassVar, TYPE_CHECKING
 
 import claripy
 from archinfo.arch_soot import ArchSoot, SootAddressDescriptor
@@ -77,12 +79,12 @@ class SimRegNameView(SimStatePlugin):
 
         try:
             return self.state.registers.store(k, v, inspect=inspect, disable_actions=disable_actions)
-        except KeyError:
+        except KeyError as err:
             # What do we do in case we are dealing with soot? there are no register
             if isinstance(self.state.arch, ArchSoot):
                 pass
             else:
-                raise AttributeError(k)
+                raise AttributeError(k) from err
 
     def __dir__(self):
         if self.state.arch.name in ("X86", "AMD64"):
@@ -92,8 +94,8 @@ class SimRegNameView(SimStatePlugin):
                 + ["tag%d" % n for n in range(8)]
                 + ["flags", "eflags", "rflags"]
             )
-        elif is_arm_arch(self.state.arch):
-            return list(self.state.arch.registers.keys()) + ["flags"]
+        if is_arm_arch(self.state.arch):
+            return [*list(self.state.arch.registers.keys()), "flags"]
         return self.state.arch.registers.keys()
 
     @SimStatePlugin.memo
@@ -119,7 +121,7 @@ class SimMemView(SimStatePlugin):
         - You first use [array index notation] to specify the address you'd like to load from
         - If at that address is a pointer, you may access the ``deref`` property to return a SimMemView at the
           address present in memory.
-        - You then specify a type for the data by simply accesing a property of that name. For a list of supported
+        - You then specify a type for the data by simply accessing a property of that name. For a list of supported
           types, look at ``state.mem.types``.
         - You can then *refine* the type. Any type may support any refinement it likes. Right now the only refinements
           supported are that you may access any member of a struct by its member name, and you may index into a
@@ -159,7 +161,7 @@ class SimMemView(SimStatePlugin):
         if isinstance(self._addr, int):
             self._addr = claripy.BVV(self._addr, self.state.arch.bits)
 
-    def _deeper(self, **kwargs) -> "SimMemView":
+    def _deeper(self, **kwargs) -> SimMemView:
         if "ty" not in kwargs:
             kwargs["ty"] = self._type
         if "addr" not in kwargs:
@@ -168,16 +170,15 @@ class SimMemView(SimStatePlugin):
             kwargs["state"] = self.state
         return SimMemView(**kwargs)
 
-    def __getitem__(self, k) -> "SimMemView":
+    def __getitem__(self, k) -> SimMemView:
         if isinstance(k, slice):
             if k.step is not None:
                 raise ValueError("Slices with strides are not supported")
-            elif k.start is None:
+            if k.start is None:
                 raise ValueError("Must specify start index")
-            elif k.stop is not None:
+            if k.stop is not None:
                 raise ValueError("Slices with stop index are not supported")
-            else:
-                addr = k.start
+            addr = k.start
         elif self._type is not None and self._type._can_refine_int:
             return self._type._refine(self, k)
         else:
@@ -187,7 +188,7 @@ class SimMemView(SimStatePlugin):
     def __setitem__(self, k, v):
         self.__getitem__(k).store(v)
 
-    types = {}
+    types: ClassVar[dict] = {}
     state = None
 
     def __repr__(self):
@@ -208,7 +209,7 @@ class SimMemView(SimStatePlugin):
     def __dir__(self):
         return self._type._refine_dir() if self._type else [x for x in SimMemView.types if " " not in x] + ["struct"]
 
-    struct: "StructMode"
+    struct: StructMode
 
     def __getattr__(self, k):
         if k in (
@@ -239,7 +240,7 @@ class SimMemView(SimStatePlugin):
     def __cmp__(self, other):
         raise ValueError("Trying to compare SimMemView is not what you want to do")
 
-    def with_type(self, sim_type: "SimType") -> "SimMemView":
+    def with_type(self, sim_type: SimType) -> SimMemView:
         """
         Returns a copy of the SimMemView with a type.
 
@@ -276,7 +277,7 @@ class SimMemView(SimStatePlugin):
         return self._type.extract(self.state, self._addr, True)
 
     @property
-    def deref(self) -> "SimMemView":
+    def deref(self) -> SimMemView:
         if self._addr is None:
             raise ValueError("Trying to dereference pointer without addr defined")
         ptr = self.state.memory.load(self._addr, self.state.arch.bytes, endness=self.state.arch.memory_endness)
@@ -286,14 +287,14 @@ class SimMemView(SimStatePlugin):
 
         return self._deeper(ty=self._type.pts_to if isinstance(self._type, SimTypePointer) else None, addr=ptr)
 
-    def array(self, n) -> "SimMemView":
+    def array(self, n) -> SimMemView:
         if self._addr is None:
-            raise ValueError("Trying to produce array without specifying adddress")
+            raise ValueError("Trying to produce array without specifying address")
         if self._type is None:
             raise ValueError("Trying to produce array without specifying type")
         return self._deeper(ty=SimTypeFixedSizeArray(self._type, n))
 
-    def member(self, member_name: str) -> "SimMemView":
+    def member(self, member_name: str) -> SimMemView:
         """
         If self is a struct and member_name is a member of the struct, return
         that member element. Otherwise raise an exception.

angr/storage/__init__.py

@@ -1,4 +1,5 @@
 # misc
+from __future__ import annotations
 
 DUMMY_SYMBOLIC_READ_VALUE = 0xC0DEB4BE
 

angr/storage/file.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 import itertools
 
@@ -43,8 +44,7 @@ class Flags:  # pylint: disable=W0232,
 def _deps_unpack(a):
     if isinstance(a, SimActionObject):
         return a.ast, a.reg_deps, a.tmp_deps
-    else:
-        return a, None, None
+    return a, None, None
 
 
 class SimFileBase(SimStatePlugin):
@@ -209,12 +209,11 @@ class SimFile(SimFileBase, DefaultMemory):  # TODO: pick a better base class omg
             content = claripy.BVV(content.encode())
         elif content is None:
             pass
-        elif isinstance(content, claripy.Bits):
+        elif isinstance(content, claripy.ast.Bits):
             if concrete is None and not content.symbolic:
                 concrete = True
-            pass
         else:
-            raise TypeError("Can't handle SimFile content of type %s" % type(content))
+            raise TypeError(f"Can't handle SimFile content of type {type(content)}")
 
         if concrete is None:
             concrete = False
@@ -265,7 +264,7 @@ class SimFile(SimFileBase, DefaultMemory):  # TODO: pick a better base class omg
         data = self.load(0, size)
 
         kwargs["cast_to"] = kwargs.get("cast_to", bytes)
-        kwargs["extra_constraints"] = tuple(kwargs.get("extra_constraints", ())) + (self._size == size,)
+        kwargs["extra_constraints"] = (*tuple(kwargs.get("extra_constraints", ())), self._size == size)
         return self.state.solver.eval(data, **kwargs)
 
     def read(self, pos, size, **kwargs):
@@ -311,12 +310,11 @@ class SimFile(SimFileBase, DefaultMemory):  # TODO: pick a better base class omg
                 real_size,
                 real_size + pos,
             )
-        else:
-            # it's not possible to EOF
-            # we don't need to constrain or min/max the output size because there are already constraints asserting
-            # that the total filesize is pretty big
-            # note: this assumes that constraints cannot be removed
-            return self.load(pos, passed_max_size, disable_actions=disable_actions, inspect=inspect), size, size + pos
+        # it's not possible to EOF
+        # we don't need to constrain or min/max the output size because there are already constraints asserting
+        # that the total filesize is pretty big
+        # note: this assumes that constraints cannot be removed
+        return self.load(pos, passed_max_size, disable_actions=disable_actions, inspect=inspect), size, size + pos
 
     def write(self, pos, data, size=None, events=True, **kwargs):
         if events:
@@ -324,7 +322,7 @@ class SimFile(SimFileBase, DefaultMemory):  # TODO: pick a better base class omg
 
         data = _deps_unpack(data)[0]
         if size is None:
-            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.Bits) else len(data)
+            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.ast.Bits) else len(data)
         # \(_^^)/
         self.store(pos, data, size=size)
         new_end = _deps_unpack(pos + size)[0]  # decline to store SAO
@@ -394,7 +392,7 @@ class SimFileStream(SimFile):
 
     def write(self, _, data, size=None, **kwargs):
         self.pos = super().write(self.pos, data, size, **kwargs)
-        return None
+        return
 
     @SimStatePlugin.memo
     def copy(self, memo):
@@ -444,7 +442,7 @@ class SimPackets(SimFileBase):
                     if type(x) is tuple
                     else (
                         (x, len(x) // 8)
-                        if isinstance(x, claripy.Bits)
+                        if isinstance(x, claripy.ast.Bits)
                         else (
                             (x.ast, len(x) // 8)
                             if isinstance(x, SimActionObject)
@@ -512,9 +510,9 @@ class SimPackets(SimFileBase):
             pos = len(self.content)
         if pos < 0:
             raise SimFileError("SimPacket.read(%d): Negative packet number?" % pos)
-        elif pos > len(self.content):
+        if pos > len(self.content):
             raise SimFileError("SimPacket.read(%d): Packet number is past frontier of %d?" % (pos, len(self.content)))
-        elif pos != len(self.content):
+        if pos != len(self.content):
             _, realsize = self.content[pos]
             self.state.add_constraints(realsize <= size)  # assert that the packet fits within the read request
             if not self.state.solver.satisfiable():
@@ -569,7 +567,7 @@ class SimPackets(SimFileBase):
         )
         packet = (data, size)
         self.content.append(packet)
-        return packet + (pos + 1,)
+        return (*packet, pos + 1)
 
     def write(self, pos, data, size=None, events=True, **kwargs):
         """
@@ -595,7 +593,7 @@ class SimPackets(SimFileBase):
         if type(data) is bytes:
             data = claripy.BVV(data)
         if size is None:
-            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.Bits) else len(data)
+            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.ast.Bits) else len(data)
         if type(size) is int:
             size = claripy.BVV(size, self.state.arch.bits)
 
@@ -604,9 +602,9 @@ class SimPackets(SimFileBase):
             pos = len(self.content)
         if pos < 0:
             raise SimFileError("SimPacket.write(%d): Negative packet number?" % pos)
-        elif pos > len(self.content):
+        if pos > len(self.content):
             raise SimFileError("SimPacket.write(%d): Packet number is past frontier of %d?" % (pos, len(self.content)))
-        elif pos != len(self.content):
+        if pos != len(self.content):
             realdata, realsize = self.content[pos]
             maxlen = max(len(realdata), len(data))
             self.state.add_constraints(realdata[maxlen - 1 : 0] == data[maxlen - 1 : 0])
@@ -631,7 +629,7 @@ class SimPackets(SimFileBase):
         for o in others:
             if o.write_mode is None:
                 continue
-            elif self.write_mode is None:
+            if self.write_mode is None:
                 self.write_mode = o.write_mode
             elif self.write_mode is not o.write_mode:
                 raise SimMergeError("Cannot merge SimPackets with disparate write_mode")
@@ -687,7 +685,7 @@ class SimPacketsStream(SimPackets):
 
     def write(self, _, data, size=None, **kwargs):
         self.pos = super().write(self.pos, data, size, **kwargs)
-        return None
+        return
 
     @SimStatePlugin.memo
     def copy(self, memo):
@@ -905,7 +903,7 @@ class SimFileDescriptor(SimFileDescriptorBase):
 
         data = _deps_unpack(data)[0]
         if size is None:
-            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.Bits) else len(data)
+            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.ast.Bits) else len(data)
 
         size = self._prep_write(size)
         self._pos = self.file.write(self._pos, data, size)
@@ -913,7 +911,7 @@ class SimFileDescriptor(SimFileDescriptorBase):
 
     def seek(self, offset, whence="start"):
         if not self.file.seekable:
-            return claripy.false
+            return claripy.false()
 
         if type(offset) is int:
             offset = claripy.BVV(offset, self.state.arch.bits)
@@ -931,9 +929,9 @@ class SimFileDescriptor(SimFileDescriptorBase):
 
     def eof(self):
         if not self.file.seekable:
-            return claripy.false
+            return claripy.false()
         if not getattr(self.file, "has_end", True):
-            return claripy.false
+            return claripy.false()
         return self._pos == self.file.size
 
     def tell(self):
@@ -1036,7 +1034,7 @@ class SimFileDescriptorDuplex(SimFileDescriptorBase):
     def write_data(self, data, size=None, **kwargs):
         data = _deps_unpack(data)[0]
         if size is None:
-            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.Bits) else len(data)
+            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.ast.Bits) else len(data)
 
         size = self._prep_write(size)
         self._write_pos = self._write_file.write(self._write_pos, data, size)
@@ -1050,16 +1048,16 @@ class SimFileDescriptorDuplex(SimFileDescriptorBase):
     def eof(self):
         # the thing that makes the most sense is for this to refer to the read eof status...
         if not self._read_file.seekable:
-            return claripy.false
+            return claripy.false()
         if not getattr(self._read_file, "has_end", True):
-            return claripy.false
+            return claripy.false()
         return self._read_pos == self._read_file.size
 
     def tell(self):
         return None
 
     def seek(self, offset, whence="start"):
-        return claripy.false
+        return claripy.false()
 
     def size(self):
         return None
@@ -1158,8 +1156,8 @@ class SimPacketsSlots(SimFileBase):
 
         try:
             req_size = self.state.solver.eval_one(size)
-        except SimSolverError:
-            raise SimFileError("SimPacketsSlots can't handle multivalued read sizes")
+        except SimSolverError as err:
+            raise SimFileError("SimPacketsSlots can't handle multivalued read sizes") from err
 
         avail_size = self.read_sizes[0]
 

angr/storage/memory_mixins/__init__.py

@@ -1,4 +1,5 @@
 # pylint:disable=abstract-method,wrong-import-position,unused-argument,missing-class-docstring,arguments-differ
+from __future__ import annotations
 from typing import Tuple, Dict, Any, Optional
 from collections.abc import Iterable
 
@@ -32,14 +33,13 @@ class MemoryMixin(SimStatePlugin):
         if self.id in ("reg", "mem"):
             return self.id
 
-        elif self.id.startswith("file"):
+        if self.id.startswith("file"):
             return "file"
 
-        elif "_" in self.id:
+        if "_" in self.id:
             return self.id.split("_")[0]
 
-        else:
-            raise SimMemoryError('Unknown SimMemory category for memory_id "%s"' % self.id)
+        raise SimMemoryError(f'Unknown SimMemory category for memory_id "{self.id}"')
 
     @property
     def variable_key_prefix(self):
@@ -53,10 +53,7 @@ class MemoryMixin(SimStatePlugin):
 
     def _add_constraints(self, c, add_constraints=True, condition=None, **kwargs):
         if add_constraints:
-            if condition is not None:
-                to_add = (c & condition) | ~condition
-            else:
-                to_add = c
+            to_add = c & condition | ~condition if condition is not None else c
             self.state.add_constraints(to_add)
 
     def load(self, addr, size=None, **kwargs):
@@ -94,7 +91,7 @@ class MemoryMixin(SimStatePlugin):
         :param writing:
         :return:        A memoryview into the loaded bytes.
         """
-        raise NotImplementedError()
+        raise NotImplementedError
 
     def erase(self, addr, size=None, **kwargs) -> None:
         """
@@ -105,7 +102,7 @@ class MemoryMixin(SimStatePlugin):
         :param size:    The number of bytes for erasing.
         :return:        None
         """
-        raise NotImplementedError()
+        raise NotImplementedError
 
     def _default_value(self, addr, size, name=None, inspect=True, events=True, key=None, **kwargs):
         """
@@ -127,7 +124,7 @@ class MemoryMixin(SimStatePlugin):
         :param merged_size:     The size (in bytes) of the merged value.
         :return:                The merged value, or None to skip merging of the current value.
         """
-        raise NotImplementedError()
+        raise NotImplementedError
 
     def _merge_labels(self, labels: Iterable[dict], **kwargs) -> dict | None:
         """
@@ -136,13 +133,13 @@ class MemoryMixin(SimStatePlugin):
         :param labels:          A collection of labels.
         :return:                The merged label, or None to skip merging of the current label.
         """
-        raise NotImplementedError()
+        raise NotImplementedError
 
     def replace_all(self, old: claripy.ast.BV, new: claripy.ast.BV):
-        raise NotImplementedError()
+        raise NotImplementedError
 
     def _replace_all(self, addrs: Iterable[int], old: claripy.ast.BV, new: claripy.ast.BV):
-        raise NotImplementedError()
+        raise NotImplementedError
 
     def copy_contents(self, dst, src, size, condition=None, **kwargs):
         """
@@ -155,7 +152,7 @@ class MemoryMixin(SimStatePlugin):
         :param kwargs:      Other parameters.
         :return:        None
         """
-        raise NotImplementedError()
+        raise NotImplementedError
 
 
 from .actions_mixin import ActionsMixinHigh, ActionsMixinLow