v86 0.4.0 → 0.5.10

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (386) hide show
  1. package/Readme.md +56 -111
  2. package/build/libv86-debug.js +12677 -0
  3. package/build/libv86-debug.mjs +732 -0
  4. package/build/libv86.js +710 -0
  5. package/build/libv86.mjs +636 -0
  6. package/build/v86-debug.wasm +0 -0
  7. package/build/v86-fallback.wasm +0 -0
  8. package/build/v86.wasm +0 -0
  9. package/package.json +12 -35
  10. package/bios/.gitignore +0 -1
  11. package/bios/COPYING.LESSER +0 -165
  12. package/bios/bochs-bios.bin +0 -0
  13. package/bios/bochs-vgabios.bin +0 -0
  14. package/bios/fetch-and-build-seabios.sh +0 -13
  15. package/bios/seabios/.config +0 -113
  16. package/bios/seabios/.config.old +0 -114
  17. package/bios/seabios/.gitignore +0 -4
  18. package/bios/seabios/COPYING +0 -674
  19. package/bios/seabios/COPYING.LESSER +0 -165
  20. package/bios/seabios/Makefile +0 -286
  21. package/bios/seabios/README +0 -17
  22. package/bios/seabios/docs/Build_overview.md +0 -104
  23. package/bios/seabios/docs/Contributing.md +0 -20
  24. package/bios/seabios/docs/Debugging.md +0 -111
  25. package/bios/seabios/docs/Developer_Documentation.md +0 -25
  26. package/bios/seabios/docs/Developer_links.md +0 -86
  27. package/bios/seabios/docs/Download.md +0 -27
  28. package/bios/seabios/docs/Execution_and_code_flow.md +0 -178
  29. package/bios/seabios/docs/Linking_overview.md +0 -160
  30. package/bios/seabios/docs/Mailinglist.md +0 -8
  31. package/bios/seabios/docs/Memory_Model.md +0 -253
  32. package/bios/seabios/docs/README +0 -5
  33. package/bios/seabios/docs/Releases.md +0 -482
  34. package/bios/seabios/docs/Runtime_config.md +0 -193
  35. package/bios/seabios/docs/SeaBIOS.md +0 -17
  36. package/bios/seabios/docs/SeaVGABIOS.md +0 -39
  37. package/bios/seabios/out/autoconf.h +0 -117
  38. package/bios/seabios/out/include/config/acpi/dsdt.h +0 -0
  39. package/bios/seabios/out/include/config/acpi.h +0 -0
  40. package/bios/seabios/out/include/config/ahci.h +0 -0
  41. package/bios/seabios/out/include/config/apmbios.h +0 -0
  42. package/bios/seabios/out/include/config/ata/dma.h +0 -0
  43. package/bios/seabios/out/include/config/ata/pio32.h +0 -0
  44. package/bios/seabios/out/include/config/ata.h +0 -0
  45. package/bios/seabios/out/include/config/auto.conf +0 -69
  46. package/bios/seabios/out/include/config/auto.conf.cmd +0 -9
  47. package/bios/seabios/out/include/config/boot.h +0 -0
  48. package/bios/seabios/out/include/config/bootorder.h +0 -0
  49. package/bios/seabios/out/include/config/build/vgabios.h +0 -0
  50. package/bios/seabios/out/include/config/call32/smm.h +0 -0
  51. package/bios/seabios/out/include/config/cdrom/boot.h +0 -0
  52. package/bios/seabios/out/include/config/cdrom/emu.h +0 -0
  53. package/bios/seabios/out/include/config/debug/level.h +0 -0
  54. package/bios/seabios/out/include/config/drives.h +0 -0
  55. package/bios/seabios/out/include/config/entry/extrastack.h +0 -0
  56. package/bios/seabios/out/include/config/esp/scsi.h +0 -0
  57. package/bios/seabios/out/include/config/flash/floppy.h +0 -0
  58. package/bios/seabios/out/include/config/floppy.h +0 -0
  59. package/bios/seabios/out/include/config/fw/romfile/load.h +0 -0
  60. package/bios/seabios/out/include/config/hardware/irq.h +0 -0
  61. package/bios/seabios/out/include/config/kbd/call/int15/4f.h +0 -0
  62. package/bios/seabios/out/include/config/keyboard.h +0 -0
  63. package/bios/seabios/out/include/config/lpt.h +0 -0
  64. package/bios/seabios/out/include/config/lsi/scsi.h +0 -0
  65. package/bios/seabios/out/include/config/malloc/uppermemory.h +0 -0
  66. package/bios/seabios/out/include/config/megasas.h +0 -0
  67. package/bios/seabios/out/include/config/mouse.h +0 -0
  68. package/bios/seabios/out/include/config/mpt/scsi.h +0 -0
  69. package/bios/seabios/out/include/config/mptable.h +0 -0
  70. package/bios/seabios/out/include/config/mtrr/init.h +0 -0
  71. package/bios/seabios/out/include/config/optionroms.h +0 -0
  72. package/bios/seabios/out/include/config/override/pci/id.h +0 -0
  73. package/bios/seabios/out/include/config/pcibios.h +0 -0
  74. package/bios/seabios/out/include/config/pirtable.h +0 -0
  75. package/bios/seabios/out/include/config/pmm.h +0 -0
  76. package/bios/seabios/out/include/config/pmtimer.h +0 -0
  77. package/bios/seabios/out/include/config/pnpbios.h +0 -0
  78. package/bios/seabios/out/include/config/ps2port.h +0 -0
  79. package/bios/seabios/out/include/config/pvscsi.h +0 -0
  80. package/bios/seabios/out/include/config/qemu/hardware.h +0 -0
  81. package/bios/seabios/out/include/config/qemu.h +0 -0
  82. package/bios/seabios/out/include/config/rom/size.h +0 -0
  83. package/bios/seabios/out/include/config/rtc/timer.h +0 -0
  84. package/bios/seabios/out/include/config/s3/resume.h +0 -0
  85. package/bios/seabios/out/include/config/sdcard.h +0 -0
  86. package/bios/seabios/out/include/config/serial.h +0 -0
  87. package/bios/seabios/out/include/config/tcgbios.h +0 -0
  88. package/bios/seabios/out/include/config/threads.h +0 -0
  89. package/bios/seabios/out/include/config/tristate.conf +0 -4
  90. package/bios/seabios/out/include/config/tsc/timer.h +0 -0
  91. package/bios/seabios/out/include/config/use/smm.h +0 -0
  92. package/bios/seabios/out/include/config/vga/allocate/extra/stack.h +0 -0
  93. package/bios/seabios/out/include/config/vga/bochs/stdvga.h +0 -0
  94. package/bios/seabios/out/include/config/vga/bochs.h +0 -0
  95. package/bios/seabios/out/include/config/vga/did.h +0 -0
  96. package/bios/seabios/out/include/config/vga/extra/stack/size.h +0 -0
  97. package/bios/seabios/out/include/config/vga/fixup/asm.h +0 -0
  98. package/bios/seabios/out/include/config/vga/pci.h +0 -0
  99. package/bios/seabios/out/include/config/vga/stdvga/ports.h +0 -0
  100. package/bios/seabios/out/include/config/vga/vbe.h +0 -0
  101. package/bios/seabios/out/include/config/vga/vid.h +0 -0
  102. package/bios/seabios/out/include/config/vgahooks.h +0 -0
  103. package/bios/seabios/out/include/config/virtio/blk.h +0 -0
  104. package/bios/seabios/out/include/config/virtio/scsi.h +0 -0
  105. package/bios/seabios/out/include/config/xen.h +0 -0
  106. package/bios/seabios/out/scripts/kconfig/conf +0 -0
  107. package/bios/seabios/out/scripts/kconfig/conf.o +0 -0
  108. package/bios/seabios/out/scripts/kconfig/zconf.hash.c +0 -289
  109. package/bios/seabios/out/scripts/kconfig/zconf.lex.c +0 -2420
  110. package/bios/seabios/out/scripts/kconfig/zconf.tab.c +0 -2538
  111. package/bios/seabios/out/scripts/kconfig/zconf.tab.o +0 -0
  112. package/bios/seabios/scripts/acpi_extract.py +0 -366
  113. package/bios/seabios/scripts/acpi_extract_preprocess.py +0 -41
  114. package/bios/seabios/scripts/buildrom.py +0 -56
  115. package/bios/seabios/scripts/buildversion.py +0 -134
  116. package/bios/seabios/scripts/checkrom.py +0 -95
  117. package/bios/seabios/scripts/checkstack.py +0 -226
  118. package/bios/seabios/scripts/checksum.py +0 -16
  119. package/bios/seabios/scripts/encodeint.py +0 -21
  120. package/bios/seabios/scripts/gen-offsets.sh +0 -17
  121. package/bios/seabios/scripts/kconfig/.gitignore +0 -22
  122. package/bios/seabios/scripts/kconfig/Makefile +0 -331
  123. package/bios/seabios/scripts/kconfig/POTFILES.in +0 -12
  124. package/bios/seabios/scripts/kconfig/check.sh +0 -13
  125. package/bios/seabios/scripts/kconfig/conf.c +0 -718
  126. package/bios/seabios/scripts/kconfig/confdata.c +0 -1250
  127. package/bios/seabios/scripts/kconfig/expr.c +0 -1168
  128. package/bios/seabios/scripts/kconfig/expr.h +0 -241
  129. package/bios/seabios/scripts/kconfig/gconf.c +0 -1542
  130. package/bios/seabios/scripts/kconfig/gconf.glade +0 -661
  131. package/bios/seabios/scripts/kconfig/images.c +0 -326
  132. package/bios/seabios/scripts/kconfig/kxgettext.c +0 -235
  133. package/bios/seabios/scripts/kconfig/lex.zconf.c +0 -2430
  134. package/bios/seabios/scripts/kconfig/list.h +0 -131
  135. package/bios/seabios/scripts/kconfig/lkc.h +0 -200
  136. package/bios/seabios/scripts/kconfig/lkc_proto.h +0 -57
  137. package/bios/seabios/scripts/kconfig/lxdialog/.gitignore +0 -4
  138. package/bios/seabios/scripts/kconfig/lxdialog/BIG.FAT.WARNING +0 -4
  139. package/bios/seabios/scripts/kconfig/lxdialog/check-lxdialog.sh +0 -87
  140. package/bios/seabios/scripts/kconfig/lxdialog/checklist.c +0 -332
  141. package/bios/seabios/scripts/kconfig/lxdialog/dialog.h +0 -257
  142. package/bios/seabios/scripts/kconfig/lxdialog/inputbox.c +0 -301
  143. package/bios/seabios/scripts/kconfig/lxdialog/menubox.c +0 -437
  144. package/bios/seabios/scripts/kconfig/lxdialog/textbox.c +0 -408
  145. package/bios/seabios/scripts/kconfig/lxdialog/util.c +0 -713
  146. package/bios/seabios/scripts/kconfig/lxdialog/yesno.c +0 -114
  147. package/bios/seabios/scripts/kconfig/mconf.c +0 -1036
  148. package/bios/seabios/scripts/kconfig/menu.c +0 -697
  149. package/bios/seabios/scripts/kconfig/merge_config.sh +0 -150
  150. package/bios/seabios/scripts/kconfig/nconf.c +0 -1556
  151. package/bios/seabios/scripts/kconfig/nconf.gui.c +0 -656
  152. package/bios/seabios/scripts/kconfig/nconf.h +0 -96
  153. package/bios/seabios/scripts/kconfig/qconf.cc +0 -1795
  154. package/bios/seabios/scripts/kconfig/qconf.h +0 -338
  155. package/bios/seabios/scripts/kconfig/streamline_config.pl +0 -647
  156. package/bios/seabios/scripts/kconfig/symbol.c +0 -1373
  157. package/bios/seabios/scripts/kconfig/util.c +0 -157
  158. package/bios/seabios/scripts/kconfig/zconf.gperf +0 -48
  159. package/bios/seabios/scripts/kconfig/zconf.hash.c_shipped +0 -289
  160. package/bios/seabios/scripts/kconfig/zconf.l +0 -363
  161. package/bios/seabios/scripts/kconfig/zconf.lex.c_shipped +0 -2420
  162. package/bios/seabios/scripts/kconfig/zconf.tab.c_shipped +0 -2538
  163. package/bios/seabios/scripts/kconfig/zconf.y +0 -733
  164. package/bios/seabios/scripts/layoutrom.py +0 -705
  165. package/bios/seabios/scripts/python23compat.py +0 -14
  166. package/bios/seabios/scripts/readserial.py +0 -190
  167. package/bios/seabios/scripts/tarball.sh +0 -36
  168. package/bios/seabios/scripts/test-build.sh +0 -90
  169. package/bios/seabios/scripts/transdump.py +0 -53
  170. package/bios/seabios/scripts/vgafixup.py +0 -96
  171. package/bios/seabios/src/Kconfig +0 -579
  172. package/bios/seabios/src/apm.c +0 -215
  173. package/bios/seabios/src/asm-offsets.c +0 -23
  174. package/bios/seabios/src/biosvar.h +0 -130
  175. package/bios/seabios/src/block.c +0 -623
  176. package/bios/seabios/src/block.h +0 -121
  177. package/bios/seabios/src/bmp.c +0 -117
  178. package/bios/seabios/src/boot.c +0 -793
  179. package/bios/seabios/src/bootsplash.c +0 -255
  180. package/bios/seabios/src/bregs.h +0 -80
  181. package/bios/seabios/src/byteorder.h +0 -71
  182. package/bios/seabios/src/cdrom.c +0 -322
  183. package/bios/seabios/src/clock.c +0 -506
  184. package/bios/seabios/src/code16gcc.s +0 -1
  185. package/bios/seabios/src/config.h +0 -108
  186. package/bios/seabios/src/cp437.c +0 -275
  187. package/bios/seabios/src/cp437.h +0 -1
  188. package/bios/seabios/src/disk.c +0 -779
  189. package/bios/seabios/src/e820map.c +0 -152
  190. package/bios/seabios/src/e820map.h +0 -26
  191. package/bios/seabios/src/entryfuncs.S +0 -165
  192. package/bios/seabios/src/farptr.h +0 -208
  193. package/bios/seabios/src/font.c +0 -139
  194. package/bios/seabios/src/fw/acpi-dsdt-cpu-hotplug.dsl +0 -78
  195. package/bios/seabios/src/fw/acpi-dsdt-dbug.dsl +0 -26
  196. package/bios/seabios/src/fw/acpi-dsdt-hpet.dsl +0 -36
  197. package/bios/seabios/src/fw/acpi-dsdt-isa.dsl +0 -102
  198. package/bios/seabios/src/fw/acpi-dsdt-pci-crs.dsl +0 -90
  199. package/bios/seabios/src/fw/acpi-dsdt.dsl +0 -342
  200. package/bios/seabios/src/fw/acpi-dsdt.hex +0 -554
  201. package/bios/seabios/src/fw/acpi.c +0 -685
  202. package/bios/seabios/src/fw/biostables.c +0 -491
  203. package/bios/seabios/src/fw/coreboot.c +0 -569
  204. package/bios/seabios/src/fw/csm.c +0 -347
  205. package/bios/seabios/src/fw/dev-pci.h +0 -52
  206. package/bios/seabios/src/fw/dev-piix.h +0 -29
  207. package/bios/seabios/src/fw/dev-q35.h +0 -52
  208. package/bios/seabios/src/fw/lzmadecode.c +0 -398
  209. package/bios/seabios/src/fw/lzmadecode.h +0 -67
  210. package/bios/seabios/src/fw/mptable.c +0 -197
  211. package/bios/seabios/src/fw/mtrr.c +0 -105
  212. package/bios/seabios/src/fw/multiboot.c +0 -111
  213. package/bios/seabios/src/fw/paravirt.c +0 -624
  214. package/bios/seabios/src/fw/paravirt.h +0 -63
  215. package/bios/seabios/src/fw/pciinit.c +0 -1187
  216. package/bios/seabios/src/fw/pirtable.c +0 -103
  217. package/bios/seabios/src/fw/q35-acpi-dsdt.dsl +0 -450
  218. package/bios/seabios/src/fw/romfile_loader.c +0 -259
  219. package/bios/seabios/src/fw/romfile_loader.h +0 -91
  220. package/bios/seabios/src/fw/shadow.c +0 -208
  221. package/bios/seabios/src/fw/smbios.c +0 -585
  222. package/bios/seabios/src/fw/smm.c +0 -269
  223. package/bios/seabios/src/fw/smp.c +0 -194
  224. package/bios/seabios/src/fw/ssdt-misc.dsl +0 -104
  225. package/bios/seabios/src/fw/ssdt-misc.hex +0 -88
  226. package/bios/seabios/src/fw/ssdt-pcihp.dsl +0 -36
  227. package/bios/seabios/src/fw/ssdt-pcihp.hex +0 -38
  228. package/bios/seabios/src/fw/ssdt-proc.dsl +0 -48
  229. package/bios/seabios/src/fw/ssdt-proc.hex +0 -35
  230. package/bios/seabios/src/fw/xen.c +0 -149
  231. package/bios/seabios/src/fw/xen.h +0 -125
  232. package/bios/seabios/src/gen-defs.h +0 -19
  233. package/bios/seabios/src/hw/ahci.c +0 -697
  234. package/bios/seabios/src/hw/ahci.h +0 -201
  235. package/bios/seabios/src/hw/ata.c +0 -1046
  236. package/bios/seabios/src/hw/ata.h +0 -163
  237. package/bios/seabios/src/hw/blockcmd.c +0 -372
  238. package/bios/seabios/src/hw/blockcmd.h +0 -114
  239. package/bios/seabios/src/hw/dma.c +0 -67
  240. package/bios/seabios/src/hw/esp-scsi.c +0 -241
  241. package/bios/seabios/src/hw/esp-scsi.h +0 -8
  242. package/bios/seabios/src/hw/floppy.c +0 -741
  243. package/bios/seabios/src/hw/lsi-scsi.c +0 -221
  244. package/bios/seabios/src/hw/lsi-scsi.h +0 -8
  245. package/bios/seabios/src/hw/megasas.c +0 -405
  246. package/bios/seabios/src/hw/megasas.h +0 -8
  247. package/bios/seabios/src/hw/mpt-scsi.c +0 -319
  248. package/bios/seabios/src/hw/mpt-scsi.h +0 -8
  249. package/bios/seabios/src/hw/nvme-int.h +0 -199
  250. package/bios/seabios/src/hw/nvme.c +0 -708
  251. package/bios/seabios/src/hw/nvme.h +0 -17
  252. package/bios/seabios/src/hw/pci.c +0 -133
  253. package/bios/seabios/src/hw/pci.h +0 -47
  254. package/bios/seabios/src/hw/pci_ids.h +0 -2632
  255. package/bios/seabios/src/hw/pci_regs.h +0 -556
  256. package/bios/seabios/src/hw/pcidevice.c +0 -192
  257. package/bios/seabios/src/hw/pcidevice.h +0 -76
  258. package/bios/seabios/src/hw/pic.c +0 -115
  259. package/bios/seabios/src/hw/pic.h +0 -60
  260. package/bios/seabios/src/hw/ps2port.c +0 -543
  261. package/bios/seabios/src/hw/ps2port.h +0 -67
  262. package/bios/seabios/src/hw/pvscsi.c +0 -333
  263. package/bios/seabios/src/hw/pvscsi.h +0 -8
  264. package/bios/seabios/src/hw/ramdisk.c +0 -108
  265. package/bios/seabios/src/hw/rtc.c +0 -100
  266. package/bios/seabios/src/hw/rtc.h +0 -75
  267. package/bios/seabios/src/hw/sdcard.c +0 -572
  268. package/bios/seabios/src/hw/serialio.c +0 -113
  269. package/bios/seabios/src/hw/serialio.h +0 -29
  270. package/bios/seabios/src/hw/timer.c +0 -259
  271. package/bios/seabios/src/hw/tpm_drivers.c +0 -636
  272. package/bios/seabios/src/hw/tpm_drivers.h +0 -127
  273. package/bios/seabios/src/hw/usb-ehci.c +0 -650
  274. package/bios/seabios/src/hw/usb-ehci.h +0 -177
  275. package/bios/seabios/src/hw/usb-hid.c +0 -442
  276. package/bios/seabios/src/hw/usb-hid.h +0 -29
  277. package/bios/seabios/src/hw/usb-hub.c +0 -205
  278. package/bios/seabios/src/hw/usb-hub.h +0 -64
  279. package/bios/seabios/src/hw/usb-msc.c +0 -222
  280. package/bios/seabios/src/hw/usb-msc.h +0 -10
  281. package/bios/seabios/src/hw/usb-ohci.c +0 -568
  282. package/bios/seabios/src/hw/usb-ohci.h +0 -144
  283. package/bios/seabios/src/hw/usb-uas.c +0 -289
  284. package/bios/seabios/src/hw/usb-uas.h +0 -9
  285. package/bios/seabios/src/hw/usb-uhci.c +0 -571
  286. package/bios/seabios/src/hw/usb-uhci.h +0 -128
  287. package/bios/seabios/src/hw/usb-xhci.c +0 -1161
  288. package/bios/seabios/src/hw/usb-xhci.h +0 -133
  289. package/bios/seabios/src/hw/usb.c +0 -499
  290. package/bios/seabios/src/hw/usb.h +0 -254
  291. package/bios/seabios/src/hw/virtio-blk.c +0 -211
  292. package/bios/seabios/src/hw/virtio-blk.h +0 -43
  293. package/bios/seabios/src/hw/virtio-pci.c +0 -501
  294. package/bios/seabios/src/hw/virtio-pci.h +0 -151
  295. package/bios/seabios/src/hw/virtio-ring.c +0 -147
  296. package/bios/seabios/src/hw/virtio-ring.h +0 -121
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@@ -1,253 +0,0 @@
1
- The SeaBIOS code is required to support multiple x86 CPU memory
2
- models. This requirement impacts the code layout and internal storage
3
- of SeaBIOS.
4
-
5
- x86 Memory Models
6
- =================
7
-
8
- The x86 line of CPUs has evolved over many years. The original 8086
9
- chip used 16bit pointers and could only address 1 megabyte of memory.
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- The 80286 CPU still used 16bit pointers, but could address up to 16
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- megabytes of memory. The 80386 chips could process 32bit instructions
12
- and could access up to 4 gigabyte of memory. The most recent x86 chips
13
- can process 64bit instructions and access 16 exabytes of ram.
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-
15
- During the evolution of the x86 CPUs from the 8086 to the 80386 the
16
- BIOS was extended to handle calls in the various modes that the CPU
17
- implemented.
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-
19
- This section outlines the five different x86 CPU execution and memory
20
- access models that SeaBIOS supports.
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-
22
- 16bit real mode
23
- ---------------
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-
25
- This mode is a
26
- [segmented](http://en.wikipedia.org/wiki/Memory_segmentation) memory
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- mode invoked by callers. The CPU defaults to executing 16bit
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- instructions. Callers typically invoke the BIOS by issuing an "int x"
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- instruction which causes a software
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- [interrupt](http://en.wikipedia.org/wiki/Interrupt) that is handled by
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- the BIOS. The SeaBIOS code also handles hardware interrupts in this
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- mode. SeaBIOS can only access the first 1 megabyte of memory in this
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- mode, but it can access any part of that first megabyte.
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-
35
- 16bit bigreal mode
36
- ------------------
37
-
38
- This mode is a segmented memory mode that is used for [option
39
- roms](http://en.wikipedia.org/wiki/Option_ROM). The CPU defaults to
40
- executing 16bit instructions and segmented memory accesses are still
41
- used. However, the segment limits are increased so that the entire
42
- first 4 gigabytes of memory is fully accessible. Callers can invoke
43
- all the [16bit real mode](#16bit_real_mode) functions while in this
44
- mode and can also invoke the Post Memory Manager (PMM) functions that
45
- are available during option rom execution.
46
-
47
- 16bit protected mode
48
- --------------------
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-
50
- CPU execution in this mode is similar to [16bit real
51
- mode](#16bit_real_mode). The CPU defaults to executing 16bit
52
- instructions. However, each segment register indexes a "descriptor
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- table", and it is difficult or impossible to know what the physical
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- address of each segment is. Generally speaking, the BIOS can only
55
- access code and data in the f-segment. The PCIBIOS, APM BIOS, and PNP
56
- BIOS all have documented 16bit protected mode entry points.
57
-
58
- Some old code may attempt to invoke the standard [16bit real
59
- mode](#16bit_real_mode) entry points while in 16bit protected
60
- mode. The PCI BIOS specification explicitly requires that the legacy
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- "int 1a" real mode entry point support 16bit protected mode calls if
62
- they are for the PCI BIOS. Callers of other legacy entry points in
63
- protected mode have not been observed and SeaBIOS does not support
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- them.
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-
66
- 32bit segmented mode
67
- --------------------
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-
69
- In this mode the processor runs in 32bit mode, but the segment
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- registers may have a limit and may have a non-zero offset. In effect,
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- this mode has all of the limitations of [16bit protected
72
- mode](#16bit_protected_mode) - the main difference between the modes
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- is that the processor defaults to executing 32bit instructions. In
74
- addition to these limitations, callers may also run the SeaBIOS code
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- at varying virtual addresses and so the code must support code
76
- relocation. The PCI BIOS specification and APM BIOS specification
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- define 32bit segmented mode interfaces.
78
-
79
- 32bit flat mode
80
- ---------------
81
-
82
- In this mode the processor defaults to executing 32bit instructions,
83
- and all segment registers have an offset of zero and allow access to
84
- the entire first 4 gigabytes of memory. This is the only "sane" mode
85
- for 32bit code - modern compilers and modern operating systems will
86
- generally only support this mode (when running 32bit code).
87
- Ironically, it's the only mode that is not strictly required for a
88
- BIOS to support. SeaBIOS uses this mode internally to support the POST
89
- and BOOT [phases of execution](Execution and code flow).
90
-
91
- code16gcc
92
- =========
93
-
94
- In order to produce code that can run when the processor is in a 16bit
95
- mode, SeaBIOS uses the
96
- [binutils](http://en.wikipedia.org/wiki/GNU_Binutils) ".code16gcc"
97
- assembler flag. This instructs the assembler to emit extra prefix
98
- opcodes so that the 32bit code produced by
99
- [gcc](http://en.wikipedia.org/wiki/GNU_Compiler_Collection) will run
100
- even when the processor is in 16bit mode. Note that gcc always
101
- produces 32bit code - it does not know about the ".code16gcc" flag and
102
- does not know that the code will run in a 16bit mode.
103
-
104
- SeaBIOS uses the same code for all of the 16bit modes ([16bit real
105
- mode](#16bit_real_mode), [16bit bigreal mode](#16bit_bigreal_mode),
106
- and [16bit protected mode](#16bit_protected_mode)) and that code is
107
- assembled using ".code16gcc". SeaBIOS is careful to use segment
108
- registers properly so that the same code can run in the different
109
- 16bit modes that it needs to support.
110
-
111
- C code mode flags
112
- =================
113
-
114
- Two compile time flags are available to determine the memory model the
115
- code is intended for: MODE16 and MODESEGMENT. When compiling for the
116
- 16 bit modes, MODE16 is true and MODESEGMENT is true. In 32bit
117
- segmented mode, MODE16 is false and MODESEGMENT is true. In 32bit flat
118
- mode both MODE16 and MODESEGMENT are false.
119
-
120
- Common memory used at run-time
121
- ==============================
122
-
123
- There are several memory areas that the SeaBIOS "runtime"
124
- [phase](Execution and code flow) makes use of:
125
-
126
- * 0x000000-0x000400: Interrupt descriptor table (IDT). This area
127
- defines 256 interrupt vectors as defined by the Intel CPU
128
- specification for 16bit irq handlers. This area is read/writable at
129
- runtime and can be accessed from 16bit real mode and 16bit bigreal
130
- mode calls. SeaBIOS only uses this area to maintain compatibility
131
- with legacy systems.
132
-
133
- * 0x000400-0x000500: BIOS Data Area (BDA). This area contains various
134
- legacy flags and attributes. The area is read/writable at runtime
135
- and can be accessed from 16bit real mode and 16bit bigreal mode
136
- calls. SeaBIOS only uses this area to maintain compatibility with
137
- legacy systems.
138
-
139
- * 0x09FC00-0x0A0000 (typical): Extended BIOS Data Area (EBDA). This
140
- area contains a few legacy flags and attributes. The area is
141
- typically located at 0x9FC00, but it can be moved by option roms, by
142
- legacy operating systems, and by SeaBIOS if
143
- CONFIG_MALLOC_UPPERMEMORY is not set. Its actual location is
144
- determined by a pointer in the BDA. The area is read/writable at
145
- runtime and can be accessed from 16bit real mode and 16bit bigreal
146
- mode calls. SeaBIOS only uses this area to maintain compatibility
147
- with legacy systems.
148
-
149
- * 0x0E0000-0x0F0000 (typical): "low" memory. This area is used for
150
- custom read/writable storage internal to SeaBIOS. The area is
151
- read/writable at runtime and can be accessed from 16bit real mode
152
- and 16bit bigreal mode calls. The area is typically located at the
153
- end of the e-segment, but the build may position it anywhere in the
154
- 0x0C0000-0x0F0000 region. However, if CONFIG_MALLOC_UPPERMEMORY is
155
- not set, then this region is between 0x090000-0x0A0000. Space is
156
- allocated in this region by either marking a global variable with
157
- the "VARLOW" flag or by calling malloc_low() during
158
- initialization. The area can be grown dynamically (via malloc_low),
159
- but it will never exceed 64K.
160
-
161
- * 0x0F0000-0x100000: The BIOS segment. This area is used for both
162
- runtime code and static variables. Space is allocated in this region
163
- by either marking a global variable with VAR16, one of the VARFSEG
164
- flags, or by calling malloc_fseg() during initialization. The area
165
- is read-only at runtime and can be accessed from 16bit real mode,
166
- 16bit bigreal mode, 16bit protected mode, and 32bit segmented mode
167
- calls.
168
-
169
- All of the above areas are also read/writable during the SeaBIOS
170
- initialization phase and are accessible when in 32bit flat mode.
171
-
172
- Segmented mode memory access
173
- ============================
174
-
175
- The assembler entry functions for segmented mode calls (all modes
176
- except [32bit flat mode](#32bit_flat_mode)) will arrange
177
- to set the data segment (%ds) to be the same as the stack segment
178
- (%ss) before calling any C code. This permits all C variables located
179
- on the stack and C pointers to data located on the stack to work as
180
- normal.
181
-
182
- However, all code running in segmented mode must wrap non-stack memory
183
- accesses in special macros. These macros ensure the correct segment
184
- register is used. Failure to use the correct macro will result in an
185
- incorrect memory access that will likely cause hard to find errors.
186
-
187
- There are three low-level memory access macros:
188
-
189
- * GET_VAR / SET_VAR : Accesses a variable using the specified segment
190
- register. This isn't typically used directly by C code.
191
-
192
- * GET_FARVAR / SET_FARVAR : Assigns the extra segment (%es) to the
193
- given segment id and then performs the given memory access via %es.
194
-
195
- * GET_FLATPTR / SET_FLATPTR : These macros take a 32bit pointer,
196
- construct a segment/offset pair valid in real mode, and then perform
197
- the given access. These macros must not be used in 16bit protected
198
- mode or 32bit segmented mode.
199
-
200
- Since most memory accesses are to [common memory used at
201
- run-time](#Common_memory_used_at_run-time), several helper
202
- macros are also available.
203
-
204
- * GET_IDT / SET_IDT : Access the interrupt descriptor table (IDT).
205
-
206
- * GET_BDA / SET_BDA : Access the BIOS Data Area (BDA).
207
-
208
- * GET_EBDA / SET_EBDA : Access the Extended BIOS Data Area (EBDA).
209
-
210
- * GET_LOW / SET_LOW : Access internal variables marked with
211
- VARLOW. (There are also related macros GET_LOWFLAT / SET_LOWFLAT for
212
- accessing storage allocated with malloc_low.)
213
-
214
- * GET_GLOBAL : Access internal variables marked with the VAR16 or
215
- VARFSEG flags. (There is also the related macro GET_GLOBALFLAT for
216
- accessing storage allocated with malloc_fseg.)
217
-
218
- Memory available during initialization
219
- ======================================
220
-
221
- During the POST [phase](Execution and code flow) the code
222
- can fully access the first 4 gigabytes of memory. However, memory
223
- accesses are generally limited to the [common memory used at
224
- run-time](#Common_memory_used_at_run-time) and areas
225
- allocated at runtime via one of the malloc calls:
226
-
227
- * malloc_high : Permanent high-memory zone. This area is used for
228
- custom read/writable storage internal to SeaBIOS. The area is
229
- located at the top of the first 4 gigabytes of ram. It is commonly
230
- used for storing standard tables accessed by the operating system at
231
- runtime (ACPI, SMBIOS, and MPTable) and for DMA buffers used by
232
- hardware drivers. The area is read/writable at runtime and an entry
233
- in the e820 memory map is used to reserve it. When running on an
234
- emulator that has only 1 megabyte of ram this zone will be empty.
235
-
236
- * malloc_tmphigh : Temporary high-memory zone. This area is used for
237
- custom read/writable storage during the SeaBIOS initialization
238
- phase. The area generally starts after the first 1 megabyte of ram
239
- (0x100000) and ends prior to the Permanent high-memory zone. When
240
- running on an emulator that has only 1 megabyte of ram this zone
241
- will be empty. The area is not reserved from the operating system,
242
- so it must not be accessed after the SeaBIOS initialization phase.
243
-
244
- * malloc_tmplow : Temporary low-memory zone. This area is used for
245
- custom read/writable storage during the SeaBIOS initialization
246
- phase. The area resides between 0x07000-0x90000. The area is not
247
- reserved from the operating system and by specification it is
248
- required to be zero'd at the end of the initialization phase.
249
-
250
- The "tmplow" and "tmphigh" regions are only available during the
251
- initialization phase. Any access (either read or write) after
252
- completion of the initialization phase can result in difficult to find
253
- errors.
@@ -1,5 +0,0 @@
1
- This directory contains SeaBIOS documentation as found on the SeaBIOS
2
- wiki. All the files in this directory (with the exclusion of this
3
- README file) correspond to a page on the wiki.
4
-
5
- The documentation files use markdown syntax.