v86 0.3.4 → 0.3.7

package/bios/seabios/src/hw/mpt-scsi.c

@@ -0,0 +1,319 @@
+// MPT Fusion boot support.
+//
+// Copyright (c) 2012 Verizon, Inc.
+// Copyright (C) 2016 Paolo Bonzini <pbonzini@redhat.com>
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#include "biosvar.h" // GET_GLOBALFLAT
+#include "block.h" // struct drive_s
+#include "blockcmd.h" // scsi_drive_setup
+#include "config.h" // CONFIG_*
+#include "fw/paravirt.h" // runningOnQEMU
+#include "malloc.h" // free
+#include "output.h" // dprintf
+#include "pcidevice.h" // foreachpci
+#include "pci_ids.h" // PCI_DEVICE_ID
+#include "pci_regs.h" // PCI_VENDOR_ID
+#include "stacks.h" // run_thread
+#include "std/disk.h" // DISK_RET_SUCCESS
+#include "string.h" // memset
+#include "util.h" // usleep
+
+#define MPT_REG_DOORBELL  0x00
+#define MPT_REG_WRITE_SEQ 0x04
+#define MPT_REG_HOST_DIAG 0x08
+#define MPT_REG_TEST      0x0c
+#define MPT_REG_DIAG_DATA 0x10
+#define MPT_REG_DIAG_ADDR 0x14
+#define MPT_REG_ISTATUS   0x30
+#define MPT_REG_IMASK     0x34
+#define MPT_REG_REQ_Q     0x40
+#define MPT_REG_REP_Q     0x44
+
+#define MPT_DOORBELL_MSG_RESET 0x40
+#define MPT_DOORBELL_HANDSHAKE 0x42
+
+#define MPT_IMASK_DOORBELL 0x01
+#define MPT_IMASK_REPLY    0x08
+
+struct mpt_lun_s {
+    struct drive_s drive;
+    struct pci_device *pci;
+    u32 iobase;
+    u8 target;
+    u8 lun;
+};
+
+u8 reply_msg[4] __attribute((aligned(4))) VARLOW;
+
+#define MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST        (0x00)
+#define MPT_MESSAGE_HDR_FUNCTION_IOC_INIT               (0x02)
+
+static struct MptIOCInitRequest
+{
+    u8     WhoInit;             /* Which system sent this init request. */
+    u8     Reserved1;           /* Reserved */
+    u8     ChainOffset;         /* Chain offset in the SG list. */
+    u8     Function;            /* Function to execute. */
+    u8     Flags;               /* Flags */
+    u8     MaxDevices;          /* Max devices the driver can handle. */
+    u8     MaxBuses;            /* Max buses the driver can handle. */
+    u8     MessageFlags;        /* Message flags. */
+    u32    MessageContext;      /* Message context ID. */
+    u16    ReplyFrameSize;      /* Reply frame size. */
+    u16    Reserved2;           /* Reserved */
+    u32    HostMfaHighAddr;     /* Upper 32bit of the message frames. */
+    u32    SenseBufferHighAddr; /* Upper 32bit of the sense buffer. */
+} MptIOCInitRequest = {
+    .WhoInit = 2,
+    .Function = MPT_MESSAGE_HDR_FUNCTION_IOC_INIT,
+    .MaxDevices = 8,
+    .MaxBuses = 1,
+    .ReplyFrameSize = sizeof(reply_msg),
+    .HostMfaHighAddr = 0,
+    .SenseBufferHighAddr = 0
+};
+
+struct MptIOCInitReply {
+    u8     WhoInit;     /* Which subsystem sent this init request. */
+    u8     Reserved1;   /* Reserved */
+    u8     MessageLength; /* Message length */
+    u8     Function;    /* Function. */
+    u8     Flags;       /* Flags */
+    u8     MaxDevices;  /* Maximum number of devices the driver can handle. */
+    u8     MaxBuses;    /* Maximum number of busses the driver can handle. */
+    u8     MessageFlags; /* Message flags. */
+    u32    MessageContext; /* Message context ID */
+    u16    Reserved2;   /* Reserved */
+    u16    IOCStatus;   /* IO controller status. */
+    u32    IOCLogInfo;  /* IO controller log information. */
+};
+
+typedef struct MptSCSIIORequest {
+    u8     TargetID;            /* Target ID */
+    u8     Bus;                 /* Bus number */
+    u8     ChainOffset;         /* Chain offset */
+    u8     Function;            /* Function number. */
+    u8     CDBLength;           /* CDB length. */
+    u8     SenseBufferLength;   /* Sense buffer length. */
+    u8     Reserved;            /* Reserved */
+    u8     MessageFlags;        /* Message flags. */
+    u32    MessageContext;      /* Message context ID. */
+    u8     LUN[8];              /* LUN */
+    u32    Control;             /* Control values. */
+    u8     CDB[16];             /* The CDB. */
+    u32    DataLength;          /* Data length. */
+    u32    SenseBufferLowAddr;  /* Sense buffer low 32bit address. */
+} __attribute__((packed)) MptSCSIIORequest_t;
+
+#define MPT_POLL_TIMEOUT  60000
+
+typedef struct MptSGEntrySimple32 {
+    u32 FlagsLength;
+    u32 DataBufferAddressLow;
+} __attribute__((packed)) MptSGEntrySimple32_t;
+
+static int
+mpt_scsi_cmd(u32 iobase, struct disk_op_s *op,
+             u8 *cdb, u16 target, u16 lun, u16 blocksize)
+{
+    u32 end = timer_calc(MPT_POLL_TIMEOUT);
+
+    u8 sense_buf[18];
+    struct scsi_req {
+        MptSCSIIORequest_t      scsi_io;
+        MptSGEntrySimple32_t    sge;
+    } __attribute__((packed, aligned(4))) req = {
+        .scsi_io = {
+            .TargetID = target,
+            .Bus = 0,
+            .Function = MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST,
+            .CDBLength = 16,
+            .SenseBufferLength = 18,
+            .MessageContext = end & 0x7fffffff,
+            .DataLength = op->count * blocksize,
+            .SenseBufferLowAddr = (u32)MAKE_FLATPTR(GET_SEG(SS), &sense_buf[0]),
+        },
+        .sge = {
+            /* end of list, simple entry, end of buffer, last element */
+            .FlagsLength = (op->count * blocksize) | 0xD1000000,
+            .DataBufferAddressLow = (u32)op->buf_fl,
+        }
+    };
+
+    req.scsi_io.LUN[1] = lun;
+    memcpy(req.scsi_io.CDB, cdb, 16);
+    if (blocksize) {
+        if (scsi_is_read(op)) {
+            req.scsi_io.Control = 2 << 24;
+        } else {
+            req.scsi_io.Control = 1 << 24;
+            req.sge.FlagsLength |= 0x04000000;
+        }
+    }
+
+    outl((u32)MAKE_FLATPTR(GET_SEG(SS), &req), iobase + MPT_REG_REQ_Q);
+
+    for (;;) {
+        if (timer_check(end)) {
+            return DISK_RET_ETIMEOUT;
+        }
+
+        u32 istatus = inl(iobase + MPT_REG_ISTATUS);
+        if (istatus & MPT_IMASK_REPLY) {
+            u32 resp = inl(iobase + MPT_REG_REP_Q);
+            /* another read to turn interrupt off */
+            inl(iobase + MPT_REG_REP_Q);
+            if (resp == req.scsi_io.MessageContext) {
+                return DISK_RET_SUCCESS;
+            } else if (resp & 0x80000000) {
+                outl((u32)&reply_msg[0], iobase + MPT_REG_REP_Q);
+                return DISK_RET_EBADTRACK;
+            }
+        }
+        usleep(50);
+    }
+}
+
+int
+mpt_scsi_process_op(struct disk_op_s *op)
+{
+    if (!CONFIG_MPT_SCSI)
+        return DISK_RET_EBADTRACK;
+
+    u8 cdbcmd[16];
+    int blocksize = scsi_fill_cmd(op, cdbcmd, sizeof(cdbcmd));
+    if (blocksize < 0)
+        return default_process_op(op);
+
+    struct mpt_lun_s *llun_gf =
+        container_of(op->drive_fl, struct mpt_lun_s, drive);
+    u16 target = GET_GLOBALFLAT(llun_gf->target);
+    u16 lun = GET_GLOBALFLAT(llun_gf->lun);
+    u32 iobase = GET_GLOBALFLAT(llun_gf->iobase);
+    return mpt_scsi_cmd(iobase, op, cdbcmd, target, lun, blocksize);
+}
+
+static void
+mpt_scsi_init_lun(struct mpt_lun_s *llun, struct pci_device *pci,
+                  u32 iobase, u8 target, u8 lun)
+{
+    memset(llun, 0, sizeof(*llun));
+    llun->drive.type = DTYPE_MPT_SCSI;
+    llun->drive.cntl_id = pci->bdf;
+    llun->pci = pci;
+    llun->target = target;
+    llun->lun = lun;
+    llun->iobase = iobase;
+}
+
+static int
+mpt_scsi_add_lun(u32 lun, struct drive_s *tmpl_drv)
+{
+    struct mpt_lun_s *tmpl_llun =
+        container_of(tmpl_drv, struct mpt_lun_s, drive);
+    struct mpt_lun_s *llun = malloc_fseg(sizeof(*llun));
+    if (!llun) {
+        warn_noalloc();
+        return -1;
+    }
+    mpt_scsi_init_lun(llun, tmpl_llun->pci, tmpl_llun->iobase,
+                      tmpl_llun->target, lun);
+
+    char *name = znprintf(MAXDESCSIZE, "mpt %pP %d:%d",
+                          llun->pci, llun->target, llun->lun);
+    int prio = bootprio_find_scsi_device(llun->pci, llun->target, llun->lun);
+    int ret = scsi_drive_setup(&llun->drive, name, prio);
+    free(name);
+    if (ret) {
+        goto fail;
+    }
+    return 0;
+
+fail:
+    free(llun);
+    return -1;
+}
+
+static void
+mpt_scsi_scan_target(struct pci_device *pci, u32 iobase, u8 target)
+{
+    struct mpt_lun_s llun0;
+
+    mpt_scsi_init_lun(&llun0, pci, iobase, target, 0);
+
+    if (scsi_rep_luns_scan(&llun0.drive, mpt_scsi_add_lun) < 0)
+        scsi_sequential_scan(&llun0.drive, 8, mpt_scsi_add_lun);
+}
+
+static inline void
+mpt_out_doorbell(u8 func, u8 arg, u16 iobase)
+{
+    outl((func << 24) | (arg << 16), iobase + MPT_REG_DOORBELL);
+}
+
+static void
+init_mpt_scsi(void *data)
+{
+    struct pci_device *pci = data;
+    u16 *msg_in_p;
+    u32 iobase = pci_enable_iobar(pci, PCI_BASE_ADDRESS_0);
+    if (!iobase)
+        return;
+    struct MptIOCInitReply MptIOCInitReply;
+    pci_enable_busmaster(pci);
+
+    dprintf(1, "found mpt-scsi(%04x) at %pP, io @ %x\n"
+            , pci->device, pci, iobase);
+
+    // reset
+    mpt_out_doorbell(MPT_DOORBELL_MSG_RESET, 0, iobase);
+    outl(MPT_IMASK_DOORBELL|MPT_IMASK_REPLY , iobase + MPT_REG_IMASK);
+    outl(0, iobase + MPT_REG_ISTATUS);
+
+    // send IOC Init message through the doorbell
+    mpt_out_doorbell(MPT_DOORBELL_HANDSHAKE,
+                     sizeof(MptIOCInitRequest)/sizeof(u32),
+                     iobase);
+
+    outsl(iobase + MPT_REG_DOORBELL,
+          (u32 *)&MptIOCInitRequest,
+          sizeof(MptIOCInitRequest)/sizeof(u32));
+
+    // Read the reply 16 bits at a time.  Cannot use insl
+    // because the port is 32 bits wide.
+    msg_in_p = (u16 *)&MptIOCInitReply;
+    while(msg_in_p != (u16 *)(&MptIOCInitReply + 1))
+        *msg_in_p++ = (u16)inl(iobase + MPT_REG_DOORBELL);
+
+    // Eat doorbell interrupt
+    outl(0, iobase + MPT_REG_ISTATUS);
+
+    // Post reply message used for SCSI errors
+    outl((u32)&reply_msg[0], iobase + MPT_REG_REP_Q);
+
+    int i;
+    for (i = 0; i < 7; i++)
+        mpt_scsi_scan_target(pci, iobase, i);
+}
+
+void
+mpt_scsi_setup(void)
+{
+    ASSERT32FLAT();
+    if (!CONFIG_MPT_SCSI || !runningOnQEMU()) {
+        return;
+    }
+
+    dprintf(3, "init MPT\n");
+
+    struct pci_device *pci;
+    foreachpci(pci) {
+        if (pci->vendor == PCI_VENDOR_ID_LSI_LOGIC
+            && (pci->device == PCI_DEVICE_ID_LSI_53C1030
+                || pci->device == PCI_DEVICE_ID_LSI_SAS1068
+                || pci->device == PCI_DEVICE_ID_LSI_SAS1068E))
+            run_thread(init_mpt_scsi, pci);
+    }
+}

package/bios/seabios/src/hw/mpt-scsi.h

@@ -0,0 +1,8 @@
+#ifndef __MPT_SCSI_H
+#define __MPT_SCSI_H
+
+struct disk_op_s;
+int mpt_scsi_process_op(struct disk_op_s *op);
+void mpt_scsi_setup(void);
+
+#endif /* __MPT_SCSI_H */

package/bios/seabios/src/hw/nvme-int.h

@@ -0,0 +1,199 @@
+// NVMe datastructures and constants
+//
+// Copyright 2017 Amazon.com, Inc. or its affiliates.
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#ifndef __NVME_INT_H
+#define __NVME_INT_H
+
+#include "types.h" // u32
+#include "pcidevice.h" // struct pci_device
+
+/* Data structures */
+
+/* The register file of a NVMe host controller. This struct follows the naming
+   scheme in the NVMe specification. */
+struct nvme_reg {
+    u64 cap;                    /* controller capabilities */
+    u32 vs;                     /* version */
+    u32 intms;                  /* interrupt mask set */
+    u32 intmc;                  /* interrupt mask clear */
+    u32 cc;                     /* controller configuration */
+    u32 _res0;
+    u32 csts;                   /* controller status */
+    u32 _res1;
+    u32 aqa;                    /* admin queue attributes */
+    u64 asq;                    /* admin submission queue base address */
+    u64 acq;                    /* admin completion queue base address */
+};
+
+/* Submission queue entry */
+struct nvme_sqe {
+    union {
+        u32 dword[16];
+        struct {
+            u32 cdw0;           /* Command DWORD 0 */
+            u32 nsid;           /* Namespace ID */
+            u64 _res0;
+            u64 mptr;           /* metadata ptr */
+
+            u64 dptr_prp1;
+            u64 dptr_prp2;
+        };
+    };
+};
+
+/* Completion queue entry */
+struct nvme_cqe {
+    union {
+        u32 dword[4];
+        struct {
+            u32 cdw0;
+            u32 _res0;
+            u16 sq_head;
+            u16 sq_id;
+            u16 cid;
+            u16 status;
+        };
+    };
+};
+
+/* The common part of every submission or completion queue. */
+struct nvme_queue {
+    u32 *dbl;                   /* doorbell */
+    u16 mask;                   /* length - 1 */
+};
+
+struct nvme_cq {
+    struct nvme_queue common;
+    struct nvme_cqe *cqe;
+
+    /* We have read upto (but not including) this entry in the queue. */
+    u16 head;
+
+    /* The current phase bit the controller uses to indicate that it has written
+       a new entry. This is inverted after each wrap. */
+    unsigned phase : 1;
+};
+
+struct nvme_sq {
+    struct nvme_queue common;
+    struct nvme_sqe *sqe;
+
+    /* Corresponding completion queue. We only support a single SQ per CQ. */
+    struct nvme_cq *cq;
+
+    /* The last entry the controller has fetched. */
+    u16 head;
+
+    /* The last value we have written to the tail doorbell. */
+    u16 tail;
+};
+
+struct nvme_ctrl {
+    struct pci_device *pci;
+    struct nvme_reg volatile *reg;
+
+    u32 doorbell_stride;        /* in bytes */
+
+    struct nvme_sq admin_sq;
+    struct nvme_cq admin_cq;
+
+    u32 ns_count;
+    struct nvme_namespace *ns;
+
+    struct nvme_sq io_sq;
+    struct nvme_cq io_cq;
+};
+
+struct nvme_namespace {
+    struct drive_s drive;
+    struct nvme_ctrl *ctrl;
+
+    u32 ns_id;
+
+    u64 lba_count;              /* The total amount of sectors. */
+
+    u32 block_size;
+    u32 metadata_size;
+
+    /* Page aligned buffer of size NVME_PAGE_SIZE. */
+    char *dma_buffer;
+};
+
+/* Data structures for NVMe admin identify commands */
+
+struct nvme_identify_ctrl {
+    u16 vid;
+    u16 ssvid;
+    char sn[20];
+    char mn[40];
+    char fr[8];
+
+    char _boring[516 - 72];
+
+    u32 nn;                     /* number of namespaces */
+};
+
+struct nvme_identify_ns_list {
+    u32 ns_id[1024];
+};
+
+struct nvme_lba_format {
+    u16 ms;
+    u8  lbads;
+    u8  rp;
+    u8  res;
+};
+
+struct nvme_identify_ns {
+    u64 nsze;
+    u64 ncap;
+    u64 nuse;
+    u8  nsfeat;
+    u8  nlbaf;
+    u8  flbas;
+
+    char _boring[128 - 27];
+
+    struct nvme_lba_format lbaf[16];
+};
+
+union nvme_identify {
+    struct nvme_identify_ns      ns;
+    struct nvme_identify_ctrl    ctrl;
+    struct nvme_identify_ns_list ns_list;
+};
+
+/* NVMe constants */
+
+#define NVME_CAP_CSS_NVME (1ULL << 37)
+
+#define NVME_CSTS_FATAL   (1U <<  1)
+#define NVME_CSTS_RDY     (1U <<  0)
+
+#define NVME_CC_EN        (1U <<  0)
+
+#define NVME_SQE_OPC_ADMIN_CREATE_IO_SQ 1U
+#define NVME_SQE_OPC_ADMIN_CREATE_IO_CQ 5U
+#define NVME_SQE_OPC_ADMIN_IDENTIFY     6U
+
+#define NVME_SQE_OPC_IO_WRITE 1U
+#define NVME_SQE_OPC_IO_READ  2U
+
+#define NVME_ADMIN_IDENTIFY_CNS_ID_NS       0U
+#define NVME_ADMIN_IDENTIFY_CNS_ID_CTRL     1U
+#define NVME_ADMIN_IDENTIFY_CNS_GET_NS_LIST 2U
+
+#define NVME_CQE_DW3_P (1U << 16)
+
+#define NVME_PAGE_SIZE 4096
+
+/* Length for the queue entries. */
+#define NVME_SQE_SIZE_LOG 6
+#define NVME_CQE_SIZE_LOG 4
+
+#endif
+
+/* EOF */