v86 0.3.4 → 0.3.7

package/bios/seabios/src/fw/smm.c

@@ -0,0 +1,269 @@
+// System Management Mode support (on emulators)
+//
+// Copyright (C) 2008-2014  Kevin O'Connor <kevin@koconnor.net>
+// Copyright (C) 2006 Fabrice Bellard
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#include "config.h" // CONFIG_*
+#include "dev-q35.h"
+#include "dev-piix.h"
+#include "hw/pci.h" // pci_config_writel
+#include "hw/pcidevice.h" // pci_find_device
+#include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
+#include "hw/pci_regs.h" // PCI_DEVICE_ID
+#include "output.h" // dprintf
+#include "paravirt.h" // PORT_SMI_STATUS
+#include "stacks.h" // HaveSmmCall32
+#include "string.h" // memcpy
+#include "util.h" // smm_setup
+#include "x86.h" // wbinvd
+
+/*
+ * Check SMM state save area format (bits 0-15) and require support
+ * for SMBASE relocation.
+ */
+#define SMM_REV_MASK 0x0002ffff
+
+#define SMM_REV_I32  0x00020000
+#define SMM_REV_I64  0x00020064
+
+struct smm_state {
+    union {
+        struct {
+            u8 pad_000[0xf8];
+            u32 smm_base;
+            u32 smm_rev;
+            u8 pad_100[0xd0];
+            u32 eax, ecx, edx, ebx, esp, ebp, esi, edi, eip, eflags;
+            u8 pad_1f8[0x08];
+        } i32;
+        struct {
+            u8 pad_000[0xfc];
+            u32 smm_rev;
+            u32 smm_base;
+            u8 pad_104[0x6c];
+            u64 rflags, rip, r15, r14, r13, r12, r11, r10, r9, r8;
+            u64 rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax;
+        } i64;
+    };
+};
+
+struct smm_layout {
+    struct smm_state backup1;
+    struct smm_state backup2;
+    u32 backup_a20;
+    u8 stack[0x8000 - sizeof(struct smm_state)*2 - sizeof(u32)];
+    u64 codeentry;
+    u8 pad_8008[0x7df8];
+    struct smm_state cpu;
+};
+
+void VISIBLE32FLAT
+handle_smi(u16 cs)
+{
+    if (!CONFIG_USE_SMM)
+        return;
+    u8 cmd = inb(PORT_SMI_CMD);
+    struct smm_layout *smm = MAKE_FLATPTR(cs, 0);
+    u32 rev = smm->cpu.i32.smm_rev & SMM_REV_MASK;
+    dprintf(DEBUG_HDL_smi, "handle_smi cmd=%x smbase=%p\n", cmd, smm);
+
+    if (smm == (void*)BUILD_SMM_INIT_ADDR) {
+        // relocate SMBASE to 0xa0000
+        if (rev == SMM_REV_I32) {
+            smm->cpu.i32.smm_base = BUILD_SMM_ADDR;
+        } else if (rev == SMM_REV_I64) {
+            smm->cpu.i64.smm_base = BUILD_SMM_ADDR;
+        } else {
+            warn_internalerror();
+            return;
+        }
+        // indicate to smm_relocate_and_restore() that the SMM code was executed
+        outb(0x00, PORT_SMI_STATUS);
+
+        if (CONFIG_CALL32_SMM) {
+            // Backup current cpu state for SMM trampolining
+            struct smm_layout *newsmm = (void*)BUILD_SMM_ADDR;
+            memcpy(&newsmm->backup1, &smm->cpu, sizeof(newsmm->backup1));
+            memcpy(&newsmm->backup2, &smm->cpu, sizeof(newsmm->backup2));
+            HaveSmmCall32 = 1;
+        }
+
+        return;
+    }
+
+    if (CONFIG_CALL32_SMM && cmd == CALL32SMM_CMDID) {
+        if (rev == SMM_REV_I32) {
+            u32 regs[8];
+            memcpy(regs, &smm->cpu.i32.eax, sizeof(regs));
+            if (smm->cpu.i32.ecx == CALL32SMM_ENTERID) {
+                dprintf(9, "smm cpu call pc=%x esp=%x\n", regs[3], regs[4]);
+                memcpy(&smm->backup2, &smm->cpu, sizeof(smm->backup2));
+                memcpy(&smm->cpu, &smm->backup1, sizeof(smm->cpu));
+                memcpy(&smm->cpu.i32.eax, regs, sizeof(regs));
+                smm->cpu.i32.eip = regs[3];
+                // Enable a20 and backup its previous state
+                smm->backup_a20 = set_a20(1);
+            } else if (smm->cpu.i32.ecx == CALL32SMM_RETURNID) {
+                dprintf(9, "smm cpu ret %x esp=%x\n", regs[3], regs[4]);
+                memcpy(&smm->cpu, &smm->backup2, sizeof(smm->cpu));
+                memcpy(&smm->cpu.i32.eax, regs, sizeof(regs));
+                if (!smm->backup_a20)
+                    set_a20(0);
+                smm->cpu.i32.eip = regs[3];
+            }
+        } else if (rev == SMM_REV_I64) {
+            u64 regs[8];
+            memcpy(regs, &smm->cpu.i64.rdi, sizeof(regs));
+            if ((u32)smm->cpu.i64.rcx == CALL32SMM_ENTERID) {
+                memcpy(&smm->backup2, &smm->cpu, sizeof(smm->backup2));
+                memcpy(&smm->cpu, &smm->backup1, sizeof(smm->cpu));
+                memcpy(&smm->cpu.i64.rdi, regs, sizeof(regs));
+                smm->cpu.i64.rip = (u32)regs[4];
+                // Enable a20 and backup its previous state
+                smm->backup_a20 = set_a20(1);
+            } else if ((u32)smm->cpu.i64.rcx == CALL32SMM_RETURNID) {
+                memcpy(&smm->cpu, &smm->backup2, sizeof(smm->cpu));
+                memcpy(&smm->cpu.i64.rdi, regs, sizeof(regs));
+                if (!smm->backup_a20)
+                    set_a20(0);
+                smm->cpu.i64.rip = (u32)regs[4];
+            }
+        }
+    }
+}
+
+extern void entry_smi(void);
+// movw %cs, %ax; ljmpw $SEG_BIOS, $(entry_smi - BUILD_BIOS_ADDR)
+#define SMI_INSN (0xeac88c | ((u64)SEG_BIOS<<40) \
+                  | ((u64)((u32)entry_smi - BUILD_BIOS_ADDR) << 24))
+
+static void
+smm_save_and_copy(void)
+{
+    // save original memory content
+    struct smm_layout *initsmm = (void*)BUILD_SMM_INIT_ADDR;
+    struct smm_layout *smm = (void*)BUILD_SMM_ADDR;
+    memcpy(&smm->cpu, &initsmm->cpu, sizeof(smm->cpu));
+    memcpy(&smm->codeentry, &initsmm->codeentry, sizeof(smm->codeentry));
+
+    // Setup code entry point.
+    initsmm->codeentry = SMI_INSN;
+}
+
+static void
+smm_relocate_and_restore(void)
+{
+    /* init APM status port */
+    outb(0x01, PORT_SMI_STATUS);
+
+    /* raise an SMI interrupt */
+    outb(0x00, PORT_SMI_CMD);
+
+    /* wait until SMM code executed */
+    while (inb(PORT_SMI_STATUS) != 0x00)
+        ;
+
+    /* restore original memory content */
+    struct smm_layout *initsmm = (void*)BUILD_SMM_INIT_ADDR;
+    struct smm_layout *smm = (void*)BUILD_SMM_ADDR;
+    memcpy(&initsmm->cpu, &smm->cpu, sizeof(initsmm->cpu));
+    memcpy(&initsmm->codeentry, &smm->codeentry, sizeof(initsmm->codeentry));
+
+    // Setup code entry point.
+    smm->codeentry = SMI_INSN;
+    wbinvd();
+}
+
+// This code is hardcoded for PIIX4 Power Management device.
+static void piix4_apmc_smm_setup(int isabdf, int i440_bdf)
+{
+    /* check if SMM init is already done */
+    u32 value = pci_config_readl(isabdf, PIIX_DEVACTB);
+    if (value & PIIX_DEVACTB_APMC_EN)
+        return;
+
+    /* enable the SMM memory window */
+    pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x48);
+
+    smm_save_and_copy();
+
+    /* enable SMI generation when writing to the APMC register */
+    pci_config_writel(isabdf, PIIX_DEVACTB, value | PIIX_DEVACTB_APMC_EN);
+
+    /* enable SMI generation */
+    value = inl(acpi_pm_base + PIIX_PMIO_GLBCTL);
+    outl(value | PIIX_PMIO_GLBCTL_SMI_EN, acpi_pm_base + PIIX_PMIO_GLBCTL);
+
+    smm_relocate_and_restore();
+
+    /* close the SMM memory window and enable normal SMM */
+    pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x08);
+}
+
+/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
+void ich9_lpc_apmc_smm_setup(int isabdf, int mch_bdf)
+{
+    /* check if SMM init is already done */
+    u32 value = inl(acpi_pm_base + ICH9_PMIO_SMI_EN);
+    if (value & ICH9_PMIO_SMI_EN_APMC_EN)
+        return;
+
+    /* enable the SMM memory window */
+    pci_config_writeb(mch_bdf, Q35_HOST_BRIDGE_SMRAM, 0x02 | 0x48);
+
+    smm_save_and_copy();
+
+    /* enable SMI generation when writing to the APMC register */
+    outl(value | ICH9_PMIO_SMI_EN_APMC_EN | ICH9_PMIO_SMI_EN_GLB_SMI_EN,
+         acpi_pm_base + ICH9_PMIO_SMI_EN);
+
+    /* lock SMI generation */
+    value = pci_config_readw(isabdf, ICH9_LPC_GEN_PMCON_1);
+    pci_config_writel(isabdf, ICH9_LPC_GEN_PMCON_1,
+                      value | ICH9_LPC_GEN_PMCON_1_SMI_LOCK);
+
+    smm_relocate_and_restore();
+
+    /* close the SMM memory window and enable normal SMM */
+    pci_config_writeb(mch_bdf, Q35_HOST_BRIDGE_SMRAM, 0x02 | 0x08);
+}
+
+static int SMMISADeviceBDF = -1, SMMPMDeviceBDF = -1;
+
+void
+smm_device_setup(void)
+{
+    if (!CONFIG_USE_SMM)
+        return;
+
+    struct pci_device *isapci, *pmpci;
+    isapci = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3);
+    pmpci = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
+    if (isapci && pmpci) {
+        SMMISADeviceBDF = isapci->bdf;
+        SMMPMDeviceBDF = pmpci->bdf;
+        return;
+    }
+    isapci = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC);
+    pmpci = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH);
+    if (isapci && pmpci) {
+        SMMISADeviceBDF = isapci->bdf;
+        SMMPMDeviceBDF = pmpci->bdf;
+    }
+}
+
+void
+smm_setup(void)
+{
+    if (!CONFIG_USE_SMM || SMMISADeviceBDF < 0)
+        return;
+
+    dprintf(3, "init smm\n");
+    u16 device = pci_config_readw(SMMISADeviceBDF, PCI_DEVICE_ID);
+    if (device == PCI_DEVICE_ID_INTEL_82371AB_3)
+        piix4_apmc_smm_setup(SMMISADeviceBDF, SMMPMDeviceBDF);
+    else
+        ich9_lpc_apmc_smm_setup(SMMISADeviceBDF, SMMPMDeviceBDF);
+}

package/bios/seabios/src/fw/smp.c

@@ -0,0 +1,194 @@
+// QEMU multi-CPU initialization code
+//
+// Copyright (C) 2008  Kevin O'Connor <kevin@koconnor.net>
+// Copyright (C) 2006 Fabrice Bellard
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#include "config.h" // CONFIG_*
+#include "hw/rtc.h" // CMOS_BIOS_SMP_COUNT
+#include "output.h" // dprintf
+#include "romfile.h" // romfile_loadint
+#include "stacks.h" // yield
+#include "util.h" // smp_setup, msr_feature_control_setup
+#include "x86.h" // wrmsr
+#include "paravirt.h" // qemu_*_present_cpus_count
+
+#define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300)
+#define APIC_SVR     ((u8*)BUILD_APIC_ADDR + 0x0F0)
+#define APIC_LINT0   ((u8*)BUILD_APIC_ADDR + 0x350)
+#define APIC_LINT1   ((u8*)BUILD_APIC_ADDR + 0x360)
+
+#define APIC_ENABLED 0x0100
+#define MSR_IA32_APIC_BASE 0x01B
+#define MSR_LOCAL_APIC_ID 0x802
+#define MSR_IA32_APICBASE_EXTD (1ULL << 10) /* Enable x2APIC mode */
+
+static struct { u32 index; u64 val; } smp_msr[32];
+static u32 smp_msr_count;
+
+void
+wrmsr_smp(u32 index, u64 val)
+{
+    wrmsr(index, val);
+    if (smp_msr_count >= ARRAY_SIZE(smp_msr)) {
+        warn_noalloc();
+        return;
+    }
+    smp_msr[smp_msr_count].index = index;
+    smp_msr[smp_msr_count].val = val;
+    smp_msr_count++;
+}
+
+static void
+smp_write_msrs(void)
+{
+    // MTRR and MSR_IA32_FEATURE_CONTROL setup
+    int i;
+    for (i=0; i<smp_msr_count; i++)
+        wrmsr(smp_msr[i].index, smp_msr[i].val);
+}
+
+u32 MaxCountCPUs;
+static u32 CountCPUs;
+// 256 bits for the found APIC IDs
+static u32 FoundAPICIDs[256/32];
+
+int apic_id_is_present(u8 apic_id)
+{
+    return !!(FoundAPICIDs[apic_id/32] & (1ul << (apic_id % 32)));
+}
+
+static int
+apic_id_init(void)
+{
+    u32 eax, ebx, ecx, cpuid_features;
+    cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
+    u32 apic_id = ebx>>24;
+    if (MaxCountCPUs < 256) { // xAPIC mode
+        // Track found apic id for use in legacy internal bios tables
+        FoundAPICIDs[apic_id/32] |= 1 << (apic_id % 32);
+    } else if (ecx & CPUID_X2APIC) {
+        // switch to x2APIC mode
+        u64 apic_base = rdmsr(MSR_IA32_APIC_BASE);
+        wrmsr(MSR_IA32_APIC_BASE, apic_base | MSR_IA32_APICBASE_EXTD);
+        apic_id = rdmsr(MSR_LOCAL_APIC_ID);
+    } else {
+        // x2APIC is masked by CPUID
+        apic_id = -1;
+    }
+    return apic_id;
+}
+
+void VISIBLE32FLAT
+handle_smp(void)
+{
+    if (!CONFIG_QEMU)
+        return;
+
+    // Track this CPU and detect the apic_id
+    int apic_id = apic_id_init();
+    dprintf(DEBUG_HDL_smp, "handle_smp: apic_id=0x%x\n", apic_id);
+
+    smp_write_msrs();
+
+    CountCPUs++;
+}
+
+// Atomic lock for shared stack across processors.
+u32 SMPLock __VISIBLE;
+u32 SMPStack __VISIBLE;
+
+// find and initialize the CPUs by launching a SIPI to them
+static void
+smp_scan(void)
+{
+    ASSERT32FLAT();
+    u32 eax, ebx, ecx, cpuid_features;
+    cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
+    if (eax < 1 || !(cpuid_features & CPUID_APIC)) {
+        // No apic - only the main cpu is present.
+        dprintf(1, "No apic - only the main cpu is present.\n");
+        CountCPUs= 1;
+        return;
+    }
+
+    // mark the BSP initial APIC ID as found, too:
+    CountCPUs = 1;
+
+    // Setup jump trampoline to counter code.
+    u64 old = *(u64*)BUILD_AP_BOOT_ADDR;
+    // ljmpw $SEG_BIOS, $(entry_smp - BUILD_BIOS_ADDR)
+    extern void entry_smp(void);
+    u64 new = (0xea | ((u64)SEG_BIOS<<24)
+               | (((u32)entry_smp - BUILD_BIOS_ADDR) << 8));
+    *(u64*)BUILD_AP_BOOT_ADDR = new;
+
+    // enable local APIC
+    u32 val = readl(APIC_SVR);
+    writel(APIC_SVR, val | APIC_ENABLED);
+
+    /* Set LINT0 as Ext_INT, level triggered */
+    writel(APIC_LINT0, 0x8700);
+
+    /* Set LINT1 as NMI, level triggered */
+    writel(APIC_LINT1, 0x8400);
+
+    // Init the lock.
+    writel(&SMPLock, 1);
+
+    // broadcast SIPI
+    barrier();
+    writel(APIC_ICR_LOW, 0x000C4500);
+    u32 sipi_vector = BUILD_AP_BOOT_ADDR >> 12;
+    writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
+
+    // switch to x2APIC mode after sending SIPI so that
+    // x2APIC and xAPIC mode could share AP wake up code
+    apic_id_init();
+
+    // Wait for other CPUs to process the SIPI.
+    u16 expected_cpus_count = qemu_get_present_cpus_count();
+    while (expected_cpus_count != CountCPUs)
+        asm volatile(
+            // Release lock and allow other processors to use the stack.
+            "  movl %%esp, %1\n"
+            "  movl $0, %0\n"
+            // Reacquire lock and take back ownership of stack.
+            "1:rep ; nop\n"
+            "  lock btsl $0, %0\n"
+            "  jc 1b\n"
+            : "+m" (SMPLock), "+m" (SMPStack)
+            : : "cc", "memory");
+    yield();
+
+    // Restore memory.
+    *(u64*)BUILD_AP_BOOT_ADDR = old;
+
+    dprintf(1, "Found %d cpu(s) max supported %d cpu(s)\n", CountCPUs,
+            MaxCountCPUs);
+}
+
+void
+smp_setup(void)
+{
+    if (!CONFIG_QEMU)
+        return;
+
+    MaxCountCPUs = romfile_loadint("etc/max-cpus", 0);
+    u16 smp_count = qemu_get_present_cpus_count();
+    if (MaxCountCPUs < smp_count)
+        MaxCountCPUs = smp_count;
+
+    smp_scan();
+}
+
+void
+smp_resume(void)
+{
+    if (!CONFIG_QEMU)
+        return;
+
+    smp_write_msrs();
+    smp_scan();
+}

package/bios/seabios/src/fw/ssdt-misc.dsl

@@ -0,0 +1,104 @@
+ACPI_EXTRACT_ALL_CODE ssdp_misc_aml
+
+DefinitionBlock ("ssdt-misc.aml", "SSDT", 0x01, "BXPC", "BXSSDTSU", 0x1)
+{
+
+/****************************************************************
+ * PCI memory ranges
+ ****************************************************************/
+
+    Scope(\) {
+       ACPI_EXTRACT_NAME_DWORD_CONST acpi_pci32_start
+       Name(P0S, 0x12345678)
+       ACPI_EXTRACT_NAME_DWORD_CONST acpi_pci32_end
+       Name(P0E, 0x12345678)
+       ACPI_EXTRACT_NAME_BYTE_CONST acpi_pci64_valid
+       Name(P1V, 0x12)
+       ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_start
+       Name(P1S, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
+       ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_end
+       Name(P1E, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
+       ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_length
+       Name(P1L, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
+    }
+
+
+/****************************************************************
+ * Suspend
+ ****************************************************************/
+
+    Scope(\) {
+    /*
+     * S3 (suspend-to-ram), S4 (suspend-to-disk) and S5 (power-off) type codes:
+     * must match piix4 emulation.
+     */
+
+        ACPI_EXTRACT_NAME_STRING acpi_s3_name
+        Name(_S3, Package(0x04) {
+            One,  /* PM1a_CNT.SLP_TYP */
+            One,  /* PM1b_CNT.SLP_TYP */
+            Zero,  /* reserved */
+            Zero   /* reserved */
+        })
+        ACPI_EXTRACT_NAME_STRING acpi_s4_name
+        ACPI_EXTRACT_PKG_START acpi_s4_pkg
+        Name(_S4, Package(0x04) {
+            0x2,  /* PM1a_CNT.SLP_TYP */
+            0x2,  /* PM1b_CNT.SLP_TYP */
+            Zero,  /* reserved */
+            Zero   /* reserved */
+        })
+        Name(_S5, Package(0x04) {
+            Zero,  /* PM1a_CNT.SLP_TYP */
+            Zero,  /* PM1b_CNT.SLP_TYP */
+            Zero,  /* reserved */
+            Zero   /* reserved */
+        })
+    }
+
+    External(\_SB.PCI0, DeviceObj)
+    External(\_SB.PCI0.ISA, DeviceObj)
+
+    Scope(\_SB.PCI0.ISA) {
+        Device(PEVT) {
+            Name(_HID, "QEMU0001")
+            /* PEST will be patched to be Zero if no such device */
+            ACPI_EXTRACT_NAME_WORD_CONST ssdt_isa_pest
+            Name(PEST, 0xFFFF)
+            OperationRegion(PEOR, SystemIO, PEST, 0x01)
+            Field(PEOR, ByteAcc, NoLock, Preserve) {
+                PEPT,   8,
+            }
+
+            Method(_STA, 0, NotSerialized) {
+                Store(PEST, Local0)
+                If (LEqual(Local0, Zero)) {
+                    Return (0x00)
+                } Else {
+                    Return (0x0F)
+                }
+            }
+
+            Method(RDPT, 0, NotSerialized) {
+                Store(PEPT, Local0)
+                Return (Local0)
+            }
+
+            Method(WRPT, 1, NotSerialized) {
+                Store(Arg0, PEPT)
+            }
+
+            Name(_CRS, ResourceTemplate() {
+                IO(Decode16, 0x00, 0x00, 0x01, 0x01, IO)
+            })
+
+            CreateWordField(_CRS, IO._MIN, IOMN)
+            CreateWordField(_CRS, IO._MAX, IOMX)
+
+            Method(_INI, 0, NotSerialized) {
+                Store(PEST, IOMN)
+                Store(PEST, IOMX)
+            }
+        }
+    }
+}

package/bios/seabios/src/fw/ssdt-misc.hex

@@ -0,0 +1,88 @@
+/* DO NOT EDIT!  This is an autogenerated file.  See scripts/acpi_extract.py. */
+static unsigned char acpi_pci64_length[] = {
+    0x6f
+};
+
+static unsigned char acpi_s4_pkg[] = {
+    0x8f
+};
+
+static unsigned char acpi_s3_name[] = {
+    0x7c
+};
+
+static unsigned char acpi_pci32_start[] = {
+    0x2f
+};
+
+static unsigned char acpi_pci64_valid[] = {
+    0x43
+};
+
+static unsigned char ssdp_misc_aml[] = {
+    0x53, 0x53, 0x44, 0x54, 0x62, 0x01, 0x00, 0x00,
+    0x01, 0x7f, 0x42, 0x58, 0x50, 0x43, 0x00, 0x00,
+    0x42, 0x58, 0x53, 0x53, 0x44, 0x54, 0x53, 0x55,
+    0x01, 0x00, 0x00, 0x00, 0x49, 0x4e, 0x54, 0x4c,
+    0x18, 0x08, 0x15, 0x20, 0x10, 0x42, 0x05, 0x5c,
+    0x00, 0x08, 0x50, 0x30, 0x53, 0x5f, 0x0c, 0x78,
+    0x56, 0x34, 0x12, 0x08, 0x50, 0x30, 0x45, 0x5f,
+    0x0c, 0x78, 0x56, 0x34, 0x12, 0x08, 0x50, 0x31,
+    0x56, 0x5f, 0x0a, 0x12, 0x08, 0x50, 0x31, 0x53,
+    0x5f, 0x11, 0x0b, 0x0a, 0x08, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x50, 0x31,
+    0x45, 0x5f, 0x11, 0x0b, 0x0a, 0x08, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x50,
+    0x31, 0x4c, 0x5f, 0x11, 0x0b, 0x0a, 0x08, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+    0x29, 0x5c, 0x00, 0x08, 0x5f, 0x53, 0x33, 0x5f,
+    0x12, 0x06, 0x04, 0x01, 0x01, 0x00, 0x00, 0x08,
+    0x5f, 0x53, 0x34, 0x5f, 0x12, 0x08, 0x04, 0x0a,
+    0x02, 0x0a, 0x02, 0x00, 0x00, 0x08, 0x5f, 0x53,
+    0x35, 0x5f, 0x12, 0x06, 0x04, 0x00, 0x00, 0x00,
+    0x00, 0x10, 0x40, 0x0c, 0x5c, 0x2f, 0x03, 0x5f,
+    0x53, 0x42, 0x5f, 0x50, 0x43, 0x49, 0x30, 0x49,
+    0x53, 0x41, 0x5f, 0x5b, 0x82, 0x4d, 0x0a, 0x50,
+    0x45, 0x56, 0x54, 0x08, 0x5f, 0x48, 0x49, 0x44,
+    0x0d, 0x51, 0x45, 0x4d, 0x55, 0x30, 0x30, 0x30,
+    0x31, 0x00, 0x08, 0x50, 0x45, 0x53, 0x54, 0x0b,
+    0xff, 0xff, 0x5b, 0x80, 0x50, 0x45, 0x4f, 0x52,
+    0x01, 0x50, 0x45, 0x53, 0x54, 0x01, 0x5b, 0x81,
+    0x0b, 0x50, 0x45, 0x4f, 0x52, 0x01, 0x50, 0x45,
+    0x50, 0x54, 0x08, 0x14, 0x18, 0x5f, 0x53, 0x54,
+    0x41, 0x00, 0x70, 0x50, 0x45, 0x53, 0x54, 0x60,
+    0xa0, 0x06, 0x93, 0x60, 0x00, 0xa4, 0x00, 0xa1,
+    0x04, 0xa4, 0x0a, 0x0f, 0x14, 0x0e, 0x52, 0x44,
+    0x50, 0x54, 0x00, 0x70, 0x50, 0x45, 0x50, 0x54,
+    0x60, 0xa4, 0x60, 0x14, 0x0c, 0x57, 0x52, 0x50,
+    0x54, 0x01, 0x70, 0x68, 0x50, 0x45, 0x50, 0x54,
+    0x08, 0x5f, 0x43, 0x52, 0x53, 0x11, 0x0d, 0x0a,
+    0x0a, 0x47, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
+    0x01, 0x79, 0x00, 0x8b, 0x5f, 0x43, 0x52, 0x53,
+    0x0a, 0x02, 0x49, 0x4f, 0x4d, 0x4e, 0x8b, 0x5f,
+    0x43, 0x52, 0x53, 0x0a, 0x04, 0x49, 0x4f, 0x4d,
+    0x58, 0x14, 0x18, 0x5f, 0x49, 0x4e, 0x49, 0x00,
+    0x70, 0x50, 0x45, 0x53, 0x54, 0x49, 0x4f, 0x4d,
+    0x4e, 0x70, 0x50, 0x45, 0x53, 0x54, 0x49, 0x4f,
+    0x4d, 0x58
+};
+
+static unsigned char ssdt_isa_pest[] = {
+    0xd0
+};
+
+static unsigned char acpi_s4_name[] = {
+    0x88
+};
+
+static unsigned char acpi_pci64_start[] = {
+    0x4d
+};
+
+static unsigned char acpi_pci64_end[] = {
+    0x5e
+};
+
+static unsigned char acpi_pci32_end[] = {
+    0x39
+};

package/bios/seabios/src/fw/ssdt-pcihp.dsl

@@ -0,0 +1,36 @@
+ACPI_EXTRACT_ALL_CODE ssdp_pcihp_aml
+
+DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPC", 0x1)
+{
+
+/****************************************************************
+ * PCI hotplug
+ ****************************************************************/
+
+    /* Objects supplied by DSDT */
+    External(\_SB.PCI0, DeviceObj)
+    External(\_SB.PCI0.PCEJ, MethodObj)
+
+    Scope(\_SB.PCI0) {
+
+        /* Bulk generated PCI hotplug devices */
+        ACPI_EXTRACT_DEVICE_START ssdt_pcihp_start
+        ACPI_EXTRACT_DEVICE_END ssdt_pcihp_end
+        ACPI_EXTRACT_DEVICE_STRING ssdt_pcihp_name
+
+        // Method _EJ0 can be patched by BIOS to EJ0_
+        // at runtime, if the slot is detected to not support hotplug.
+        // Extract the offset of the address dword and the
+        // _EJ0 name to allow this patching.
+        Device(SAA) {
+            ACPI_EXTRACT_NAME_BYTE_CONST ssdt_pcihp_id
+            Name(_SUN, 0xAA)
+            ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcihp_adr
+            Name(_ADR, 0xAA0000)
+            ACPI_EXTRACT_METHOD_STRING ssdt_pcihp_ej0
+            Method(_EJ0, 1) {
+                PCEJ(_SUN)
+            }
+        }
+    }
+}