@depz/sensor-sdk 0.2.1 → 0.3.0

package/dist/sensors/vl53lx/uld/bare/nvm.js

@@ -0,0 +1,148 @@
+/**
+ * uld/bare/nvm — the raw NVM, which the register blocks do not cover.
+ * Mirror of the Python `depz_sensor_sdk.vl53lx.uld.bare.nvm`.
+ *
+ * Part of the factory calibration never appears in the register map: the
+ * optical centre, the 5x5 peak-rate map, the mode-mitigation offset
+ * calibration and the FMT range results. To get at them the driver stops the
+ * firmware, powers the NVM array and clocks words out of it one at a time —
+ * four writes and a read per 32-bit word. That cost is why this reads regions,
+ * not the whole array.
+ *
+ * Every region is wrapped in its own enable/disable pair (as
+ * `VL53LX_read_nvm_raw_data()` does): the sensor must not be left with its
+ * firmware stopped by an exception in the middle of a multi-region read.
+ *
+ * Reference: vl53lx_nvm.c, vl53lx_nvm_map.h.
+ */
+// ── registers (vl53lx_register_map.h) ────────────────────────────────────────
+export const POWER_MANAGEMENT__GO1_POWER_FORCE = 0x0083;
+export const FIRMWARE__ENABLE = 0x0085;
+export const RANGING_CORE__CLK_CTRL1 = 0x0683;
+export const RANGING_CORE__NVM_CTRL__MODE = 0x0780;
+export const RANGING_CORE__NVM_CTRL__PDN = 0x0781;
+export const RANGING_CORE__NVM_CTRL__READN = 0x0783;
+export const RANGING_CORE__NVM_CTRL__PULSE_WIDTH_MSB = 0x0784;
+export const RANGING_CORE__NVM_CTRL__DATAOUT_MMM = 0x0790;
+export const RANGING_CORE__NVM_CTRL__ADDR = 0x0794;
+// ── timings (vl53lx_nvm.h, vl53lx_ll_device.h) ───────────────────────────────
+export const NVM_POWER_UP_DELAY_US = 50;
+export const NVM_READ_TRIGGER_DELAY_US = 5;
+export const ENABLE_POWERFORCE_SETTLING_TIME_US = 250;
+export const NVM_CTRL_PULSE_WIDTH = 0x0004;
+export const FMT_OPTICAL_CENTRE = [0x00b8, 4];
+export const FMT_CAL_PEAK_RATE_MAP = [0x015c, 56];
+export const FMT_ADDITIONAL_OFFSET_CAL = [0x0194, 8];
+export const FMT_RANGE_RESULTS__140MM_DARK = [0x01ac, 16];
+export const PEAK_RATE_MAP_WIDTH = 5;
+export const PEAK_RATE_MAP_HEIGHT = 5;
+export const PEAK_RATE_MAP_SAMPLES = PEAK_RATE_MAP_WIDTH * PEAK_RATE_MAP_HEIGHT;
+function u16(buf, off) {
+    return (buf[off] << 8) | buf[off + 1];
+}
+/** Raw NVM access. Holds no state between reads — the sensor does. */
+export class NvmReader {
+    p;
+    img;
+    constructor(p, img) {
+        this.p = p;
+        this.img = img;
+    }
+    // ── VL53LX_nvm_enable / _disable ──
+    async enable() {
+        // disable_firmware / enable_powerforce, both through system_control so
+        // the image stays truthful about what the device was told.
+        this.img.system_control.v.firmware__enable = 0;
+        await this.p.wrByte(FIRMWARE__ENABLE, 0);
+        this.img.system_control.v.power_management__go1_power_force = 1;
+        await this.p.wrByte(POWER_MANAGEMENT__GO1_POWER_FORCE, 1);
+        await this.p.sleepMs(1); // 250 us settling, rounded up
+        await this.p.wrByte(RANGING_CORE__NVM_CTRL__PDN, 0x01);
+        await this.p.wrByte(RANGING_CORE__CLK_CTRL1, 0x05);
+        await this.p.sleepMs(1); // 50 us power-up, rounded up
+        await this.p.wrByte(RANGING_CORE__NVM_CTRL__MODE, 0x01);
+        await this.p.wrWord(RANGING_CORE__NVM_CTRL__PULSE_WIDTH_MSB, NVM_CTRL_PULSE_WIDTH);
+    }
+    async disable() {
+        await this.p.wrByte(RANGING_CORE__NVM_CTRL__READN, 0x01);
+        await this.p.wrByte(RANGING_CORE__NVM_CTRL__PDN, 0x00);
+        this.img.system_control.v.power_management__go1_power_force = 0;
+        await this.p.wrByte(POWER_MANAGEMENT__GO1_POWER_FORCE, 0);
+        this.img.system_control.v.firmware__enable = 1;
+        await this.p.wrByte(FIRMWARE__ENABLE, 1);
+    }
+    // ── VL53LX_nvm_read ──
+    async readWords(startWord, count) {
+        const out = new Uint8Array(count * 4);
+        for (let i = 0; i < count; i++) {
+            await this.p.wrByte(RANGING_CORE__NVM_CTRL__ADDR, startWord + i);
+            await this.p.wrByte(RANGING_CORE__NVM_CTRL__READN, 0x00);
+            // 5 us trigger delay: a USB round trip is three orders of magnitude
+            // longer, so the next transfer is the wait.
+            await this.p.wrByte(RANGING_CORE__NVM_CTRL__READN, 0x01);
+            out.set(await this.p.rdMulti(RANGING_CORE__NVM_CTRL__DATAOUT_MMM, 4), i * 4);
+        }
+        return out;
+    }
+    // ── VL53LX_read_nvm_raw_data ──
+    /** [byte index, byte size] → the bytes. Both must be word-aligned. */
+    async readRegion(region) {
+        const [index, size] = region;
+        if (index & 3 || size & 3) {
+            throw new RangeError(`NVM region 0x${index.toString(16).toUpperCase().padStart(4, "0")}+${size} is not word-aligned`);
+        }
+        await this.enable();
+        try {
+            return await this.readWords(index >> 2, size >> 2);
+        }
+        finally {
+            await this.disable();
+        }
+    }
+    // ── the four decoders the driver needs ──
+    async opticalCentre() {
+        const buf = await this.readRegion(FMT_OPTICAL_CENTRE);
+        // Stored as a distance down from 0x0100; on a never-programmed part the
+        // subtraction overflows and the driver zeroes it.
+        const x = 0x0100 - buf[2];
+        return { x_centre: x <= 0xff ? x : 0, y_centre: buf[3] };
+    }
+    async calPeakRateMap() {
+        const buf = await this.readRegion(FMT_CAL_PEAK_RATE_MAP);
+        const peak = [];
+        for (let i = 0; i < PEAK_RATE_MAP_SAMPLES; i++)
+            peak.push(u16(buf, 4 + 2 * i));
+        return {
+            cal_distance_mm: u16(buf, 0),
+            cal_reflectance_pc: u16(buf, 2) >> 6,
+            max_samples: PEAK_RATE_MAP_SAMPLES,
+            width: PEAK_RATE_MAP_WIDTH,
+            height: PEAK_RATE_MAP_HEIGHT,
+            peak_rate_mcps: peak,
+        };
+    }
+    async additionalOffsetCalData() {
+        const buf = await this.readRegion(FMT_ADDITIONAL_OFFSET_CAL);
+        return {
+            result__mm_inner_actual_effective_spads: u16(buf, 0),
+            result__mm_outer_actual_effective_spads: u16(buf, 2),
+            result__mm_inner_peak_signal_count_rtn_mcps: u16(buf, 4),
+            result__mm_outer_peak_signal_count_rtn_mcps: u16(buf, 6),
+        };
+    }
+    async fmtRangeResults(region = FMT_RANGE_RESULTS__140MM_DARK) {
+        const buf = await this.readRegion(region);
+        return {
+            result__actual_effective_rtn_spads: u16(buf, 0),
+            ref_spad_array__num_requested_ref_spads: buf[2],
+            ref_spad_array__ref_location: buf[3],
+            result__peak_signal_count_rate_rtn_mcps: u16(buf, 4),
+            result__ambient_count_rate_rtn_mcps: u16(buf, 6),
+            result__peak_signal_count_rate_ref_mcps: u16(buf, 8),
+            result__ambient_count_rate_ref_mcps: u16(buf, 10),
+            measured_distance_mm: u16(buf, 12),
+            measured_distance_stdev_mm: u16(buf, 14),
+        };
+    }
+}
+//# sourceMappingURL=nvm.js.map

package/dist/sensors/vl53lx/uld/bare/nvm.js.map

@@ -0,0 +1 @@
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package/dist/sensors/vl53lx/uld/bare/regs.d.ts

@@ -0,0 +1,54 @@
+/**
+ * uld/bare/regs — the VL53LX register blocks, as ST's BareDriver sees them.
+ * Mirror of the Python `depz_sensor_sdk.vl53lx.uld.bare.regs`.
+ *
+ * The BareDriver does not touch registers one at a time. It keeps the device
+ * image in a handful of C structs (`VL53LX_static_config_t`, ...), each mapping
+ * onto one contiguous I2C block, and moves a whole block at a time. `BLOCKS`
+ * is that mapping: base address, byte length, whether the block is writable,
+ * and the field list with offset, width, signedness and the bit mask the C
+ * codec applies. Generated from the Python table (itself generated from
+ * `vl53lx_register_funcs.c`) — data, not hand-written: the masks and the
+ * reserved holes (general_config has one at offset 10) match the C driver.
+ */
+/** One register field: name, byte offset, byte width, signed, C codec mask. */
+export interface RegField {
+    readonly name: string;
+    readonly off: number;
+    readonly width: number;
+    readonly signed: boolean;
+    readonly mask: number | null;
+}
+export interface Block {
+    readonly base: number;
+    readonly size: number;
+    readonly writable: boolean;
+    readonly fields: readonly RegField[];
+}
+export type BlockName = "static_nvm_managed" | "customer_nvm_managed" | "static_config" | "general_config" | "timing_config" | "dynamic_config" | "system_control" | "system_results" | "core_results" | "debug_results" | "nvm_copy_data" | "patch_debug" | "gph_general_config" | "gph_static_config" | "gph_timing_config" | "fw_internal";
+export declare const BLOCK_NAMES: readonly BlockName[];
+export declare const BLOCKS: Readonly<Record<BlockName, Block>>;
+/**
+ * One register block's worth of device image, addressed by field name.
+ *
+ * `v` holds the field values exactly as the Python `RegBlock` does: a write
+ * stores the value as given (unclipped — Python keeps `int(value)`), a decode
+ * stores it masked and sign-extended; the mask/width are applied only on
+ * `encode()`. `v` is sealed, so writing a field the block does not have
+ * throws (ES modules are strict mode), as Python's `AttributeError` does.
+ * Fields not named in the block (the reserved holes) keep whatever bytes were
+ * read, so a read-modify-write round trip is byte-exact.
+ */
+export declare class RegBlock {
+    readonly name: BlockName;
+    readonly block: Block;
+    readonly v: Record<string, number>;
+    private raw;
+    constructor(name: BlockName);
+    decode(raw: Uint8Array): this;
+    encode(): Uint8Array;
+    get base(): number;
+    get size(): number;
+    items(): Array<[string, number]>;
+}
+//# sourceMappingURL=regs.d.ts.map

package/dist/sensors/vl53lx/uld/bare/regs.d.ts.map

@@ -0,0 +1 @@
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