wasmtime 21.0.1 → 23.0.2
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- checksums.yaml +4 -4
- data/Cargo.lock +129 -99
- data/ext/Cargo.toml +5 -5
- data/ext/cargo-vendor/cranelift-bforest-0.110.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.110.2/Cargo.toml +50 -0
- data/ext/cargo-vendor/cranelift-bitset-0.110.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bitset-0.110.2/Cargo.toml +60 -0
- data/ext/cargo-vendor/cranelift-bitset-0.110.2/src/compound.rs +508 -0
- data/ext/cargo-vendor/cranelift-bitset-0.110.2/src/lib.rs +19 -0
- data/ext/cargo-vendor/cranelift-bitset-0.110.2/src/scalar.rs +575 -0
- data/ext/cargo-vendor/cranelift-bitset-0.110.2/tests/bitset.rs +78 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/Cargo.toml +206 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/binemit/stack_map.rs +141 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/context.rs +390 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/data_value.rs +410 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/dominator_tree.rs +727 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/egraph.rs +835 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/inst_predicates.rs +230 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/dfg.rs +1806 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/extfunc.rs +402 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/globalvalue.rs +147 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/immediates.rs +2109 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/instructions.rs +1015 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/jumptable.rs +168 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/mod.rs +110 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/stackslot.rs +208 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/trapcode.rs +148 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/types.rs +643 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/ir/user_stack_maps.rs +101 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/abi.rs +1556 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/args.rs +711 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/emit.rs +3605 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/emit_tests.rs +7927 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/imms.rs +1213 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/mod.rs +3058 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/regs.rs +269 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst/unwind/systemv.rs +174 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/inst.isle +4221 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/lower.isle +2969 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/mod.rs +259 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/aarch64/pcc.rs +568 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/mod.rs +462 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/abi.rs +1029 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/args.rs +2054 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/emit.rs +2741 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/emit_tests.rs +2219 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/encode.rs +675 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/imms.rs +374 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/mod.rs +1935 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/unwind/systemv.rs +170 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst/vector.rs +1150 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst.isle +3153 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/inst_vector.isle +1907 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/lower/isle.rs +654 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/lower.isle +2953 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/riscv64/mod.rs +265 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/abi.rs +1016 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/inst/args.rs +298 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/inst/emit.rs +3421 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/inst/emit_tests.rs +13388 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/inst/imms.rs +202 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/inst/mod.rs +3395 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/inst/regs.rs +169 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/inst/unwind/systemv.rs +212 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/inst.isle +5028 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/lower.isle +3983 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/s390x/mod.rs +220 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/abi.rs +1390 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/args.rs +2240 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/emit.rs +4297 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/emit_state.rs +65 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/emit_tests.rs +5171 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/mod.rs +2818 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/regs.rs +275 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst/unwind/systemv.rs +198 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/inst.isle +5299 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/lower.isle +4819 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/mod.rs +239 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isa/x64/pcc.rs +1014 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/isle_prelude.rs +965 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/legalizer/mod.rs +343 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/lib.rs +106 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/abi.rs +2427 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/blockorder.rs +465 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/buffer.rs +2544 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/helpers.rs +23 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/isle.rs +908 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/lower.rs +1462 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/mod.rs +564 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/reg.rs +479 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/valueregs.rs +138 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/machinst/vcode.rs +1840 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/opts/cprop.isle +297 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/opts/shifts.isle +307 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/prelude.isle +654 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/prelude_lower.isle +1070 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/timing.rs +296 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/traversals.rs +216 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/verifier/mod.rs +1957 -0
- data/ext/cargo-vendor/cranelift-codegen-0.110.2/src/write.rs +660 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/Cargo.toml +45 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/cdsl/types.rs +512 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/cdsl/typevar.rs +980 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/gen_inst.rs +1278 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/isa/riscv64.rs +174 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/shared/instructions.rs +3760 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.110.2/src/shared/types.rs +143 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.110.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.110.2/Cargo.toml +31 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.110.2/src/constants.rs +28 -0
- data/ext/cargo-vendor/cranelift-control-0.110.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.110.2/Cargo.toml +39 -0
- data/ext/cargo-vendor/cranelift-entity-0.110.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.110.2/Cargo.toml +66 -0
- data/ext/cargo-vendor/cranelift-entity-0.110.2/src/set.rs +193 -0
- data/ext/cargo-vendor/cranelift-frontend-0.110.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.110.2/Cargo.toml +87 -0
- data/ext/cargo-vendor/cranelift-frontend-0.110.2/src/frontend.rs +2867 -0
- data/ext/cargo-vendor/cranelift-frontend-0.110.2/src/lib.rs +187 -0
- data/ext/cargo-vendor/cranelift-frontend-0.110.2/src/ssa.rs +1328 -0
- data/ext/cargo-vendor/cranelift-isle-0.110.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.110.2/Cargo.toml +60 -0
- data/ext/cargo-vendor/cranelift-isle-0.110.2/src/codegen.rs +920 -0
- data/ext/cargo-vendor/cranelift-isle-0.110.2/src/parser.rs +562 -0
- data/ext/cargo-vendor/cranelift-isle-0.110.2/src/sema.rs +2503 -0
- data/ext/cargo-vendor/cranelift-isle-0.110.2/src/trie_again.rs +695 -0
- data/ext/cargo-vendor/cranelift-native-0.110.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-native-0.110.2/Cargo.toml +52 -0
- data/ext/cargo-vendor/cranelift-native-0.110.2/src/lib.rs +188 -0
- data/ext/cargo-vendor/cranelift-native-0.110.2/src/riscv.rs +128 -0
- data/ext/cargo-vendor/cranelift-wasm-0.110.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-wasm-0.110.2/Cargo.toml +119 -0
- data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/code_translator/bounds_checks.rs +731 -0
- data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/code_translator.rs +3694 -0
- data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/func_translator.rs +296 -0
- data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/heap.rs +119 -0
- data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/module_translator.rs +120 -0
- data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/sections_translator.rs +333 -0
- data/ext/cargo-vendor/cranelift-wasm-0.110.2/src/state.rs +522 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.23/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.23/Cargo.toml +69 -0
- data/ext/cargo-vendor/object-0.36.3/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/object-0.36.3/CHANGELOG.md +1028 -0
- data/ext/cargo-vendor/object-0.36.3/Cargo.toml +180 -0
- data/ext/cargo-vendor/object-0.36.3/README.md +60 -0
- data/ext/cargo-vendor/object-0.36.3/src/build/bytes.rs +146 -0
- data/ext/cargo-vendor/object-0.36.3/src/build/elf.rs +3113 -0
- data/ext/cargo-vendor/object-0.36.3/src/common.rs +590 -0
- data/ext/cargo-vendor/object-0.36.3/src/elf.rs +6303 -0
- data/ext/cargo-vendor/object-0.36.3/src/endian.rs +831 -0
- data/ext/cargo-vendor/object-0.36.3/src/macho.rs +3303 -0
- data/ext/cargo-vendor/object-0.36.3/src/pod.rs +281 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/any.rs +1334 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/archive.rs +1133 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/comdat.rs +220 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/file.rs +381 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/relocation.rs +113 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/section.rs +619 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/coff/symbol.rs +669 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/attributes.rs +340 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/comdat.rs +186 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/file.rs +959 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/hash.rs +236 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/note.rs +302 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/relocation.rs +661 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/section.rs +1241 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/segment.rs +365 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/symbol.rs +654 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/elf/version.rs +513 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/gnu_compression.rs +36 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/dyld_cache.rs +384 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/file.rs +779 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/load_command.rs +404 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/section.rs +420 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/segment.rs +317 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/macho/symbol.rs +532 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/mod.rs +1018 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/pe/file.rs +1033 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/pe/import.rs +381 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/pe/relocation.rs +109 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/pe/section.rs +476 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/read_cache.rs +261 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/traits.rs +589 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/wasm.rs +983 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/xcoff/file.rs +716 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/xcoff/relocation.rs +138 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/xcoff/section.rs +452 -0
- data/ext/cargo-vendor/object-0.36.3/src/read/xcoff/symbol.rs +836 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/coff/object.rs +681 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/coff/writer.rs +520 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/elf/object.rs +897 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/elf/writer.rs +2361 -0
- data/ext/cargo-vendor/object-0.36.3/src/write/macho.rs +1124 -0
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- data/ext/cargo-vendor/object-0.36.3/src/write/pe.rs +849 -0
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- data/ext/cargo-vendor/object-0.36.3/tests/build/elf.rs +254 -0
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- data/ext/cargo-vendor/object-0.36.3/tests/read/mod.rs +5 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/bss.rs +244 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/comdat.rs +217 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/common.rs +241 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/elf.rs +302 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/mod.rs +682 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/section_flags.rs +89 -0
- data/ext/cargo-vendor/object-0.36.3/tests/round_trip/tls.rs +308 -0
- data/ext/cargo-vendor/termcolor-1.4.1/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/termcolor-1.4.1/rustfmt.toml +2 -0
- data/ext/cargo-vendor/termcolor-1.4.1/src/lib.rs +2572 -0
- data/ext/cargo-vendor/wasi-common-23.0.2/.cargo-checksum.json +1 -0
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- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/use-chain.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/use-chain.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/use.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/use.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/versions/deps/a1/foo.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/versions/deps/a2/foo.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/versions/foo.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/versions.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/wasi.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/wasi.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/world-diamond.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/world-iface-no-collide.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/world-implicit-import1.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/world-implicit-import2.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/world-implicit-import3.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/world-same-fields4.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/world-top-level-funcs.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/world-top-level-funcs.wit.json +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/world-top-level-resources.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/worlds-union-dedup.wit +0 -0
- /data/ext/cargo-vendor/{wit-parser-0.207.0 → wit-parser-0.212.0}/tests/ui/worlds-with-types.wit +0 -0
@@ -1,1037 +0,0 @@
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//! Implementation of a standard S390x ABI.
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//!
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//! This machine uses the "vanilla" ABI implementation from abi.rs,
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//! however a few details are different from the description there:
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//!
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//! - On s390x, the caller must provide a "register save area" of 160
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//! bytes to any function it calls. The called function is free to use
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//! this space for any purpose; usually to save callee-saved GPRs.
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//! (Note that while this area is allocated by the caller, it is counted
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//! as part of the callee's stack frame; in particular, the callee's CFA
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//! is the top of the register save area, not the incoming SP value.)
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//!
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//! - Overflow arguments are passed on the stack starting immediately
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//! above the register save area. On s390x, this space is allocated
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//! only once directly in the prologue, using a size large enough to
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//! hold overflow arguments for every call in the function.
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//!
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//! - On s390x we do not use a frame pointer register; instead, every
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//! element of the stack frame is addressed via (constant) offsets
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//! from the stack pointer. Note that due to the above (and because
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//! there are no variable-sized stack allocations in cranelift), the
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//! value of the stack pointer register never changes after the
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//! initial allocation in the function prologue.
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//!
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//! - If we are asked to "preserve frame pointers" to enable stack
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//! unwinding, we use the stack backchain feature instead, which
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//! is documented by the s390x ELF ABI, but marked as optional.
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//! This ensures that at all times during execution of a function,
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//! the lowest word on the stack (part of the register save area)
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//! holds a copy of the stack pointer at function entry.
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//!
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//! Overall, the stack frame layout on s390x is as follows:
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//!
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//! ```plain
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//! (high address)
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//!
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//! +---------------------------+
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//! | ... |
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//! CFA -----> | stack args |
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//! +---------------------------+
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//! | ... |
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//! | 160 bytes reg save area |
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//! | (used to save GPRs) |
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//! SP at function entry -----> | (incl. caller's backchain)|
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//! +---------------------------+
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//! | ... |
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//! | clobbered callee-saves |
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//! | (used to save FPRs) |
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//! unwind-frame base ----> | (alloc'd by prologue) |
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//! +---------------------------+
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//! | ... |
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//! | spill slots |
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//! | (accessed via nominal SP) |
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//! | ... |
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//! | stack slots |
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//! | (accessed via nominal SP) |
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//! nominal SP ---------------> | (alloc'd by prologue) |
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//! +---------------------------+
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//! | ... |
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//! | args for call |
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//! | outgoing reg save area |
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//! | (alloc'd by prologue) |
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//! SP during function ------> | (incl. callee's backchain)|
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//! +---------------------------+
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//!
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//! (low address)
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//! ```
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use crate::ir;
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use crate::ir::condcodes::IntCC;
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use crate::ir::types;
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use crate::ir::MemFlags;
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use crate::ir::Signature;
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use crate::ir::Type;
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use crate::isa;
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use crate::isa::s390x::{inst::*, settings as s390x_settings};
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use crate::isa::unwind::UnwindInst;
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use crate::machinst::*;
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use crate::settings;
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use crate::{CodegenError, CodegenResult};
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use alloc::vec::Vec;
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use regalloc2::{MachineEnv, PRegSet};
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use smallvec::{smallvec, SmallVec};
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use std::sync::OnceLock;
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// We use a generic implementation that factors out ABI commonalities.
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/// Support for the S390x ABI from the callee side (within a function body).
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pub type S390xCallee = Callee<S390xMachineDeps>;
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/// ABI Register usage
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fn in_int_reg(ty: Type) -> bool {
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match ty {
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types::I8 | types::I16 | types::I32 | types::I64 | types::R64 => true,
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_ => false,
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}
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}
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fn in_flt_reg(ty: Type) -> bool {
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match ty {
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types::F32 | types::F64 => true,
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_ => false,
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}
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}
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fn in_vec_reg(ty: Type) -> bool {
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ty.is_vector() && ty.bits() == 128
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}
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fn get_intreg_for_arg(idx: usize) -> Option<Reg> {
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match idx {
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0 => Some(regs::gpr(2)),
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1 => Some(regs::gpr(3)),
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2 => Some(regs::gpr(4)),
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3 => Some(regs::gpr(5)),
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4 => Some(regs::gpr(6)),
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_ => None,
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}
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}
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fn get_fltreg_for_arg(idx: usize) -> Option<Reg> {
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match idx {
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0 => Some(regs::vr(0)),
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1 => Some(regs::vr(2)),
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2 => Some(regs::vr(4)),
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3 => Some(regs::vr(6)),
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_ => None,
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}
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}
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fn get_vecreg_for_arg(idx: usize) -> Option<Reg> {
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match idx {
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0 => Some(regs::vr(24)),
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1 => Some(regs::vr(25)),
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2 => Some(regs::vr(26)),
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3 => Some(regs::vr(27)),
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4 => Some(regs::vr(28)),
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5 => Some(regs::vr(29)),
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6 => Some(regs::vr(30)),
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7 => Some(regs::vr(31)),
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_ => None,
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}
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}
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fn get_intreg_for_ret(idx: usize) -> Option<Reg> {
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match idx {
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0 => Some(regs::gpr(2)),
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// ABI extension to support multi-value returns:
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1 => Some(regs::gpr(3)),
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2 => Some(regs::gpr(4)),
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3 => Some(regs::gpr(5)),
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_ => None,
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}
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}
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fn get_fltreg_for_ret(idx: usize) -> Option<Reg> {
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match idx {
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0 => Some(regs::vr(0)),
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// ABI extension to support multi-value returns:
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1 => Some(regs::vr(2)),
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2 => Some(regs::vr(4)),
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3 => Some(regs::vr(6)),
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_ => None,
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}
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}
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fn get_vecreg_for_ret(idx: usize) -> Option<Reg> {
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match idx {
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0 => Some(regs::vr(24)),
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// ABI extension to support multi-value returns:
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1 => Some(regs::vr(25)),
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2 => Some(regs::vr(26)),
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3 => Some(regs::vr(27)),
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4 => Some(regs::vr(28)),
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5 => Some(regs::vr(29)),
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6 => Some(regs::vr(30)),
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7 => Some(regs::vr(31)),
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_ => None,
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}
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}
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/// This is the limit for the size of argument and return-value areas on the
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/// stack. We place a reasonable limit here to avoid integer overflow issues
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/// with 32-bit arithmetic: for now, 128 MB.
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static STACK_ARG_RET_SIZE_LIMIT: u32 = 128 * 1024 * 1024;
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/// The size of the register save area
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pub static REG_SAVE_AREA_SIZE: u32 = 160;
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impl Into<MemArg> for StackAMode {
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fn into(self) -> MemArg {
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match self {
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// Argument area always begins at the initial SP.
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StackAMode::IncomingArg(off, _) => MemArg::InitialSPOffset { off },
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StackAMode::Slot(off) => MemArg::NominalSPOffset { off },
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StackAMode::OutgoingArg(off) => {
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MemArg::reg_plus_off(stack_reg(), off, MemFlags::trusted())
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}
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}
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}
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}
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/// S390x-specific ABI behavior. This struct just serves as an implementation
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/// point for the trait; it is never actually instantiated.
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pub struct S390xMachineDeps;
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impl IsaFlags for s390x_settings::Flags {}
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impl ABIMachineSpec for S390xMachineDeps {
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type I = Inst;
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type F = s390x_settings::Flags;
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fn word_bits() -> u32 {
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64
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}
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/// Return required stack alignment in bytes.
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fn stack_align(_call_conv: isa::CallConv) -> u32 {
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8
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}
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fn compute_arg_locs(
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call_conv: isa::CallConv,
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_flags: &settings::Flags,
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params: &[ir::AbiParam],
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args_or_rets: ArgsOrRets,
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add_ret_area_ptr: bool,
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mut args: ArgsAccumulator,
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) -> CodegenResult<(u32, Option<usize>)> {
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assert_ne!(
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call_conv,
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isa::CallConv::Tail,
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"s390x does not support the 'tail' calling convention yet"
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);
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assert_ne!(
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call_conv,
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isa::CallConv::Winch,
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"s390x does not support the 'winch' calling convention yet"
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);
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let mut next_gpr = 0;
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let mut next_fpr = 0;
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let mut next_vr = 0;
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let mut next_stack: u32 = 0;
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if args_or_rets == ArgsOrRets::Args {
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next_stack = REG_SAVE_AREA_SIZE;
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}
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// In the SystemV ABI, the return area pointer is the first argument,
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// so we need to leave room for it if required.
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if add_ret_area_ptr {
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next_gpr += 1;
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}
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for mut param in params.into_iter().copied() {
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let intreg = in_int_reg(param.value_type);
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let fltreg = in_flt_reg(param.value_type);
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let vecreg = in_vec_reg(param.value_type);
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debug_assert!(intreg as i32 + fltreg as i32 + vecreg as i32 <= 1);
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263
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let (next_reg, candidate, implicit_ref) = if intreg {
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265
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let candidate = match args_or_rets {
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ArgsOrRets::Args => get_intreg_for_arg(next_gpr),
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ArgsOrRets::Rets => get_intreg_for_ret(next_gpr),
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};
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(&mut next_gpr, candidate, None)
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} else if fltreg {
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let candidate = match args_or_rets {
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ArgsOrRets::Args => get_fltreg_for_arg(next_fpr),
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ArgsOrRets::Rets => get_fltreg_for_ret(next_fpr),
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};
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(&mut next_fpr, candidate, None)
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} else if vecreg {
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277
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let candidate = match args_or_rets {
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ArgsOrRets::Args => get_vecreg_for_arg(next_vr),
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ArgsOrRets::Rets => get_vecreg_for_ret(next_vr),
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};
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(&mut next_vr, candidate, None)
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} else {
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// We must pass this by implicit reference.
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if args_or_rets == ArgsOrRets::Rets {
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// For return values, just force them to memory.
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(&mut next_gpr, None, None)
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287
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} else {
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// For arguments, implicitly convert to pointer type.
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289
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let implicit_ref = Some(param.value_type);
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290
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param = ir::AbiParam::new(types::I64);
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291
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let candidate = get_intreg_for_arg(next_gpr);
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(&mut next_gpr, candidate, implicit_ref)
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293
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}
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};
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296
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let slot = if let Some(reg) = candidate {
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297
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*next_reg += 1;
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298
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ABIArgSlot::Reg {
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299
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reg: reg.to_real_reg().unwrap(),
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ty: param.value_type,
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extension: param.extension,
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}
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303
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} else {
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304
|
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// Compute size. Every argument or return value takes a slot of
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305
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// at least 8 bytes.
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306
|
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let size = (ty_bits(param.value_type) / 8) as u32;
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307
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let slot_size = std::cmp::max(size, 8);
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308
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309
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// Align the stack slot.
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310
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debug_assert!(slot_size.is_power_of_two());
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311
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let slot_align = std::cmp::min(slot_size, 8);
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312
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next_stack = align_to(next_stack, slot_align);
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313
|
-
|
314
|
-
// If the type is actually of smaller size (and the argument
|
315
|
-
// was not extended), it is passed right-aligned.
|
316
|
-
let offset = if size < slot_size && param.extension == ir::ArgumentExtension::None {
|
317
|
-
slot_size - size
|
318
|
-
} else {
|
319
|
-
0
|
320
|
-
};
|
321
|
-
let offset = (next_stack + offset) as i64;
|
322
|
-
next_stack += slot_size;
|
323
|
-
ABIArgSlot::Stack {
|
324
|
-
offset,
|
325
|
-
ty: param.value_type,
|
326
|
-
extension: param.extension,
|
327
|
-
}
|
328
|
-
};
|
329
|
-
|
330
|
-
if let ir::ArgumentPurpose::StructArgument(size) = param.purpose {
|
331
|
-
assert!(size % 8 == 0, "StructArgument size is not properly aligned");
|
332
|
-
args.push(ABIArg::StructArg {
|
333
|
-
pointer: Some(slot),
|
334
|
-
offset: 0,
|
335
|
-
size: size as u64,
|
336
|
-
purpose: param.purpose,
|
337
|
-
});
|
338
|
-
} else if let Some(ty) = implicit_ref {
|
339
|
-
assert!(
|
340
|
-
(ty_bits(ty) / 8) % 8 == 0,
|
341
|
-
"implicit argument size is not properly aligned"
|
342
|
-
);
|
343
|
-
args.push(ABIArg::ImplicitPtrArg {
|
344
|
-
pointer: slot,
|
345
|
-
offset: 0,
|
346
|
-
ty,
|
347
|
-
purpose: param.purpose,
|
348
|
-
});
|
349
|
-
} else {
|
350
|
-
args.push(ABIArg::Slots {
|
351
|
-
slots: smallvec![slot],
|
352
|
-
purpose: param.purpose,
|
353
|
-
});
|
354
|
-
}
|
355
|
-
}
|
356
|
-
|
357
|
-
next_stack = align_to(next_stack, 8);
|
358
|
-
|
359
|
-
let extra_arg = if add_ret_area_ptr {
|
360
|
-
debug_assert!(args_or_rets == ArgsOrRets::Args);
|
361
|
-
// The return pointer is passed as first argument.
|
362
|
-
if let Some(reg) = get_intreg_for_arg(0) {
|
363
|
-
args.push(ABIArg::reg(
|
364
|
-
reg.to_real_reg().unwrap(),
|
365
|
-
types::I64,
|
366
|
-
ir::ArgumentExtension::None,
|
367
|
-
ir::ArgumentPurpose::Normal,
|
368
|
-
));
|
369
|
-
} else {
|
370
|
-
args.push(ABIArg::stack(
|
371
|
-
next_stack as i64,
|
372
|
-
types::I64,
|
373
|
-
ir::ArgumentExtension::None,
|
374
|
-
ir::ArgumentPurpose::Normal,
|
375
|
-
));
|
376
|
-
next_stack += 8;
|
377
|
-
}
|
378
|
-
Some(args.args().len() - 1)
|
379
|
-
} else {
|
380
|
-
None
|
381
|
-
};
|
382
|
-
|
383
|
-
// After all arguments are in their well-defined location,
|
384
|
-
// allocate buffers for all StructArg or ImplicitPtrArg arguments.
|
385
|
-
for arg in args.args_mut() {
|
386
|
-
match arg {
|
387
|
-
ABIArg::StructArg { offset, size, .. } => {
|
388
|
-
*offset = next_stack as i64;
|
389
|
-
next_stack += *size as u32;
|
390
|
-
}
|
391
|
-
ABIArg::ImplicitPtrArg { offset, ty, .. } => {
|
392
|
-
*offset = next_stack as i64;
|
393
|
-
next_stack += (ty_bits(*ty) / 8) as u32;
|
394
|
-
}
|
395
|
-
_ => {}
|
396
|
-
}
|
397
|
-
}
|
398
|
-
|
399
|
-
// To avoid overflow issues, limit the arg/return size to something
|
400
|
-
// reasonable -- here, 128 MB.
|
401
|
-
if next_stack > STACK_ARG_RET_SIZE_LIMIT {
|
402
|
-
return Err(CodegenError::ImplLimitExceeded);
|
403
|
-
}
|
404
|
-
|
405
|
-
Ok((next_stack, extra_arg))
|
406
|
-
}
|
407
|
-
|
408
|
-
fn gen_load_stack(mem: StackAMode, into_reg: Writable<Reg>, ty: Type) -> Inst {
|
409
|
-
Inst::gen_load(into_reg, mem.into(), ty)
|
410
|
-
}
|
411
|
-
|
412
|
-
fn gen_store_stack(mem: StackAMode, from_reg: Reg, ty: Type) -> Inst {
|
413
|
-
Inst::gen_store(mem.into(), from_reg, ty)
|
414
|
-
}
|
415
|
-
|
416
|
-
fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
|
417
|
-
Inst::gen_move(to_reg, from_reg, ty)
|
418
|
-
}
|
419
|
-
|
420
|
-
fn gen_extend(
|
421
|
-
to_reg: Writable<Reg>,
|
422
|
-
from_reg: Reg,
|
423
|
-
signed: bool,
|
424
|
-
from_bits: u8,
|
425
|
-
to_bits: u8,
|
426
|
-
) -> Inst {
|
427
|
-
assert!(from_bits < to_bits);
|
428
|
-
Inst::Extend {
|
429
|
-
rd: to_reg,
|
430
|
-
rn: from_reg,
|
431
|
-
signed,
|
432
|
-
from_bits,
|
433
|
-
to_bits,
|
434
|
-
}
|
435
|
-
}
|
436
|
-
|
437
|
-
fn gen_args(args: Vec<ArgPair>) -> Inst {
|
438
|
-
Inst::Args { args }
|
439
|
-
}
|
440
|
-
|
441
|
-
fn gen_rets(rets: Vec<RetPair>) -> Inst {
|
442
|
-
Inst::Rets { rets }
|
443
|
-
}
|
444
|
-
|
445
|
-
fn gen_add_imm(
|
446
|
-
_call_conv: isa::CallConv,
|
447
|
-
into_reg: Writable<Reg>,
|
448
|
-
from_reg: Reg,
|
449
|
-
imm: u32,
|
450
|
-
) -> SmallInstVec<Inst> {
|
451
|
-
let mut insts = SmallVec::new();
|
452
|
-
if let Some(imm) = UImm12::maybe_from_u64(imm as u64) {
|
453
|
-
insts.push(Inst::LoadAddr {
|
454
|
-
rd: into_reg,
|
455
|
-
mem: MemArg::BXD12 {
|
456
|
-
base: from_reg,
|
457
|
-
index: zero_reg(),
|
458
|
-
disp: imm,
|
459
|
-
flags: MemFlags::trusted(),
|
460
|
-
},
|
461
|
-
});
|
462
|
-
} else if let Some(imm) = SImm20::maybe_from_i64(imm as i64) {
|
463
|
-
insts.push(Inst::LoadAddr {
|
464
|
-
rd: into_reg,
|
465
|
-
mem: MemArg::BXD20 {
|
466
|
-
base: from_reg,
|
467
|
-
index: zero_reg(),
|
468
|
-
disp: imm,
|
469
|
-
flags: MemFlags::trusted(),
|
470
|
-
},
|
471
|
-
});
|
472
|
-
} else {
|
473
|
-
if from_reg != into_reg.to_reg() {
|
474
|
-
insts.push(Inst::mov64(into_reg, from_reg));
|
475
|
-
}
|
476
|
-
insts.push(Inst::AluRUImm32 {
|
477
|
-
alu_op: ALUOp::AddLogical64,
|
478
|
-
rd: into_reg,
|
479
|
-
ri: into_reg.to_reg(),
|
480
|
-
imm,
|
481
|
-
});
|
482
|
-
}
|
483
|
-
insts
|
484
|
-
}
|
485
|
-
|
486
|
-
fn gen_stack_lower_bound_trap(limit_reg: Reg) -> SmallInstVec<Inst> {
|
487
|
-
let mut insts = SmallVec::new();
|
488
|
-
insts.push(Inst::CmpTrapRR {
|
489
|
-
op: CmpOp::CmpL64,
|
490
|
-
rn: stack_reg(),
|
491
|
-
rm: limit_reg,
|
492
|
-
cond: Cond::from_intcc(IntCC::UnsignedLessThanOrEqual),
|
493
|
-
trap_code: ir::TrapCode::StackOverflow,
|
494
|
-
});
|
495
|
-
insts
|
496
|
-
}
|
497
|
-
|
498
|
-
fn gen_get_stack_addr(mem: StackAMode, into_reg: Writable<Reg>) -> Inst {
|
499
|
-
let mem = mem.into();
|
500
|
-
Inst::LoadAddr { rd: into_reg, mem }
|
501
|
-
}
|
502
|
-
|
503
|
-
fn get_stacklimit_reg(_call_conv: isa::CallConv) -> Reg {
|
504
|
-
spilltmp_reg()
|
505
|
-
}
|
506
|
-
|
507
|
-
fn gen_load_base_offset(into_reg: Writable<Reg>, base: Reg, offset: i32, ty: Type) -> Inst {
|
508
|
-
let mem = MemArg::reg_plus_off(base, offset.into(), MemFlags::trusted());
|
509
|
-
Inst::gen_load(into_reg, mem, ty)
|
510
|
-
}
|
511
|
-
|
512
|
-
fn gen_store_base_offset(base: Reg, offset: i32, from_reg: Reg, ty: Type) -> Inst {
|
513
|
-
let mem = MemArg::reg_plus_off(base, offset.into(), MemFlags::trusted());
|
514
|
-
Inst::gen_store(mem, from_reg, ty)
|
515
|
-
}
|
516
|
-
|
517
|
-
fn gen_sp_reg_adjust(imm: i32) -> SmallInstVec<Inst> {
|
518
|
-
if imm == 0 {
|
519
|
-
return SmallVec::new();
|
520
|
-
}
|
521
|
-
|
522
|
-
let mut insts = SmallVec::new();
|
523
|
-
if let Ok(imm) = i16::try_from(imm) {
|
524
|
-
insts.push(Inst::AluRSImm16 {
|
525
|
-
alu_op: ALUOp::Add64,
|
526
|
-
rd: writable_stack_reg(),
|
527
|
-
ri: stack_reg(),
|
528
|
-
imm,
|
529
|
-
});
|
530
|
-
} else {
|
531
|
-
insts.push(Inst::AluRSImm32 {
|
532
|
-
alu_op: ALUOp::Add64,
|
533
|
-
rd: writable_stack_reg(),
|
534
|
-
ri: stack_reg(),
|
535
|
-
imm,
|
536
|
-
});
|
537
|
-
}
|
538
|
-
insts
|
539
|
-
}
|
540
|
-
|
541
|
-
fn gen_nominal_sp_adj(offset: i32) -> Inst {
|
542
|
-
Inst::VirtualSPOffsetAdj {
|
543
|
-
offset: offset.into(),
|
544
|
-
}
|
545
|
-
}
|
546
|
-
|
547
|
-
fn gen_prologue_frame_setup(
|
548
|
-
_call_conv: isa::CallConv,
|
549
|
-
_flags: &settings::Flags,
|
550
|
-
_isa_flags: &s390x_settings::Flags,
|
551
|
-
_frame_layout: &FrameLayout,
|
552
|
-
) -> SmallInstVec<Inst> {
|
553
|
-
SmallVec::new()
|
554
|
-
}
|
555
|
-
|
556
|
-
fn gen_epilogue_frame_restore(
|
557
|
-
call_conv: isa::CallConv,
|
558
|
-
_flags: &settings::Flags,
|
559
|
-
_isa_flags: &s390x_settings::Flags,
|
560
|
-
frame_layout: &FrameLayout,
|
561
|
-
) -> SmallInstVec<Inst> {
|
562
|
-
let mut insts = SmallVec::new();
|
563
|
-
if call_conv == isa::CallConv::Tail && frame_layout.incoming_args_size > 0 {
|
564
|
-
insts.extend(Self::gen_sp_reg_adjust(
|
565
|
-
frame_layout.incoming_args_size.try_into().unwrap(),
|
566
|
-
));
|
567
|
-
}
|
568
|
-
insts
|
569
|
-
}
|
570
|
-
|
571
|
-
fn gen_return(
|
572
|
-
_call_conv: isa::CallConv,
|
573
|
-
_isa_flags: &s390x_settings::Flags,
|
574
|
-
_frame_layout: &FrameLayout,
|
575
|
-
) -> SmallInstVec<Inst> {
|
576
|
-
smallvec![Inst::Ret { link: gpr(14) }]
|
577
|
-
}
|
578
|
-
|
579
|
-
fn gen_probestack(_insts: &mut SmallInstVec<Self::I>, _: u32) {
|
580
|
-
// TODO: implement if we ever require stack probes on an s390x host
|
581
|
-
// (unlikely unless Lucet is ported)
|
582
|
-
unimplemented!("Stack probing is unimplemented on S390x");
|
583
|
-
}
|
584
|
-
|
585
|
-
fn gen_inline_probestack(
|
586
|
-
_insts: &mut SmallInstVec<Self::I>,
|
587
|
-
_call_conv: isa::CallConv,
|
588
|
-
_frame_size: u32,
|
589
|
-
_guard_size: u32,
|
590
|
-
) {
|
591
|
-
unimplemented!("Inline stack probing is unimplemented on S390x");
|
592
|
-
}
|
593
|
-
|
594
|
-
fn gen_clobber_save(
|
595
|
-
_call_conv: isa::CallConv,
|
596
|
-
flags: &settings::Flags,
|
597
|
-
frame_layout: &FrameLayout,
|
598
|
-
) -> SmallVec<[Inst; 16]> {
|
599
|
-
let mut insts = SmallVec::new();
|
600
|
-
|
601
|
-
// Collect clobbered registers.
|
602
|
-
let (first_clobbered_gpr, clobbered_fpr) = get_clobbered_gpr_fpr(frame_layout);
|
603
|
-
if flags.unwind_info() {
|
604
|
-
insts.push(Inst::Unwind {
|
605
|
-
inst: UnwindInst::DefineNewFrame {
|
606
|
-
offset_upward_to_caller_sp: REG_SAVE_AREA_SIZE,
|
607
|
-
offset_downward_to_clobbers: frame_layout.clobber_size,
|
608
|
-
},
|
609
|
-
});
|
610
|
-
}
|
611
|
-
|
612
|
-
// Use STMG to save clobbered GPRs into save area.
|
613
|
-
if first_clobbered_gpr < 16 {
|
614
|
-
let offset = 8 * first_clobbered_gpr as i64;
|
615
|
-
insts.push(Inst::StoreMultiple64 {
|
616
|
-
rt: gpr(first_clobbered_gpr),
|
617
|
-
rt2: gpr(15),
|
618
|
-
mem: MemArg::reg_plus_off(stack_reg(), offset, MemFlags::trusted()),
|
619
|
-
});
|
620
|
-
}
|
621
|
-
if flags.unwind_info() {
|
622
|
-
for i in first_clobbered_gpr..16 {
|
623
|
-
insts.push(Inst::Unwind {
|
624
|
-
inst: UnwindInst::SaveReg {
|
625
|
-
clobber_offset: frame_layout.clobber_size + (i * 8) as u32,
|
626
|
-
reg: gpr(i).to_real_reg().unwrap(),
|
627
|
-
},
|
628
|
-
});
|
629
|
-
}
|
630
|
-
}
|
631
|
-
|
632
|
-
// Save current stack pointer value if we need to write the backchain.
|
633
|
-
if flags.preserve_frame_pointers() {
|
634
|
-
insts.push(Inst::mov64(writable_gpr(1), stack_reg()));
|
635
|
-
}
|
636
|
-
|
637
|
-
// Decrement stack pointer.
|
638
|
-
let stack_size = frame_layout.outgoing_args_size as i32
|
639
|
-
+ frame_layout.clobber_size as i32
|
640
|
-
+ frame_layout.fixed_frame_storage_size as i32;
|
641
|
-
insts.extend(Self::gen_sp_reg_adjust(-stack_size));
|
642
|
-
if flags.unwind_info() {
|
643
|
-
insts.push(Inst::Unwind {
|
644
|
-
inst: UnwindInst::StackAlloc {
|
645
|
-
size: stack_size as u32,
|
646
|
-
},
|
647
|
-
});
|
648
|
-
}
|
649
|
-
|
650
|
-
let sp_adj = frame_layout.outgoing_args_size as i32;
|
651
|
-
if sp_adj > 0 {
|
652
|
-
insts.push(Self::gen_nominal_sp_adj(sp_adj));
|
653
|
-
}
|
654
|
-
|
655
|
-
// Write the stack backchain if requested, using the value saved above.
|
656
|
-
if flags.preserve_frame_pointers() {
|
657
|
-
insts.push(Inst::Store64 {
|
658
|
-
rd: gpr(1),
|
659
|
-
mem: MemArg::reg_plus_off(stack_reg(), 0, MemFlags::trusted()),
|
660
|
-
});
|
661
|
-
}
|
662
|
-
|
663
|
-
// Save FPRs.
|
664
|
-
for (i, reg) in clobbered_fpr.iter().enumerate() {
|
665
|
-
insts.push(Inst::VecStoreLane {
|
666
|
-
size: 64,
|
667
|
-
rd: reg.to_reg().into(),
|
668
|
-
mem: MemArg::reg_plus_off(
|
669
|
-
stack_reg(),
|
670
|
-
(i * 8) as i64
|
671
|
-
+ frame_layout.outgoing_args_size as i64
|
672
|
-
+ frame_layout.fixed_frame_storage_size as i64,
|
673
|
-
MemFlags::trusted(),
|
674
|
-
),
|
675
|
-
lane_imm: 0,
|
676
|
-
});
|
677
|
-
if flags.unwind_info() {
|
678
|
-
insts.push(Inst::Unwind {
|
679
|
-
inst: UnwindInst::SaveReg {
|
680
|
-
clobber_offset: (i * 8) as u32,
|
681
|
-
reg: reg.to_reg(),
|
682
|
-
},
|
683
|
-
});
|
684
|
-
}
|
685
|
-
}
|
686
|
-
|
687
|
-
insts
|
688
|
-
}
|
689
|
-
|
690
|
-
fn gen_clobber_restore(
|
691
|
-
_call_conv: isa::CallConv,
|
692
|
-
_flags: &settings::Flags,
|
693
|
-
frame_layout: &FrameLayout,
|
694
|
-
) -> SmallVec<[Inst; 16]> {
|
695
|
-
let mut insts = SmallVec::new();
|
696
|
-
|
697
|
-
// Collect clobbered registers.
|
698
|
-
let (first_clobbered_gpr, clobbered_fpr) = get_clobbered_gpr_fpr(frame_layout);
|
699
|
-
|
700
|
-
// Restore FPRs.
|
701
|
-
for (i, reg) in clobbered_fpr.iter().enumerate() {
|
702
|
-
insts.push(Inst::VecLoadLaneUndef {
|
703
|
-
size: 64,
|
704
|
-
rd: Writable::from_reg(reg.to_reg().into()),
|
705
|
-
mem: MemArg::reg_plus_off(
|
706
|
-
stack_reg(),
|
707
|
-
(i * 8) as i64
|
708
|
-
+ frame_layout.outgoing_args_size as i64
|
709
|
-
+ frame_layout.fixed_frame_storage_size as i64,
|
710
|
-
MemFlags::trusted(),
|
711
|
-
),
|
712
|
-
lane_imm: 0,
|
713
|
-
});
|
714
|
-
}
|
715
|
-
|
716
|
-
// Increment stack pointer unless it will be restored implicitly.
|
717
|
-
let stack_size = frame_layout.outgoing_args_size as i32
|
718
|
-
+ frame_layout.clobber_size as i32
|
719
|
-
+ frame_layout.fixed_frame_storage_size as i32;
|
720
|
-
let implicit_sp_restore = first_clobbered_gpr < 16
|
721
|
-
&& SImm20::maybe_from_i64(8 * first_clobbered_gpr as i64 + stack_size as i64).is_some();
|
722
|
-
if !implicit_sp_restore {
|
723
|
-
insts.extend(Self::gen_sp_reg_adjust(stack_size));
|
724
|
-
}
|
725
|
-
|
726
|
-
// Use LMG to restore clobbered GPRs from save area.
|
727
|
-
if first_clobbered_gpr < 16 {
|
728
|
-
let mut offset = 8 * first_clobbered_gpr as i64;
|
729
|
-
if implicit_sp_restore {
|
730
|
-
offset += stack_size as i64;
|
731
|
-
}
|
732
|
-
insts.push(Inst::LoadMultiple64 {
|
733
|
-
rt: writable_gpr(first_clobbered_gpr),
|
734
|
-
rt2: writable_gpr(15),
|
735
|
-
mem: MemArg::reg_plus_off(stack_reg(), offset, MemFlags::trusted()),
|
736
|
-
});
|
737
|
-
}
|
738
|
-
|
739
|
-
insts
|
740
|
-
}
|
741
|
-
|
742
|
-
fn gen_call(
|
743
|
-
_dest: &CallDest,
|
744
|
-
_uses: CallArgList,
|
745
|
-
_defs: CallRetList,
|
746
|
-
_clobbers: PRegSet,
|
747
|
-
_opcode: ir::Opcode,
|
748
|
-
_tmp: Writable<Reg>,
|
749
|
-
_callee_conv: isa::CallConv,
|
750
|
-
_caller_conv: isa::CallConv,
|
751
|
-
_callee_pop_size: u32,
|
752
|
-
) -> SmallVec<[Inst; 2]> {
|
753
|
-
unreachable!();
|
754
|
-
}
|
755
|
-
|
756
|
-
fn gen_memcpy<F: FnMut(Type) -> Writable<Reg>>(
|
757
|
-
_call_conv: isa::CallConv,
|
758
|
-
_dst: Reg,
|
759
|
-
_src: Reg,
|
760
|
-
_size: usize,
|
761
|
-
_alloc: F,
|
762
|
-
) -> SmallVec<[Self::I; 8]> {
|
763
|
-
unimplemented!("StructArgs not implemented for S390X yet");
|
764
|
-
}
|
765
|
-
|
766
|
-
fn get_number_of_spillslots_for_value(
|
767
|
-
rc: RegClass,
|
768
|
-
_vector_scale: u32,
|
769
|
-
_isa_flags: &Self::F,
|
770
|
-
) -> u32 {
|
771
|
-
// We allocate in terms of 8-byte slots.
|
772
|
-
match rc {
|
773
|
-
RegClass::Int => 1,
|
774
|
-
RegClass::Float => 2,
|
775
|
-
RegClass::Vector => unreachable!(),
|
776
|
-
}
|
777
|
-
}
|
778
|
-
|
779
|
-
/// Get the current virtual-SP offset from an instruction-emission state.
|
780
|
-
fn get_virtual_sp_offset_from_state(s: &EmitState) -> i64 {
|
781
|
-
s.virtual_sp_offset
|
782
|
-
}
|
783
|
-
|
784
|
-
/// Get the nominal-SP-to-FP offset from an instruction-emission state.
|
785
|
-
fn get_nominal_sp_to_fp(s: &EmitState) -> i64 {
|
786
|
-
s.initial_sp_offset
|
787
|
-
}
|
788
|
-
|
789
|
-
fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv {
|
790
|
-
static MACHINE_ENV: OnceLock<MachineEnv> = OnceLock::new();
|
791
|
-
MACHINE_ENV.get_or_init(create_machine_env)
|
792
|
-
}
|
793
|
-
|
794
|
-
fn get_regs_clobbered_by_call(_call_conv_of_callee: isa::CallConv) -> PRegSet {
|
795
|
-
CLOBBERS
|
796
|
-
}
|
797
|
-
|
798
|
-
fn get_ext_mode(
|
799
|
-
_call_conv: isa::CallConv,
|
800
|
-
specified: ir::ArgumentExtension,
|
801
|
-
) -> ir::ArgumentExtension {
|
802
|
-
specified
|
803
|
-
}
|
804
|
-
|
805
|
-
fn compute_frame_layout(
|
806
|
-
call_conv: isa::CallConv,
|
807
|
-
flags: &settings::Flags,
|
808
|
-
_sig: &Signature,
|
809
|
-
regs: &[Writable<RealReg>],
|
810
|
-
_is_leaf: bool,
|
811
|
-
incoming_args_size: u32,
|
812
|
-
tail_args_size: u32,
|
813
|
-
fixed_frame_storage_size: u32,
|
814
|
-
mut outgoing_args_size: u32,
|
815
|
-
) -> FrameLayout {
|
816
|
-
assert!(
|
817
|
-
!flags.enable_pinned_reg(),
|
818
|
-
"Pinned register not supported on s390x"
|
819
|
-
);
|
820
|
-
|
821
|
-
let mut regs: Vec<Writable<RealReg>> = regs
|
822
|
-
.iter()
|
823
|
-
.cloned()
|
824
|
-
.filter(|r| is_reg_saved_in_prologue(call_conv, r.to_reg()))
|
825
|
-
.collect();
|
826
|
-
|
827
|
-
// If the front end asks to preserve frame pointers (which we do not
|
828
|
-
// really have in the s390x ABI), we use the stack backchain instead.
|
829
|
-
// For this to work in all cases, we must allocate a stack frame with
|
830
|
-
// at least the outgoing register save area even in leaf functions.
|
831
|
-
// Update our caller's outgoing_args_size to reflect this.
|
832
|
-
if flags.preserve_frame_pointers() {
|
833
|
-
if outgoing_args_size < REG_SAVE_AREA_SIZE {
|
834
|
-
outgoing_args_size = REG_SAVE_AREA_SIZE;
|
835
|
-
}
|
836
|
-
}
|
837
|
-
|
838
|
-
// We need to save/restore the link register in non-leaf functions.
|
839
|
-
// This is not included in the clobber list because we have excluded
|
840
|
-
// call instructions via the is_included_in_clobbers callback.
|
841
|
-
// We also want to enforce saving the link register in leaf functions
|
842
|
-
// for stack unwinding, if we're asked to preserve frame pointers.
|
843
|
-
if outgoing_args_size > 0 {
|
844
|
-
let link_reg = Writable::from_reg(RealReg::from(gpr_preg(14)));
|
845
|
-
if !regs.contains(&link_reg) {
|
846
|
-
regs.push(link_reg);
|
847
|
-
}
|
848
|
-
}
|
849
|
-
|
850
|
-
// Sort registers for deterministic code output. We can do an unstable
|
851
|
-
// sort because the registers will be unique (there are no dups).
|
852
|
-
regs.sort_unstable();
|
853
|
-
|
854
|
-
// Compute clobber size. We only need to count FPR save slots.
|
855
|
-
let mut clobber_size = 0;
|
856
|
-
for reg in ®s {
|
857
|
-
match reg.to_reg().class() {
|
858
|
-
RegClass::Int => {}
|
859
|
-
RegClass::Float => {
|
860
|
-
clobber_size += 8;
|
861
|
-
}
|
862
|
-
RegClass::Vector => unreachable!(),
|
863
|
-
}
|
864
|
-
}
|
865
|
-
|
866
|
-
// Return FrameLayout structure.
|
867
|
-
FrameLayout {
|
868
|
-
incoming_args_size,
|
869
|
-
tail_args_size,
|
870
|
-
setup_area_size: 0,
|
871
|
-
clobber_size,
|
872
|
-
fixed_frame_storage_size,
|
873
|
-
outgoing_args_size,
|
874
|
-
clobbered_callee_saves: regs,
|
875
|
-
}
|
876
|
-
}
|
877
|
-
}
|
878
|
-
|
879
|
-
fn is_reg_saved_in_prologue(_call_conv: isa::CallConv, r: RealReg) -> bool {
|
880
|
-
match r.class() {
|
881
|
-
RegClass::Int => {
|
882
|
-
// r6 - r15 inclusive are callee-saves.
|
883
|
-
r.hw_enc() >= 6 && r.hw_enc() <= 15
|
884
|
-
}
|
885
|
-
RegClass::Float => {
|
886
|
-
// f8 - f15 inclusive are callee-saves.
|
887
|
-
r.hw_enc() >= 8 && r.hw_enc() <= 15
|
888
|
-
}
|
889
|
-
RegClass::Vector => unreachable!(),
|
890
|
-
}
|
891
|
-
}
|
892
|
-
|
893
|
-
fn get_clobbered_gpr_fpr(frame_layout: &FrameLayout) -> (u8, &[Writable<RealReg>]) {
|
894
|
-
// Collect clobbered registers. Note we save/restore GPR always as
|
895
|
-
// a block of registers using LOAD MULTIPLE / STORE MULTIPLE, starting
|
896
|
-
// with the clobbered GPR with the lowest number up to %r15. We
|
897
|
-
// return the number of that first GPR (or 16 if none is to be saved).
|
898
|
-
let (clobbered_gpr, clobbered_fpr) = frame_layout.clobbered_callee_saves_by_class();
|
899
|
-
|
900
|
-
let first_clobbered_gpr = clobbered_gpr.split_first().map_or(16, |(first, rest)| {
|
901
|
-
let first = first.to_reg().hw_enc();
|
902
|
-
debug_assert!(rest.iter().all(|r| r.to_reg().hw_enc() > first));
|
903
|
-
first
|
904
|
-
});
|
905
|
-
|
906
|
-
(first_clobbered_gpr, clobbered_fpr)
|
907
|
-
}
|
908
|
-
|
909
|
-
const fn clobbers() -> PRegSet {
|
910
|
-
PRegSet::empty()
|
911
|
-
.with(gpr_preg(0))
|
912
|
-
.with(gpr_preg(1))
|
913
|
-
.with(gpr_preg(2))
|
914
|
-
.with(gpr_preg(3))
|
915
|
-
.with(gpr_preg(4))
|
916
|
-
.with(gpr_preg(5))
|
917
|
-
// v0 - v7 inclusive and v16 - v31 inclusive are
|
918
|
-
// caller-saves. The upper 64 bits of v8 - v15 inclusive are
|
919
|
-
// also caller-saves. However, because we cannot currently
|
920
|
-
// represent partial registers to regalloc2, we indicate here
|
921
|
-
// that every vector register is caller-save. Because this
|
922
|
-
// function is used at *callsites*, approximating in this
|
923
|
-
// direction (save more than necessary) is conservative and
|
924
|
-
// thus safe.
|
925
|
-
//
|
926
|
-
// Note that we exclude clobbers from a call instruction when
|
927
|
-
// a call instruction's callee has the same ABI as the caller
|
928
|
-
// (the current function body); this is safe (anything
|
929
|
-
// clobbered by callee can be clobbered by caller as well) and
|
930
|
-
// avoids unnecessary saves of v8-v15 in the prologue even
|
931
|
-
// though we include them as defs here.
|
932
|
-
.with(vr_preg(0))
|
933
|
-
.with(vr_preg(1))
|
934
|
-
.with(vr_preg(2))
|
935
|
-
.with(vr_preg(3))
|
936
|
-
.with(vr_preg(4))
|
937
|
-
.with(vr_preg(5))
|
938
|
-
.with(vr_preg(6))
|
939
|
-
.with(vr_preg(7))
|
940
|
-
.with(vr_preg(8))
|
941
|
-
.with(vr_preg(9))
|
942
|
-
.with(vr_preg(10))
|
943
|
-
.with(vr_preg(11))
|
944
|
-
.with(vr_preg(12))
|
945
|
-
.with(vr_preg(13))
|
946
|
-
.with(vr_preg(14))
|
947
|
-
.with(vr_preg(15))
|
948
|
-
.with(vr_preg(16))
|
949
|
-
.with(vr_preg(17))
|
950
|
-
.with(vr_preg(18))
|
951
|
-
.with(vr_preg(19))
|
952
|
-
.with(vr_preg(20))
|
953
|
-
.with(vr_preg(21))
|
954
|
-
.with(vr_preg(22))
|
955
|
-
.with(vr_preg(23))
|
956
|
-
.with(vr_preg(24))
|
957
|
-
.with(vr_preg(25))
|
958
|
-
.with(vr_preg(26))
|
959
|
-
.with(vr_preg(27))
|
960
|
-
.with(vr_preg(28))
|
961
|
-
.with(vr_preg(29))
|
962
|
-
.with(vr_preg(30))
|
963
|
-
.with(vr_preg(31))
|
964
|
-
}
|
965
|
-
|
966
|
-
const CLOBBERS: PRegSet = clobbers();
|
967
|
-
|
968
|
-
fn create_machine_env() -> MachineEnv {
|
969
|
-
MachineEnv {
|
970
|
-
preferred_regs_by_class: [
|
971
|
-
vec![
|
972
|
-
// no r0; can't use for addressing?
|
973
|
-
// no r1; it is our spilltmp.
|
974
|
-
gpr_preg(2),
|
975
|
-
gpr_preg(3),
|
976
|
-
gpr_preg(4),
|
977
|
-
gpr_preg(5),
|
978
|
-
],
|
979
|
-
vec![
|
980
|
-
vr_preg(0),
|
981
|
-
vr_preg(1),
|
982
|
-
vr_preg(2),
|
983
|
-
vr_preg(3),
|
984
|
-
vr_preg(4),
|
985
|
-
vr_preg(5),
|
986
|
-
vr_preg(6),
|
987
|
-
vr_preg(7),
|
988
|
-
vr_preg(16),
|
989
|
-
vr_preg(17),
|
990
|
-
vr_preg(18),
|
991
|
-
vr_preg(19),
|
992
|
-
vr_preg(20),
|
993
|
-
vr_preg(21),
|
994
|
-
vr_preg(22),
|
995
|
-
vr_preg(23),
|
996
|
-
vr_preg(24),
|
997
|
-
vr_preg(25),
|
998
|
-
vr_preg(26),
|
999
|
-
vr_preg(27),
|
1000
|
-
vr_preg(28),
|
1001
|
-
vr_preg(29),
|
1002
|
-
vr_preg(30),
|
1003
|
-
vr_preg(31),
|
1004
|
-
],
|
1005
|
-
// Vector Regclass is unused
|
1006
|
-
vec![],
|
1007
|
-
],
|
1008
|
-
non_preferred_regs_by_class: [
|
1009
|
-
vec![
|
1010
|
-
gpr_preg(6),
|
1011
|
-
gpr_preg(7),
|
1012
|
-
gpr_preg(8),
|
1013
|
-
gpr_preg(9),
|
1014
|
-
gpr_preg(10),
|
1015
|
-
gpr_preg(11),
|
1016
|
-
gpr_preg(12),
|
1017
|
-
gpr_preg(13),
|
1018
|
-
gpr_preg(14),
|
1019
|
-
// no r15; it is the stack pointer.
|
1020
|
-
],
|
1021
|
-
vec![
|
1022
|
-
vr_preg(8),
|
1023
|
-
vr_preg(9),
|
1024
|
-
vr_preg(10),
|
1025
|
-
vr_preg(11),
|
1026
|
-
vr_preg(12),
|
1027
|
-
vr_preg(13),
|
1028
|
-
vr_preg(14),
|
1029
|
-
vr_preg(15),
|
1030
|
-
],
|
1031
|
-
// Vector Regclass is unused
|
1032
|
-
vec![],
|
1033
|
-
],
|
1034
|
-
fixed_stack_slots: vec![],
|
1035
|
-
scratch_by_class: [None, None, None],
|
1036
|
-
}
|
1037
|
-
}
|