wasmtime 16.0.0 → 17.0.0
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- checksums.yaml +4 -4
- data/Cargo.lock +103 -79
- data/ext/Cargo.toml +7 -6
- data/ext/cargo-vendor/cranelift-bforest-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.104.0/Cargo.toml +40 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/Cargo.toml +175 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/isa/aarch64/lower/isle.rs +882 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/isa/x64/abi.rs +1305 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/isle_prelude.rs +957 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/machinst/isle.rs +908 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/machinst/mod.rs +558 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/machinst/pcc.rs +159 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/bitops.isle +188 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/cprop.isle +248 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/icmp.isle +197 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/spaceship.isle +194 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts.rs +265 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/prelude.isle +641 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/prelude_lower.isle +1073 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/prelude_opt.isle +134 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.104.0/Cargo.toml +35 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.104.0/Cargo.toml +22 -0
- data/ext/cargo-vendor/cranelift-control-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.104.0/Cargo.toml +30 -0
- data/ext/cargo-vendor/cranelift-entity-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.104.0/Cargo.toml +50 -0
- data/ext/cargo-vendor/cranelift-entity-0.104.0/src/primary.rs +541 -0
- data/ext/cargo-vendor/cranelift-frontend-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.104.0/Cargo.toml +68 -0
- data/ext/cargo-vendor/cranelift-isle-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.104.0/Cargo.toml +46 -0
- data/ext/cargo-vendor/cranelift-native-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-native-0.104.0/Cargo.toml +43 -0
- data/ext/cargo-vendor/cranelift-wasm-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-wasm-0.104.0/Cargo.toml +106 -0
- data/ext/cargo-vendor/cranelift-wasm-0.104.0/src/code_translator.rs +3646 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/Cargo.toml +49 -0
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- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/src/clocks.rs +56 -0
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- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/src/noop_scheduler.rs +25 -0
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- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/tests/random.rs +17 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/tests/scheduler.rs +24 -0
- data/ext/cargo-vendor/rand_pcg-0.3.1/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/wasi-common-17.0.0/Cargo.toml +131 -0
- data/ext/cargo-vendor/wasi-common-17.0.0/src/error.rs +26 -0
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- data/ext/cargo-vendor/wasmtime-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/Cargo.toml +211 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/component.rs +545 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/instance.rs +815 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/linker.rs +580 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/matching.rs +215 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/mod.rs +351 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/resource_table.rs +350 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/resources.rs +823 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/config.rs +2428 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/func/typed.rs +638 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/lib.rs +526 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/store.rs +2389 -0
- data/ext/cargo-vendor/wasmtime-asm-macros-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-asm-macros-17.0.0/Cargo.toml +22 -0
- data/ext/cargo-vendor/wasmtime-cache-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-cache-17.0.0/Cargo.toml +81 -0
- data/ext/cargo-vendor/wasmtime-component-macro-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-component-macro-17.0.0/Cargo.toml +67 -0
- data/ext/cargo-vendor/wasmtime-component-macro-17.0.0/src/bindgen.rs +371 -0
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- data/ext/cargo-vendor/wasmtime-component-util-17.0.0/Cargo.toml +25 -0
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- data/ext/cargo-vendor/wasmtime-cranelift-shared-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-cranelift-shared-17.0.0/Cargo.toml +71 -0
- data/ext/cargo-vendor/wasmtime-environ-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-environ-17.0.0/Cargo.lock +726 -0
- data/ext/cargo-vendor/wasmtime-environ-17.0.0/Cargo.toml +125 -0
- data/ext/cargo-vendor/wasmtime-environ-17.0.0/examples/factc.rs +205 -0
- data/ext/cargo-vendor/wasmtime-fiber-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-fiber-17.0.0/Cargo.toml +63 -0
- data/ext/cargo-vendor/wasmtime-jit-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-jit-17.0.0/Cargo.toml +125 -0
- data/ext/cargo-vendor/wasmtime-jit-debug-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-jit-debug-17.0.0/Cargo.toml +67 -0
- data/ext/cargo-vendor/wasmtime-jit-icache-coherence-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-jit-icache-coherence-17.0.0/Cargo.toml +46 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/Cargo.toml +139 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/instance/allocator/pooling/memory_pool.rs +997 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/instance/allocator/pooling.rs +658 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/memory.rs +973 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/parking_spot.rs +622 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/sys/windows/mmap.rs +216 -0
- data/ext/cargo-vendor/wasmtime-types-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-types-17.0.0/Cargo.toml +36 -0
- data/ext/cargo-vendor/wasmtime-versioned-export-macros-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-versioned-export-macros-17.0.0/Cargo.toml +32 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/Cargo.toml +261 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/ctx.rs +333 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/filesystem.rs +325 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/clocks.rs +103 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/filesystem.rs +1069 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/instance_network.rs +15 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/network.rs +625 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/tcp.rs +605 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/udp.rs +530 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/mod.rs +327 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/network.rs +108 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/poll.rs +175 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/preview1.rs +2362 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/stream.rs +181 -0
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- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/tests/all/async_.rs +364 -0
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- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/cli/environment.wit +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/cli/exit.wit +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/cli/run.wit +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/http/handler.wit +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/sockets/instance-network.wit +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/witx/preview0/typenames.witx +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/witx/preview0/wasi_unstable.witx +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/witx/preview1/typenames.witx +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/witx/preview1/wasi_snapshot_preview1.witx +0 -0
- /data/ext/cargo-vendor/{wasmtime-winch-16.0.0 → wasmtime-winch-17.0.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{wasmtime-winch-16.0.0 → wasmtime-winch-17.0.0}/src/builder.rs +0 -0
- /data/ext/cargo-vendor/{wasmtime-winch-16.0.0 → wasmtime-winch-17.0.0}/src/compiler.rs +0 -0
- /data/ext/cargo-vendor/{wasmtime-winch-16.0.0 → wasmtime-winch-17.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{wasmtime-wit-bindgen-16.0.0 → wasmtime-wit-bindgen-17.0.0}/src/rust.rs +0 -0
- /data/ext/cargo-vendor/{wasmtime-wit-bindgen-16.0.0 → wasmtime-wit-bindgen-17.0.0}/src/source.rs +0 -0
- /data/ext/cargo-vendor/{wasmtime-wit-bindgen-16.0.0 → wasmtime-wit-bindgen-17.0.0}/src/types.rs +0 -0
- /data/ext/cargo-vendor/{wasmtime-wmemcheck-16.0.0 → wasmtime-wmemcheck-17.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/README.md +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/borrow.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/error.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/guest_type.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/region.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/wasmtime.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/README.md +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/codegen_settings.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/config.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/funcs.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/lifetimes.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/module_trait.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/names.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/error.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/flags.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/handle.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/mod.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/record.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/variant.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/wasmtime.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-macro-16.0.0 → wiggle-macro-17.0.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{wiggle-macro-16.0.0 → wiggle-macro-17.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/build.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/abi/local.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/abi/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/codegen/builtin.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/codegen/call.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/codegen/control.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/codegen/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/frame/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/abi.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/address.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/asm.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/regs.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/reg.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/x64/abi.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/x64/address.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/x64/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/x64/regs.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/regalloc.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/regset.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/trampoline.rs +0 -0
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regs.regs()[i]
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}
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fn value_slice_len(&mut self, slice: ValueSlice) -> usize {
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list.len(&self.lower_ctx.dfg().value_lists) - off
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#[inline]
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fn value_slice_get(&mut self, slice: ValueSlice, idx: usize) -> Value {
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list.get(off + idx, &self.lower_ctx.dfg().value_lists)
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.unwrap()
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r.to_reg()
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fn inst_results(&mut self, inst: Inst) -> ValueSlice {
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fn inst_data(&mut self, inst: Inst) -> InstructionData {
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}
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#[inline]
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fn def_inst(&mut self, val: Value) -> Option<Inst> {
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self.lower_ctx.dfg().value_def(val).inst()
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}
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#[inline]
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fn i64_from_iconst(&mut self, val: Value) -> Option<i64> {
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let inst = self.def_inst(val)?;
|
226
|
-
let constant = self.lower_ctx.get_constant(inst)? as i64;
|
227
|
-
let ty = self.lower_ctx.output_ty(inst, 0);
|
228
|
-
let shift_amt = std::cmp::max(0, 64 - self.ty_bits(ty));
|
229
|
-
Some((constant << shift_amt) >> shift_amt)
|
230
|
-
}
|
231
|
-
|
232
|
-
fn zero_value(&mut self, value: Value) -> Option<Value> {
|
233
|
-
let insn = self.def_inst(value);
|
234
|
-
if insn.is_some() {
|
235
|
-
let insn = insn.unwrap();
|
236
|
-
let inst_data = self.lower_ctx.data(insn);
|
237
|
-
match inst_data {
|
238
|
-
InstructionData::Unary {
|
239
|
-
opcode: Opcode::Splat,
|
240
|
-
arg,
|
241
|
-
} => {
|
242
|
-
let arg = arg.clone();
|
243
|
-
return self.zero_value(arg);
|
244
|
-
}
|
245
|
-
InstructionData::UnaryConst {
|
246
|
-
opcode: Opcode::Vconst,
|
247
|
-
constant_handle,
|
248
|
-
} => {
|
249
|
-
let constant_data =
|
250
|
-
self.lower_ctx.get_constant_data(*constant_handle).clone();
|
251
|
-
if constant_data.into_vec().iter().any(|&x| x != 0) {
|
252
|
-
return None;
|
253
|
-
} else {
|
254
|
-
return Some(value);
|
255
|
-
}
|
256
|
-
}
|
257
|
-
InstructionData::UnaryImm { imm, .. } => {
|
258
|
-
if imm.bits() == 0 {
|
259
|
-
return Some(value);
|
260
|
-
} else {
|
261
|
-
return None;
|
262
|
-
}
|
263
|
-
}
|
264
|
-
InstructionData::UnaryIeee32 { imm, .. } => {
|
265
|
-
if imm.bits() == 0 {
|
266
|
-
return Some(value);
|
267
|
-
} else {
|
268
|
-
return None;
|
269
|
-
}
|
270
|
-
}
|
271
|
-
InstructionData::UnaryIeee64 { imm, .. } => {
|
272
|
-
if imm.bits() == 0 {
|
273
|
-
return Some(value);
|
274
|
-
} else {
|
275
|
-
return None;
|
276
|
-
}
|
277
|
-
}
|
278
|
-
_ => None,
|
279
|
-
}
|
280
|
-
} else {
|
281
|
-
None
|
282
|
-
}
|
283
|
-
}
|
284
|
-
|
285
|
-
#[inline]
|
286
|
-
fn tls_model(&mut self, _: Type) -> TlsModel {
|
287
|
-
self.backend.flags().tls_model()
|
288
|
-
}
|
289
|
-
|
290
|
-
#[inline]
|
291
|
-
fn tls_model_is_elf_gd(&mut self) -> Option<()> {
|
292
|
-
if self.backend.flags().tls_model() == TlsModel::ElfGd {
|
293
|
-
Some(())
|
294
|
-
} else {
|
295
|
-
None
|
296
|
-
}
|
297
|
-
}
|
298
|
-
|
299
|
-
#[inline]
|
300
|
-
fn tls_model_is_macho(&mut self) -> Option<()> {
|
301
|
-
if self.backend.flags().tls_model() == TlsModel::Macho {
|
302
|
-
Some(())
|
303
|
-
} else {
|
304
|
-
None
|
305
|
-
}
|
306
|
-
}
|
307
|
-
|
308
|
-
#[inline]
|
309
|
-
fn tls_model_is_coff(&mut self) -> Option<()> {
|
310
|
-
if self.backend.flags().tls_model() == TlsModel::Coff {
|
311
|
-
Some(())
|
312
|
-
} else {
|
313
|
-
None
|
314
|
-
}
|
315
|
-
}
|
316
|
-
|
317
|
-
#[inline]
|
318
|
-
fn preserve_frame_pointers(&mut self) -> Option<()> {
|
319
|
-
if self.backend.flags().preserve_frame_pointers() {
|
320
|
-
Some(())
|
321
|
-
} else {
|
322
|
-
None
|
323
|
-
}
|
324
|
-
}
|
325
|
-
|
326
|
-
#[inline]
|
327
|
-
fn func_ref_data(&mut self, func_ref: FuncRef) -> (SigRef, ExternalName, RelocDistance) {
|
328
|
-
let funcdata = &self.lower_ctx.dfg().ext_funcs[func_ref];
|
329
|
-
let reloc_distance = if funcdata.colocated {
|
330
|
-
RelocDistance::Near
|
331
|
-
} else {
|
332
|
-
RelocDistance::Far
|
333
|
-
};
|
334
|
-
(funcdata.signature, funcdata.name.clone(), reloc_distance)
|
335
|
-
}
|
336
|
-
|
337
|
-
#[inline]
|
338
|
-
fn box_external_name(&mut self, extname: ExternalName) -> BoxExternalName {
|
339
|
-
Box::new(extname)
|
340
|
-
}
|
341
|
-
|
342
|
-
#[inline]
|
343
|
-
fn symbol_value_data(
|
344
|
-
&mut self,
|
345
|
-
global_value: GlobalValue,
|
346
|
-
) -> Option<(ExternalName, RelocDistance, i64)> {
|
347
|
-
let (name, reloc, offset) = self.lower_ctx.symbol_value_data(global_value)?;
|
348
|
-
Some((name.clone(), reloc, offset))
|
349
|
-
}
|
350
|
-
|
351
|
-
#[inline]
|
352
|
-
fn reloc_distance_near(&mut self, dist: RelocDistance) -> Option<()> {
|
353
|
-
if dist == RelocDistance::Near {
|
354
|
-
Some(())
|
355
|
-
} else {
|
356
|
-
None
|
357
|
-
}
|
358
|
-
}
|
359
|
-
|
360
|
-
#[inline]
|
361
|
-
fn u128_from_immediate(&mut self, imm: Immediate) -> Option<u128> {
|
362
|
-
let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
|
363
|
-
Some(u128::from_le_bytes(bytes.try_into().ok()?))
|
364
|
-
}
|
365
|
-
|
366
|
-
#[inline]
|
367
|
-
fn vconst_from_immediate(&mut self, imm: Immediate) -> Option<VCodeConstant> {
|
368
|
-
Some(self.lower_ctx.use_constant(VCodeConstantData::Generated(
|
369
|
-
self.lower_ctx.get_immediate_data(imm).clone(),
|
370
|
-
)))
|
371
|
-
}
|
372
|
-
|
373
|
-
#[inline]
|
374
|
-
fn vec_mask_from_immediate(&mut self, imm: Immediate) -> Option<VecMask> {
|
375
|
-
let data = self.lower_ctx.get_immediate_data(imm);
|
376
|
-
if data.len() == 16 {
|
377
|
-
Some(Vec::from(data.as_slice()))
|
378
|
-
} else {
|
379
|
-
None
|
380
|
-
}
|
381
|
-
}
|
382
|
-
|
383
|
-
#[inline]
|
384
|
-
fn u64_from_constant(&mut self, constant: Constant) -> Option<u64> {
|
385
|
-
let bytes = self.lower_ctx.get_constant_data(constant).as_slice();
|
386
|
-
Some(u64::from_le_bytes(bytes.try_into().ok()?))
|
387
|
-
}
|
388
|
-
|
389
|
-
#[inline]
|
390
|
-
fn u128_from_constant(&mut self, constant: Constant) -> Option<u128> {
|
391
|
-
let bytes = self.lower_ctx.get_constant_data(constant).as_slice();
|
392
|
-
Some(u128::from_le_bytes(bytes.try_into().ok()?))
|
393
|
-
}
|
394
|
-
|
395
|
-
#[inline]
|
396
|
-
fn emit_u64_le_const(&mut self, value: u64) -> VCodeConstant {
|
397
|
-
let data = VCodeConstantData::U64(value.to_le_bytes());
|
398
|
-
self.lower_ctx.use_constant(data)
|
399
|
-
}
|
400
|
-
|
401
|
-
#[inline]
|
402
|
-
fn emit_u128_le_const(&mut self, value: u128) -> VCodeConstant {
|
403
|
-
let data = VCodeConstantData::Generated(value.to_le_bytes().as_slice().into());
|
404
|
-
self.lower_ctx.use_constant(data)
|
405
|
-
}
|
406
|
-
|
407
|
-
#[inline]
|
408
|
-
fn const_to_vconst(&mut self, constant: Constant) -> VCodeConstant {
|
409
|
-
self.lower_ctx.use_constant(VCodeConstantData::Pool(
|
410
|
-
constant,
|
411
|
-
self.lower_ctx.get_constant_data(constant).clone(),
|
412
|
-
))
|
413
|
-
}
|
414
|
-
|
415
|
-
fn only_writable_reg(&mut self, regs: WritableValueRegs) -> Option<WritableReg> {
|
416
|
-
regs.only_reg()
|
417
|
-
}
|
418
|
-
|
419
|
-
fn writable_regs_get(&mut self, regs: WritableValueRegs, idx: usize) -> WritableReg {
|
420
|
-
regs.regs()[idx]
|
421
|
-
}
|
422
|
-
|
423
|
-
fn abi_num_args(&mut self, abi: Sig) -> usize {
|
424
|
-
self.lower_ctx.sigs().num_args(abi)
|
425
|
-
}
|
426
|
-
|
427
|
-
fn abi_get_arg(&mut self, abi: Sig, idx: usize) -> ABIArg {
|
428
|
-
self.lower_ctx.sigs().get_arg(abi, idx)
|
429
|
-
}
|
430
|
-
|
431
|
-
fn abi_num_rets(&mut self, abi: Sig) -> usize {
|
432
|
-
self.lower_ctx.sigs().num_rets(abi)
|
433
|
-
}
|
434
|
-
|
435
|
-
fn abi_get_ret(&mut self, abi: Sig, idx: usize) -> ABIArg {
|
436
|
-
self.lower_ctx.sigs().get_ret(abi, idx)
|
437
|
-
}
|
438
|
-
|
439
|
-
fn abi_ret_arg(&mut self, abi: Sig) -> Option<ABIArg> {
|
440
|
-
self.lower_ctx.sigs().get_ret_arg(abi)
|
441
|
-
}
|
442
|
-
|
443
|
-
fn abi_no_ret_arg(&mut self, abi: Sig) -> Option<()> {
|
444
|
-
if let Some(_) = self.lower_ctx.sigs().get_ret_arg(abi) {
|
445
|
-
None
|
446
|
-
} else {
|
447
|
-
Some(())
|
448
|
-
}
|
449
|
-
}
|
450
|
-
|
451
|
-
fn abi_sized_stack_arg_space(&mut self, abi: Sig) -> i64 {
|
452
|
-
self.lower_ctx.sigs()[abi].sized_stack_arg_space()
|
453
|
-
}
|
454
|
-
|
455
|
-
fn abi_sized_stack_ret_space(&mut self, abi: Sig) -> i64 {
|
456
|
-
self.lower_ctx.sigs()[abi].sized_stack_ret_space()
|
457
|
-
}
|
458
|
-
|
459
|
-
fn abi_arg_only_slot(&mut self, arg: &ABIArg) -> Option<ABIArgSlot> {
|
460
|
-
match arg {
|
461
|
-
&ABIArg::Slots { ref slots, .. } => {
|
462
|
-
if slots.len() == 1 {
|
463
|
-
Some(slots[0])
|
464
|
-
} else {
|
465
|
-
None
|
466
|
-
}
|
467
|
-
}
|
468
|
-
_ => None,
|
469
|
-
}
|
470
|
-
}
|
471
|
-
|
472
|
-
fn abi_arg_struct_pointer(&mut self, arg: &ABIArg) -> Option<(ABIArgSlot, i64, u64)> {
|
473
|
-
match arg {
|
474
|
-
&ABIArg::StructArg {
|
475
|
-
pointer,
|
476
|
-
offset,
|
477
|
-
size,
|
478
|
-
..
|
479
|
-
} => {
|
480
|
-
if let Some(pointer) = pointer {
|
481
|
-
Some((pointer, offset, size))
|
482
|
-
} else {
|
483
|
-
None
|
484
|
-
}
|
485
|
-
}
|
486
|
-
_ => None,
|
487
|
-
}
|
488
|
-
}
|
489
|
-
|
490
|
-
fn abi_arg_implicit_pointer(&mut self, arg: &ABIArg) -> Option<(ABIArgSlot, i64, Type)> {
|
491
|
-
match arg {
|
492
|
-
&ABIArg::ImplicitPtrArg {
|
493
|
-
pointer,
|
494
|
-
offset,
|
495
|
-
ty,
|
496
|
-
..
|
497
|
-
} => Some((pointer, offset, ty)),
|
498
|
-
_ => None,
|
499
|
-
}
|
500
|
-
}
|
501
|
-
|
502
|
-
fn abi_stackslot_addr(
|
503
|
-
&mut self,
|
504
|
-
dst: WritableReg,
|
505
|
-
stack_slot: StackSlot,
|
506
|
-
offset: Offset32,
|
507
|
-
) -> MInst {
|
508
|
-
let offset = u32::try_from(i32::from(offset)).unwrap();
|
509
|
-
self.lower_ctx
|
510
|
-
.abi()
|
511
|
-
.sized_stackslot_addr(stack_slot, offset, dst)
|
512
|
-
}
|
513
|
-
|
514
|
-
fn abi_dynamic_stackslot_addr(
|
515
|
-
&mut self,
|
516
|
-
dst: WritableReg,
|
517
|
-
stack_slot: DynamicStackSlot,
|
518
|
-
) -> MInst {
|
519
|
-
assert!(self
|
520
|
-
.lower_ctx
|
521
|
-
.abi()
|
522
|
-
.dynamic_stackslot_offsets()
|
523
|
-
.is_valid(stack_slot));
|
524
|
-
self.lower_ctx.abi().dynamic_stackslot_addr(stack_slot, dst)
|
525
|
-
}
|
526
|
-
|
527
|
-
fn real_reg_to_reg(&mut self, reg: RealReg) -> Reg {
|
528
|
-
Reg::from(reg)
|
529
|
-
}
|
530
|
-
|
531
|
-
fn real_reg_to_writable_reg(&mut self, reg: RealReg) -> WritableReg {
|
532
|
-
Writable::from_reg(Reg::from(reg))
|
533
|
-
}
|
534
|
-
|
535
|
-
fn is_sinkable_inst(&mut self, val: Value) -> Option<Inst> {
|
536
|
-
let input = self.lower_ctx.get_value_as_source_or_const(val);
|
537
|
-
|
538
|
-
if let InputSourceInst::UniqueUse(inst, _) = input.inst {
|
539
|
-
Some(inst)
|
540
|
-
} else {
|
541
|
-
None
|
542
|
-
}
|
543
|
-
}
|
544
|
-
|
545
|
-
#[inline]
|
546
|
-
fn sink_inst(&mut self, inst: Inst) {
|
547
|
-
self.lower_ctx.sink_inst(inst);
|
548
|
-
}
|
549
|
-
|
550
|
-
#[inline]
|
551
|
-
fn maybe_uextend(&mut self, value: Value) -> Option<Value> {
|
552
|
-
if let Some(def_inst) = self.def_inst(value) {
|
553
|
-
if let InstructionData::Unary {
|
554
|
-
opcode: Opcode::Uextend,
|
555
|
-
arg,
|
556
|
-
} = self.lower_ctx.data(def_inst)
|
557
|
-
{
|
558
|
-
return Some(*arg);
|
559
|
-
}
|
560
|
-
}
|
561
|
-
|
562
|
-
Some(value)
|
563
|
-
}
|
564
|
-
|
565
|
-
#[inline]
|
566
|
-
fn preg_to_reg(&mut self, preg: PReg) -> Reg {
|
567
|
-
preg.into()
|
568
|
-
}
|
569
|
-
|
570
|
-
#[inline]
|
571
|
-
fn gen_move(&mut self, ty: Type, dst: WritableReg, src: Reg) -> MInst {
|
572
|
-
MInst::gen_move(dst, src, ty)
|
573
|
-
}
|
574
|
-
|
575
|
-
/// Generate the return instruction.
|
576
|
-
fn gen_return(&mut self, (list, off): ValueSlice) {
|
577
|
-
let rets = (off..list.len(&self.lower_ctx.dfg().value_lists))
|
578
|
-
.map(|ix| {
|
579
|
-
let val = list.get(ix, &self.lower_ctx.dfg().value_lists).unwrap();
|
580
|
-
self.put_in_regs(val)
|
581
|
-
})
|
582
|
-
.collect();
|
583
|
-
self.lower_ctx.gen_return(rets);
|
584
|
-
}
|
585
|
-
|
586
|
-
/// Same as `shuffle32_from_imm`, but for 64-bit lane shuffles.
|
587
|
-
fn shuffle64_from_imm(&mut self, imm: Immediate) -> Option<(u8, u8)> {
|
588
|
-
use crate::machinst::isle::shuffle_imm_as_le_lane_idx;
|
589
|
-
|
590
|
-
let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
|
591
|
-
Some((
|
592
|
-
shuffle_imm_as_le_lane_idx(8, &bytes[0..8])?,
|
593
|
-
shuffle_imm_as_le_lane_idx(8, &bytes[8..16])?,
|
594
|
-
))
|
595
|
-
}
|
596
|
-
|
597
|
-
/// Attempts to interpret the shuffle immediate `imm` as a shuffle of
|
598
|
-
/// 32-bit lanes, returning four integers, each of which is less than 8,
|
599
|
-
/// which represents a permutation of 32-bit lanes as specified by
|
600
|
-
/// `imm`.
|
601
|
-
///
|
602
|
-
/// For example the shuffle immediate
|
603
|
-
///
|
604
|
-
/// `0 1 2 3 8 9 10 11 16 17 18 19 24 25 26 27`
|
605
|
-
///
|
606
|
-
/// would return `Some((0, 2, 4, 6))`.
|
607
|
-
fn shuffle32_from_imm(&mut self, imm: Immediate) -> Option<(u8, u8, u8, u8)> {
|
608
|
-
use crate::machinst::isle::shuffle_imm_as_le_lane_idx;
|
609
|
-
|
610
|
-
let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
|
611
|
-
Some((
|
612
|
-
shuffle_imm_as_le_lane_idx(4, &bytes[0..4])?,
|
613
|
-
shuffle_imm_as_le_lane_idx(4, &bytes[4..8])?,
|
614
|
-
shuffle_imm_as_le_lane_idx(4, &bytes[8..12])?,
|
615
|
-
shuffle_imm_as_le_lane_idx(4, &bytes[12..16])?,
|
616
|
-
))
|
617
|
-
}
|
618
|
-
|
619
|
-
/// Same as `shuffle32_from_imm`, but for 16-bit lane shuffles.
|
620
|
-
fn shuffle16_from_imm(
|
621
|
-
&mut self,
|
622
|
-
imm: Immediate,
|
623
|
-
) -> Option<(u8, u8, u8, u8, u8, u8, u8, u8)> {
|
624
|
-
use crate::machinst::isle::shuffle_imm_as_le_lane_idx;
|
625
|
-
let bytes = self.lower_ctx.get_immediate_data(imm).as_slice();
|
626
|
-
Some((
|
627
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[0..2])?,
|
628
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[2..4])?,
|
629
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[4..6])?,
|
630
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[6..8])?,
|
631
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[8..10])?,
|
632
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[10..12])?,
|
633
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[12..14])?,
|
634
|
-
shuffle_imm_as_le_lane_idx(2, &bytes[14..16])?,
|
635
|
-
))
|
636
|
-
}
|
637
|
-
|
638
|
-
fn safe_divisor_from_imm64(&mut self, ty: Type, val: Imm64) -> Option<u64> {
|
639
|
-
let minus_one = if ty.bytes() == 8 {
|
640
|
-
-1
|
641
|
-
} else {
|
642
|
-
(1 << (ty.bytes() * 8)) - 1
|
643
|
-
};
|
644
|
-
let bits = val.bits() & minus_one;
|
645
|
-
if bits == 0 || bits == minus_one {
|
646
|
-
None
|
647
|
-
} else {
|
648
|
-
Some(bits as u64)
|
649
|
-
}
|
650
|
-
}
|
651
|
-
|
652
|
-
fn single_target(&mut self, targets: &MachLabelSlice) -> Option<MachLabel> {
|
653
|
-
if targets.len() == 1 {
|
654
|
-
Some(targets[0])
|
655
|
-
} else {
|
656
|
-
None
|
657
|
-
}
|
658
|
-
}
|
659
|
-
|
660
|
-
fn two_targets(&mut self, targets: &MachLabelSlice) -> Option<(MachLabel, MachLabel)> {
|
661
|
-
if targets.len() == 2 {
|
662
|
-
Some((targets[0], targets[1]))
|
663
|
-
} else {
|
664
|
-
None
|
665
|
-
}
|
666
|
-
}
|
667
|
-
|
668
|
-
fn jump_table_targets(
|
669
|
-
&mut self,
|
670
|
-
targets: &MachLabelSlice,
|
671
|
-
) -> Option<(MachLabel, BoxVecMachLabel)> {
|
672
|
-
use std::boxed::Box;
|
673
|
-
if targets.is_empty() {
|
674
|
-
return None;
|
675
|
-
}
|
676
|
-
|
677
|
-
let default_label = targets[0];
|
678
|
-
let jt_targets = Box::new(targets[1..].to_vec());
|
679
|
-
Some((default_label, jt_targets))
|
680
|
-
}
|
681
|
-
|
682
|
-
fn jump_table_size(&mut self, targets: &BoxVecMachLabel) -> u32 {
|
683
|
-
targets.len() as u32
|
684
|
-
}
|
685
|
-
|
686
|
-
fn add_range_fact(&mut self, reg: Reg, bits: u16, min: u64, max: u64) -> Reg {
|
687
|
-
self.lower_ctx.add_range_fact(reg, bits, min, max);
|
688
|
-
reg
|
689
|
-
}
|
690
|
-
};
|
691
|
-
}
|
692
|
-
|
693
|
-
/// Returns the `size`-byte lane referred to by the shuffle immediate specified
|
694
|
-
/// in `bytes`.
|
695
|
-
///
|
696
|
-
/// This helper is used by `shuffleNN_from_imm` above and is used to interpret a
|
697
|
-
/// byte-based shuffle as a higher-level shuffle of bigger lanes. This will see
|
698
|
-
/// if the `bytes` specified, which must have `size` length, specifies a lane in
|
699
|
-
/// vectors aligned to a `size`-byte boundary.
|
700
|
-
///
|
701
|
-
/// Returns `None` if `bytes` doesn't specify a `size`-byte lane aligned
|
702
|
-
/// appropriately, or returns `Some(n)` where `n` is the index of the lane being
|
703
|
-
/// shuffled.
|
704
|
-
pub fn shuffle_imm_as_le_lane_idx(size: u8, bytes: &[u8]) -> Option<u8> {
|
705
|
-
assert_eq!(bytes.len(), usize::from(size));
|
706
|
-
|
707
|
-
// The first index in `bytes` must be aligned to a `size` boundary for the
|
708
|
-
// bytes to be a valid specifier for a lane of `size` bytes.
|
709
|
-
if bytes[0] % size != 0 {
|
710
|
-
return None;
|
711
|
-
}
|
712
|
-
|
713
|
-
// Afterwards the bytes must all be one larger than the prior to specify a
|
714
|
-
// contiguous sequence of bytes that's being shuffled. Basically `bytes`
|
715
|
-
// must refer to the entire `size`-byte lane, in little-endian order.
|
716
|
-
for i in 0..size - 1 {
|
717
|
-
let idx = usize::from(i);
|
718
|
-
if bytes[idx] + 1 != bytes[idx + 1] {
|
719
|
-
return None;
|
720
|
-
}
|
721
|
-
}
|
722
|
-
|
723
|
-
// All of the `bytes` are in-order, meaning that this is a valid shuffle
|
724
|
-
// immediate to specify a lane of `size` bytes. The index, when viewed as
|
725
|
-
// `size`-byte immediates, will be the first byte divided by the byte size.
|
726
|
-
Some(bytes[0] / size)
|
727
|
-
}
|
728
|
-
|
729
|
-
/// Helpers specifically for machines that use `abi::CallSite`.
|
730
|
-
#[macro_export]
|
731
|
-
#[doc(hidden)]
|
732
|
-
macro_rules! isle_prelude_caller_methods {
|
733
|
-
($abispec:ty, $abicaller:ty) => {
|
734
|
-
fn gen_call(
|
735
|
-
&mut self,
|
736
|
-
sig_ref: SigRef,
|
737
|
-
extname: ExternalName,
|
738
|
-
dist: RelocDistance,
|
739
|
-
args @ (inputs, off): ValueSlice,
|
740
|
-
) -> InstOutput {
|
741
|
-
let caller_conv = self.lower_ctx.abi().call_conv(self.lower_ctx.sigs());
|
742
|
-
let sig = &self.lower_ctx.dfg().signatures[sig_ref];
|
743
|
-
let num_rets = sig.returns.len();
|
744
|
-
let abi = self.lower_ctx.sigs().abi_sig_for_sig_ref(sig_ref);
|
745
|
-
let caller = <$abicaller>::from_func(
|
746
|
-
self.lower_ctx.sigs(),
|
747
|
-
sig_ref,
|
748
|
-
&extname,
|
749
|
-
dist,
|
750
|
-
caller_conv,
|
751
|
-
self.backend.flags().clone(),
|
752
|
-
);
|
753
|
-
|
754
|
-
assert_eq!(
|
755
|
-
inputs.len(&self.lower_ctx.dfg().value_lists) - off,
|
756
|
-
sig.params.len()
|
757
|
-
);
|
758
|
-
|
759
|
-
self.gen_call_common(abi, num_rets, caller, args)
|
760
|
-
}
|
761
|
-
|
762
|
-
fn gen_call_indirect(
|
763
|
-
&mut self,
|
764
|
-
sig_ref: SigRef,
|
765
|
-
val: Value,
|
766
|
-
args @ (inputs, off): ValueSlice,
|
767
|
-
) -> InstOutput {
|
768
|
-
let caller_conv = self.lower_ctx.abi().call_conv(self.lower_ctx.sigs());
|
769
|
-
let ptr = self.put_in_reg(val);
|
770
|
-
let sig = &self.lower_ctx.dfg().signatures[sig_ref];
|
771
|
-
let num_rets = sig.returns.len();
|
772
|
-
let abi = self.lower_ctx.sigs().abi_sig_for_sig_ref(sig_ref);
|
773
|
-
let caller = <$abicaller>::from_ptr(
|
774
|
-
self.lower_ctx.sigs(),
|
775
|
-
sig_ref,
|
776
|
-
ptr,
|
777
|
-
Opcode::CallIndirect,
|
778
|
-
caller_conv,
|
779
|
-
self.backend.flags().clone(),
|
780
|
-
);
|
781
|
-
|
782
|
-
assert_eq!(
|
783
|
-
inputs.len(&self.lower_ctx.dfg().value_lists) - off,
|
784
|
-
sig.params.len()
|
785
|
-
);
|
786
|
-
|
787
|
-
self.gen_call_common(abi, num_rets, caller, args)
|
788
|
-
}
|
789
|
-
};
|
790
|
-
}
|
791
|
-
|
792
|
-
/// Helpers for the above ISLE prelude implementations. Meant to go
|
793
|
-
/// inside the `impl` for the context type, not the trait impl.
|
794
|
-
#[macro_export]
|
795
|
-
#[doc(hidden)]
|
796
|
-
macro_rules! isle_prelude_method_helpers {
|
797
|
-
($abicaller:ty) => {
|
798
|
-
fn gen_call_common_args(&mut self, call_site: &mut $abicaller, (inputs, off): ValueSlice) {
|
799
|
-
let num_args = call_site.num_args(self.lower_ctx.sigs());
|
800
|
-
|
801
|
-
assert_eq!(
|
802
|
-
inputs.len(&self.lower_ctx.dfg().value_lists) - off,
|
803
|
-
num_args
|
804
|
-
);
|
805
|
-
let mut arg_regs = vec![];
|
806
|
-
for i in 0..num_args {
|
807
|
-
let input = inputs
|
808
|
-
.get(off + i, &self.lower_ctx.dfg().value_lists)
|
809
|
-
.unwrap();
|
810
|
-
arg_regs.push(self.put_in_regs(input));
|
811
|
-
}
|
812
|
-
for (i, arg_regs) in arg_regs.iter().enumerate() {
|
813
|
-
call_site.emit_copy_regs_to_buffer(self.lower_ctx, i, *arg_regs);
|
814
|
-
}
|
815
|
-
for (i, arg_regs) in arg_regs.iter().enumerate() {
|
816
|
-
for inst in call_site.gen_arg(self.lower_ctx, i, *arg_regs) {
|
817
|
-
self.lower_ctx.emit(inst);
|
818
|
-
}
|
819
|
-
}
|
820
|
-
}
|
821
|
-
|
822
|
-
fn gen_call_common(
|
823
|
-
&mut self,
|
824
|
-
abi: Sig,
|
825
|
-
num_rets: usize,
|
826
|
-
mut caller: $abicaller,
|
827
|
-
args: ValueSlice,
|
828
|
-
) -> InstOutput {
|
829
|
-
caller.emit_stack_pre_adjust(self.lower_ctx);
|
830
|
-
|
831
|
-
self.gen_call_common_args(&mut caller, args);
|
832
|
-
|
833
|
-
// Handle retvals prior to emitting call, so the
|
834
|
-
// constraints are on the call instruction; but buffer the
|
835
|
-
// instructions till after the call.
|
836
|
-
let mut outputs = InstOutput::new();
|
837
|
-
let mut retval_insts: crate::machinst::abi::SmallInstVec<_> = smallvec::smallvec![];
|
838
|
-
// We take the *last* `num_rets` returns of the sig:
|
839
|
-
// this skips a StructReturn, if any, that is present.
|
840
|
-
let sigdata_num_rets = self.lower_ctx.sigs().num_rets(abi);
|
841
|
-
debug_assert!(num_rets <= sigdata_num_rets);
|
842
|
-
for i in (sigdata_num_rets - num_rets)..sigdata_num_rets {
|
843
|
-
// Borrow `sigdata` again so we don't hold a `self`
|
844
|
-
// borrow across the `&mut self` arg to
|
845
|
-
// `abi_arg_slot_regs()` below.
|
846
|
-
let ret = self.lower_ctx.sigs().get_ret(abi, i);
|
847
|
-
let retval_regs = self.abi_arg_slot_regs(&ret).unwrap();
|
848
|
-
retval_insts.extend(
|
849
|
-
caller
|
850
|
-
.gen_retval(self.lower_ctx, i, retval_regs.clone())
|
851
|
-
.into_iter(),
|
852
|
-
);
|
853
|
-
outputs.push(valueregs::non_writable_value_regs(retval_regs));
|
854
|
-
}
|
855
|
-
|
856
|
-
caller.emit_call(self.lower_ctx);
|
857
|
-
|
858
|
-
for inst in retval_insts {
|
859
|
-
self.lower_ctx.emit(inst);
|
860
|
-
}
|
861
|
-
|
862
|
-
caller.emit_stack_post_adjust(self.lower_ctx);
|
863
|
-
|
864
|
-
outputs
|
865
|
-
}
|
866
|
-
|
867
|
-
fn abi_arg_slot_regs(&mut self, arg: &ABIArg) -> Option<WritableValueRegs> {
|
868
|
-
match arg {
|
869
|
-
&ABIArg::Slots { ref slots, .. } => match slots.len() {
|
870
|
-
1 => {
|
871
|
-
let a = self.temp_writable_reg(slots[0].get_type());
|
872
|
-
Some(WritableValueRegs::one(a))
|
873
|
-
}
|
874
|
-
2 => {
|
875
|
-
let a = self.temp_writable_reg(slots[0].get_type());
|
876
|
-
let b = self.temp_writable_reg(slots[1].get_type());
|
877
|
-
Some(WritableValueRegs::two(a, b))
|
878
|
-
}
|
879
|
-
_ => panic!("Expected to see one or two slots only from {:?}", arg),
|
880
|
-
},
|
881
|
-
_ => None,
|
882
|
-
}
|
883
|
-
}
|
884
|
-
};
|
885
|
-
}
|
886
|
-
|
887
|
-
/// This structure is used to implement the ISLE-generated `Context` trait and
|
888
|
-
/// internally has a temporary reference to a machinst `LowerCtx`.
|
889
|
-
pub(crate) struct IsleContext<'a, 'b, I, B>
|
890
|
-
where
|
891
|
-
I: VCodeInst,
|
892
|
-
B: LowerBackend,
|
893
|
-
{
|
894
|
-
pub lower_ctx: &'a mut Lower<'b, I>,
|
895
|
-
pub backend: &'a B,
|
896
|
-
}
|