wasmtime 16.0.0 → 17.0.0
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- checksums.yaml +4 -4
- data/Cargo.lock +103 -79
- data/ext/Cargo.toml +7 -6
- data/ext/cargo-vendor/cranelift-bforest-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.104.0/Cargo.toml +40 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/Cargo.toml +175 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/isa/aarch64/lower/isle.rs +882 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/isa/x64/abi.rs +1305 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/isle_prelude.rs +957 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/machinst/isle.rs +908 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/machinst/mod.rs +558 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/machinst/pcc.rs +159 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/bitops.isle +188 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/cprop.isle +248 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/icmp.isle +197 -0
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- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/spaceship.isle +194 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts.rs +265 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/prelude.isle +641 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/prelude_lower.isle +1073 -0
- data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/prelude_opt.isle +134 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.104.0/Cargo.toml +35 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.104.0/Cargo.toml +22 -0
- data/ext/cargo-vendor/cranelift-control-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.104.0/Cargo.toml +30 -0
- data/ext/cargo-vendor/cranelift-entity-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.104.0/Cargo.toml +50 -0
- data/ext/cargo-vendor/cranelift-entity-0.104.0/src/primary.rs +541 -0
- data/ext/cargo-vendor/cranelift-frontend-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.104.0/Cargo.toml +68 -0
- data/ext/cargo-vendor/cranelift-isle-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.104.0/Cargo.toml +46 -0
- data/ext/cargo-vendor/cranelift-native-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-native-0.104.0/Cargo.toml +43 -0
- data/ext/cargo-vendor/cranelift-wasm-0.104.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-wasm-0.104.0/Cargo.toml +106 -0
- data/ext/cargo-vendor/cranelift-wasm-0.104.0/src/code_translator.rs +3646 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/Cargo.toml +49 -0
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- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/src/clocks.rs +56 -0
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- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/src/noop_scheduler.rs +25 -0
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- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/tests/random.rs +17 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/tests/scheduler.rs +24 -0
- data/ext/cargo-vendor/rand_pcg-0.3.1/.cargo-checksum.json +1 -0
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- data/ext/cargo-vendor/wasi-common-17.0.0/Cargo.toml +131 -0
- data/ext/cargo-vendor/wasi-common-17.0.0/src/error.rs +26 -0
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- data/ext/cargo-vendor/wasmtime-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/Cargo.toml +211 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/component.rs +545 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/instance.rs +815 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/linker.rs +580 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/matching.rs +215 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/mod.rs +351 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/resource_table.rs +350 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/component/resources.rs +823 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/config.rs +2428 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/func/typed.rs +638 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/lib.rs +526 -0
- data/ext/cargo-vendor/wasmtime-17.0.0/src/store.rs +2389 -0
- data/ext/cargo-vendor/wasmtime-asm-macros-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-asm-macros-17.0.0/Cargo.toml +22 -0
- data/ext/cargo-vendor/wasmtime-cache-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-cache-17.0.0/Cargo.toml +81 -0
- data/ext/cargo-vendor/wasmtime-component-macro-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-component-macro-17.0.0/Cargo.toml +67 -0
- data/ext/cargo-vendor/wasmtime-component-macro-17.0.0/src/bindgen.rs +371 -0
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- data/ext/cargo-vendor/wasmtime-component-util-17.0.0/Cargo.toml +25 -0
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- data/ext/cargo-vendor/wasmtime-cranelift-shared-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-cranelift-shared-17.0.0/Cargo.toml +71 -0
- data/ext/cargo-vendor/wasmtime-environ-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-environ-17.0.0/Cargo.lock +726 -0
- data/ext/cargo-vendor/wasmtime-environ-17.0.0/Cargo.toml +125 -0
- data/ext/cargo-vendor/wasmtime-environ-17.0.0/examples/factc.rs +205 -0
- data/ext/cargo-vendor/wasmtime-fiber-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-fiber-17.0.0/Cargo.toml +63 -0
- data/ext/cargo-vendor/wasmtime-jit-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-jit-17.0.0/Cargo.toml +125 -0
- data/ext/cargo-vendor/wasmtime-jit-debug-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-jit-debug-17.0.0/Cargo.toml +67 -0
- data/ext/cargo-vendor/wasmtime-jit-icache-coherence-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-jit-icache-coherence-17.0.0/Cargo.toml +46 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/Cargo.toml +139 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/instance/allocator/pooling/memory_pool.rs +997 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/instance/allocator/pooling.rs +658 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/memory.rs +973 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/parking_spot.rs +622 -0
- data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/sys/windows/mmap.rs +216 -0
- data/ext/cargo-vendor/wasmtime-types-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-types-17.0.0/Cargo.toml +36 -0
- data/ext/cargo-vendor/wasmtime-versioned-export-macros-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-versioned-export-macros-17.0.0/Cargo.toml +32 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/Cargo.toml +261 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/ctx.rs +333 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/filesystem.rs +325 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/clocks.rs +103 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/filesystem.rs +1069 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/instance_network.rs +15 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/network.rs +625 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/tcp.rs +605 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/udp.rs +530 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/mod.rs +327 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/network.rs +108 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/poll.rs +175 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/preview1.rs +2362 -0
- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/stream.rs +181 -0
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- data/ext/cargo-vendor/wasmtime-wasi-17.0.0/tests/all/async_.rs +364 -0
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- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/cli/environment.wit +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/cli/exit.wit +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/cli/run.wit +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/http/handler.wit +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/sockets/instance-network.wit +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/witx/preview0/typenames.witx +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/witx/preview0/wasi_unstable.witx +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/witx/preview1/typenames.witx +0 -0
- /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/witx/preview1/wasi_snapshot_preview1.witx +0 -0
- /data/ext/cargo-vendor/{wasmtime-winch-16.0.0 → wasmtime-winch-17.0.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{wasmtime-winch-16.0.0 → wasmtime-winch-17.0.0}/src/builder.rs +0 -0
- /data/ext/cargo-vendor/{wasmtime-winch-16.0.0 → wasmtime-winch-17.0.0}/src/compiler.rs +0 -0
- /data/ext/cargo-vendor/{wasmtime-winch-16.0.0 → wasmtime-winch-17.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{wasmtime-wit-bindgen-16.0.0 → wasmtime-wit-bindgen-17.0.0}/src/rust.rs +0 -0
- /data/ext/cargo-vendor/{wasmtime-wit-bindgen-16.0.0 → wasmtime-wit-bindgen-17.0.0}/src/source.rs +0 -0
- /data/ext/cargo-vendor/{wasmtime-wit-bindgen-16.0.0 → wasmtime-wit-bindgen-17.0.0}/src/types.rs +0 -0
- /data/ext/cargo-vendor/{wasmtime-wmemcheck-16.0.0 → wasmtime-wmemcheck-17.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/README.md +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/borrow.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/error.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/guest_type.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/region.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/wasmtime.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/README.md +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/codegen_settings.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/config.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/funcs.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/lifetimes.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/module_trait.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/names.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/error.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/flags.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/handle.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/mod.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/record.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/variant.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/wasmtime.rs +0 -0
- /data/ext/cargo-vendor/{wiggle-macro-16.0.0 → wiggle-macro-17.0.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{wiggle-macro-16.0.0 → wiggle-macro-17.0.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/LICENSE +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/build.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/abi/local.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/abi/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/codegen/builtin.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/codegen/call.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/codegen/control.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/codegen/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/frame/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/abi.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/address.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/asm.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/regs.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/reg.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/x64/abi.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/x64/address.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/x64/mod.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/x64/regs.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/lib.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/regalloc.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/regset.rs +0 -0
- /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/trampoline.rs +0 -0
@@ -0,0 +1,1617 @@
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//! This module is the central place for machine code emission.
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//! It defines an implementation of wasmparser's Visitor trait
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//! for `CodeGen`; which defines a visitor per op-code,
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//! which validates and dispatches to the corresponding
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//! machine code emitter.
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use crate::abi::ABI;
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use crate::codegen::{control_index, Callee, CodeGen, ControlStackFrame, FnCall};
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use crate::masm::{
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DivKind, ExtendKind, FloatCmpKind, IntCmpKind, MacroAssembler, OperandSize, RegImm, RemKind,
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RoundingMode, ShiftKind,
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};
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use crate::stack::{TypedReg, Val};
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use cranelift_codegen::ir::TrapCode;
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use smallvec::SmallVec;
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use wasmparser::BrTable;
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use wasmparser::{BlockType, Ieee32, Ieee64, VisitOperator};
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use wasmtime_environ::{
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FuncIndex, GlobalIndex, MemoryIndex, TableIndex, TableStyle, TypeIndex, WasmHeapType, WasmType,
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FUNCREF_INIT_BIT,
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};
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/// A macro to define unsupported WebAssembly operators.
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///
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macro_rules! def_unsupported {
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($( @$proposal:ident $op:ident $({ $($arg:ident: $argty:ty),* })? => $visit:ident)*) => {
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$(
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def_unsupported!(
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emit
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$op
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fn $visit(&mut self $($(,$arg: $argty)*)?) -> Self::Output {
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$($(let _ = $arg;)*)?
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todo!(stringify!($op))
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}
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);
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)*
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};
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(emit I32Const $($rest:tt)*) => {};
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(emit I64Add $($rest:tt)*) => {};
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(emit I32Sub $($rest:tt)*) => {};
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(emit I32Mul $($rest:tt)*) => {};
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(emit I32DivU $($rest:tt)*) => {};
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(emit I64DivS $($rest:tt)*) => {};
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(emit I64RemU $($rest:tt)*) => {};
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(emit I32LtU $($rest:tt)*) => {};
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(emit I64LtU $($rest:tt)*) => {};
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(emit I32GeU $($rest:tt)*) => {};
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(emit I64GeU $($rest:tt)*) => {};
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(emit I32Eqz $($rest:tt)*) => {};
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(emit I64Eqz $($rest:tt)*) => {};
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(emit I32And $($rest:tt)*) => {};
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(emit I32ShrU $($rest:tt)*) => {};
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(emit I64ShrU $($rest:tt)*) => {};
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(emit I32Rotl $($rest:tt)*) => {};
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(emit I64Rotl $($rest:tt)*) => {};
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(emit I32Rotr $($rest:tt)*) => {};
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(emit I64Rotr $($rest:tt)*) => {};
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(emit I32Clz $($rest:tt)*) => {};
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(emit I64Clz $($rest:tt)*) => {};
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(emit I32Ctz $($rest:tt)*) => {};
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(emit I64Ctz $($rest:tt)*) => {};
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(emit I32Popcnt $($rest:tt)*) => {};
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(emit I64Popcnt $($rest:tt)*) => {};
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(emit I32WrapI64 $($rest:tt)*) => {};
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(emit I64ExtendI32S $($rest:tt)*) => {};
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(emit I64ExtendI32U $($rest:tt)*) => {};
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(emit I32Extend8S $($rest:tt)*) => {};
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(emit I32Extend16S $($rest:tt)*) => {};
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(emit I64Extend8S $($rest:tt)*) => {};
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(emit I64Extend16S $($rest:tt)*) => {};
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(emit I64Extend32S $($rest:tt)*) => {};
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(emit LocalGet $($rest:tt)*) => {};
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(emit LocalSet $($rest:tt)*) => {};
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(emit Call $($rest:tt)*) => {};
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(emit End $($rest:tt)*) => {};
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(emit Nop $($rest:tt)*) => {};
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(emit If $($rest:tt)*) => {};
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(emit Else $($rest:tt)*) => {};
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(emit Block $($rest:tt)*) => {};
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(emit Loop $($rest:tt)*) => {};
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(emit Br $($rest:tt)*) => {};
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(emit BrIf $($rest:tt)*) => {};
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(emit Return $($rest:tt)*) => {};
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(emit Unreachable $($rest:tt)*) => {};
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(emit LocalTee $($rest:tt)*) => {};
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(emit GlobalGet $($rest:tt)*) => {};
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(emit GlobalSet $($rest:tt)*) => {};
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(emit Select $($rest:tt)*) => {};
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(emit Drop $($rest:tt)*) => {};
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(emit BrTable $($rest:tt)*) => {};
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(emit CallIndirect $($rest:tt)*) => {};
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(emit TableInit $($rest:tt)*) => {};
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(emit TableCopy $($rest:tt)*) => {};
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(emit TableGet $($rest:tt)*) => {};
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+
(emit TableSize $($rest:tt)*) => {};
|
180
|
+
(emit TableFill $($rest:tt)*) => {};
|
181
|
+
(emit ElemDrop $($rest:tt)*) => {};
|
182
|
+
(emit MemoryInit $($rest:tt)*) => {};
|
183
|
+
(emit MemoryCopy $($rest:tt)*) => {};
|
184
|
+
(emit DataDrop $($rest:tt)*) => {};
|
185
|
+
(emit MemoryFill $($rest:tt)*) => {};
|
186
|
+
(emit MemorySize $($rest:tt)*) => {};
|
187
|
+
(emit MemoryGrow $($rest:tt)*) => {};
|
188
|
+
|
189
|
+
(emit $unsupported:tt $($rest:tt)*) => {$($rest)*};
|
190
|
+
}
|
191
|
+
|
192
|
+
impl<'a, 'translation, 'data, M> VisitOperator<'a> for CodeGen<'a, 'translation, 'data, M>
|
193
|
+
where
|
194
|
+
M: MacroAssembler,
|
195
|
+
{
|
196
|
+
type Output = ();
|
197
|
+
|
198
|
+
fn visit_i32_const(&mut self, val: i32) {
|
199
|
+
self.context.stack.push(Val::i32(val));
|
200
|
+
}
|
201
|
+
|
202
|
+
fn visit_i64_const(&mut self, val: i64) {
|
203
|
+
self.context.stack.push(Val::i64(val));
|
204
|
+
}
|
205
|
+
|
206
|
+
fn visit_f32_const(&mut self, val: Ieee32) {
|
207
|
+
self.context.stack.push(Val::f32(val));
|
208
|
+
}
|
209
|
+
|
210
|
+
fn visit_f64_const(&mut self, val: Ieee64) {
|
211
|
+
self.context.stack.push(Val::f64(val));
|
212
|
+
}
|
213
|
+
|
214
|
+
fn visit_f32_add(&mut self) {
|
215
|
+
self.context.binop(
|
216
|
+
self.masm,
|
217
|
+
OperandSize::S32,
|
218
|
+
&mut |masm: &mut M, dst, src, size| {
|
219
|
+
masm.float_add(dst, dst, src, size);
|
220
|
+
TypedReg::f32(dst)
|
221
|
+
},
|
222
|
+
);
|
223
|
+
}
|
224
|
+
|
225
|
+
fn visit_f64_add(&mut self) {
|
226
|
+
self.context.binop(
|
227
|
+
self.masm,
|
228
|
+
OperandSize::S64,
|
229
|
+
&mut |masm: &mut M, dst, src, size| {
|
230
|
+
masm.float_add(dst, dst, src, size);
|
231
|
+
TypedReg::f64(dst)
|
232
|
+
},
|
233
|
+
);
|
234
|
+
}
|
235
|
+
|
236
|
+
fn visit_f32_sub(&mut self) {
|
237
|
+
self.context.binop(
|
238
|
+
self.masm,
|
239
|
+
OperandSize::S32,
|
240
|
+
&mut |masm: &mut M, dst, src, size| {
|
241
|
+
masm.float_sub(dst, dst, src, size);
|
242
|
+
TypedReg::f32(dst)
|
243
|
+
},
|
244
|
+
);
|
245
|
+
}
|
246
|
+
|
247
|
+
fn visit_f64_sub(&mut self) {
|
248
|
+
self.context.binop(
|
249
|
+
self.masm,
|
250
|
+
OperandSize::S64,
|
251
|
+
&mut |masm: &mut M, dst, src, size| {
|
252
|
+
masm.float_sub(dst, dst, src, size);
|
253
|
+
TypedReg::f64(dst)
|
254
|
+
},
|
255
|
+
);
|
256
|
+
}
|
257
|
+
|
258
|
+
fn visit_f32_mul(&mut self) {
|
259
|
+
self.context.binop(
|
260
|
+
self.masm,
|
261
|
+
OperandSize::S32,
|
262
|
+
&mut |masm: &mut M, dst, src, size| {
|
263
|
+
masm.float_mul(dst, dst, src, size);
|
264
|
+
TypedReg::f32(dst)
|
265
|
+
},
|
266
|
+
);
|
267
|
+
}
|
268
|
+
|
269
|
+
fn visit_f64_mul(&mut self) {
|
270
|
+
self.context.binop(
|
271
|
+
self.masm,
|
272
|
+
OperandSize::S64,
|
273
|
+
&mut |masm: &mut M, dst, src, size| {
|
274
|
+
masm.float_mul(dst, dst, src, size);
|
275
|
+
TypedReg::f64(dst)
|
276
|
+
},
|
277
|
+
);
|
278
|
+
}
|
279
|
+
|
280
|
+
fn visit_f32_div(&mut self) {
|
281
|
+
self.context.binop(
|
282
|
+
self.masm,
|
283
|
+
OperandSize::S32,
|
284
|
+
&mut |masm: &mut M, dst, src, size| {
|
285
|
+
masm.float_div(dst, dst, src, size);
|
286
|
+
TypedReg::f32(dst)
|
287
|
+
},
|
288
|
+
);
|
289
|
+
}
|
290
|
+
|
291
|
+
fn visit_f64_div(&mut self) {
|
292
|
+
self.context.binop(
|
293
|
+
self.masm,
|
294
|
+
OperandSize::S64,
|
295
|
+
&mut |masm: &mut M, dst, src, size| {
|
296
|
+
masm.float_div(dst, dst, src, size);
|
297
|
+
TypedReg::f64(dst)
|
298
|
+
},
|
299
|
+
);
|
300
|
+
}
|
301
|
+
|
302
|
+
fn visit_f32_min(&mut self) {
|
303
|
+
self.context.binop(
|
304
|
+
self.masm,
|
305
|
+
OperandSize::S32,
|
306
|
+
&mut |masm: &mut M, dst, src, size| {
|
307
|
+
masm.float_min(dst, dst, src, size);
|
308
|
+
TypedReg::f32(dst)
|
309
|
+
},
|
310
|
+
);
|
311
|
+
}
|
312
|
+
|
313
|
+
fn visit_f64_min(&mut self) {
|
314
|
+
self.context.binop(
|
315
|
+
self.masm,
|
316
|
+
OperandSize::S64,
|
317
|
+
&mut |masm: &mut M, dst, src, size| {
|
318
|
+
masm.float_min(dst, dst, src, size);
|
319
|
+
TypedReg::f64(dst)
|
320
|
+
},
|
321
|
+
);
|
322
|
+
}
|
323
|
+
|
324
|
+
fn visit_f32_max(&mut self) {
|
325
|
+
self.context.binop(
|
326
|
+
self.masm,
|
327
|
+
OperandSize::S32,
|
328
|
+
&mut |masm: &mut M, dst, src, size| {
|
329
|
+
masm.float_max(dst, dst, src, size);
|
330
|
+
TypedReg::f32(dst)
|
331
|
+
},
|
332
|
+
);
|
333
|
+
}
|
334
|
+
|
335
|
+
fn visit_f64_max(&mut self) {
|
336
|
+
self.context.binop(
|
337
|
+
self.masm,
|
338
|
+
OperandSize::S64,
|
339
|
+
&mut |masm: &mut M, dst, src, size| {
|
340
|
+
masm.float_max(dst, dst, src, size);
|
341
|
+
TypedReg::f64(dst)
|
342
|
+
},
|
343
|
+
);
|
344
|
+
}
|
345
|
+
|
346
|
+
fn visit_f32_copysign(&mut self) {
|
347
|
+
self.context.binop(
|
348
|
+
self.masm,
|
349
|
+
OperandSize::S32,
|
350
|
+
&mut |masm: &mut M, dst, src, size| {
|
351
|
+
masm.float_copysign(dst, dst, src, size);
|
352
|
+
TypedReg::f32(dst)
|
353
|
+
},
|
354
|
+
);
|
355
|
+
}
|
356
|
+
|
357
|
+
fn visit_f64_copysign(&mut self) {
|
358
|
+
self.context.binop(
|
359
|
+
self.masm,
|
360
|
+
OperandSize::S64,
|
361
|
+
&mut |masm: &mut M, dst, src, size| {
|
362
|
+
masm.float_copysign(dst, dst, src, size);
|
363
|
+
TypedReg::f64(dst)
|
364
|
+
},
|
365
|
+
);
|
366
|
+
}
|
367
|
+
|
368
|
+
fn visit_f32_abs(&mut self) {
|
369
|
+
self.context
|
370
|
+
.unop(self.masm, OperandSize::S32, &mut |masm, reg, size| {
|
371
|
+
masm.float_abs(reg, size);
|
372
|
+
TypedReg::f32(reg)
|
373
|
+
});
|
374
|
+
}
|
375
|
+
|
376
|
+
fn visit_f64_abs(&mut self) {
|
377
|
+
self.context
|
378
|
+
.unop(self.masm, OperandSize::S64, &mut |masm, reg, size| {
|
379
|
+
masm.float_abs(reg, size);
|
380
|
+
TypedReg::f64(reg)
|
381
|
+
});
|
382
|
+
}
|
383
|
+
|
384
|
+
fn visit_f32_neg(&mut self) {
|
385
|
+
self.context
|
386
|
+
.unop(self.masm, OperandSize::S32, &mut |masm, reg, size| {
|
387
|
+
masm.float_neg(reg, size);
|
388
|
+
TypedReg::f32(reg)
|
389
|
+
});
|
390
|
+
}
|
391
|
+
|
392
|
+
fn visit_f64_neg(&mut self) {
|
393
|
+
self.context
|
394
|
+
.unop(self.masm, OperandSize::S64, &mut |masm, reg, size| {
|
395
|
+
masm.float_neg(reg, size);
|
396
|
+
TypedReg::f64(reg)
|
397
|
+
});
|
398
|
+
}
|
399
|
+
|
400
|
+
fn visit_f32_floor(&mut self) {
|
401
|
+
self.masm
|
402
|
+
.float_round(RoundingMode::Down, &mut self.context, OperandSize::S32);
|
403
|
+
}
|
404
|
+
|
405
|
+
fn visit_f64_floor(&mut self) {
|
406
|
+
self.masm
|
407
|
+
.float_round(RoundingMode::Down, &mut self.context, OperandSize::S64);
|
408
|
+
}
|
409
|
+
|
410
|
+
fn visit_f32_ceil(&mut self) {
|
411
|
+
self.masm
|
412
|
+
.float_round(RoundingMode::Up, &mut self.context, OperandSize::S32);
|
413
|
+
}
|
414
|
+
|
415
|
+
fn visit_f64_ceil(&mut self) {
|
416
|
+
self.masm
|
417
|
+
.float_round(RoundingMode::Up, &mut self.context, OperandSize::S64);
|
418
|
+
}
|
419
|
+
|
420
|
+
fn visit_f32_nearest(&mut self) {
|
421
|
+
self.masm
|
422
|
+
.float_round(RoundingMode::Nearest, &mut self.context, OperandSize::S32);
|
423
|
+
}
|
424
|
+
|
425
|
+
fn visit_f64_nearest(&mut self) {
|
426
|
+
self.masm
|
427
|
+
.float_round(RoundingMode::Nearest, &mut self.context, OperandSize::S64);
|
428
|
+
}
|
429
|
+
|
430
|
+
fn visit_f32_trunc(&mut self) {
|
431
|
+
self.masm
|
432
|
+
.float_round(RoundingMode::Zero, &mut self.context, OperandSize::S32);
|
433
|
+
}
|
434
|
+
|
435
|
+
fn visit_f64_trunc(&mut self) {
|
436
|
+
self.masm
|
437
|
+
.float_round(RoundingMode::Zero, &mut self.context, OperandSize::S64);
|
438
|
+
}
|
439
|
+
|
440
|
+
fn visit_f32_sqrt(&mut self) {
|
441
|
+
self.context
|
442
|
+
.unop(self.masm, OperandSize::S32, &mut |masm, reg, size| {
|
443
|
+
masm.float_sqrt(reg, reg, size);
|
444
|
+
TypedReg::f32(reg)
|
445
|
+
});
|
446
|
+
}
|
447
|
+
|
448
|
+
fn visit_f64_sqrt(&mut self) {
|
449
|
+
self.context
|
450
|
+
.unop(self.masm, OperandSize::S64, &mut |masm, reg, size| {
|
451
|
+
masm.float_sqrt(reg, reg, size);
|
452
|
+
TypedReg::f64(reg)
|
453
|
+
});
|
454
|
+
}
|
455
|
+
|
456
|
+
fn visit_f32_eq(&mut self) {
|
457
|
+
self.context.float_cmp_op(
|
458
|
+
self.masm,
|
459
|
+
OperandSize::S32,
|
460
|
+
&mut |masm: &mut M, dst, src1, src2, size| {
|
461
|
+
masm.float_cmp_with_set(src1, src2, dst, FloatCmpKind::Eq, size);
|
462
|
+
},
|
463
|
+
);
|
464
|
+
}
|
465
|
+
|
466
|
+
fn visit_f64_eq(&mut self) {
|
467
|
+
self.context.float_cmp_op(
|
468
|
+
self.masm,
|
469
|
+
OperandSize::S64,
|
470
|
+
&mut |masm: &mut M, dst, src1, src2, size| {
|
471
|
+
masm.float_cmp_with_set(src1, src2, dst, FloatCmpKind::Eq, size);
|
472
|
+
},
|
473
|
+
);
|
474
|
+
}
|
475
|
+
|
476
|
+
fn visit_f32_ne(&mut self) {
|
477
|
+
self.context.float_cmp_op(
|
478
|
+
self.masm,
|
479
|
+
OperandSize::S32,
|
480
|
+
&mut |masm: &mut M, dst, src1, src2, size| {
|
481
|
+
masm.float_cmp_with_set(src1, src2, dst, FloatCmpKind::Ne, size);
|
482
|
+
},
|
483
|
+
);
|
484
|
+
}
|
485
|
+
|
486
|
+
fn visit_f64_ne(&mut self) {
|
487
|
+
self.context.float_cmp_op(
|
488
|
+
self.masm,
|
489
|
+
OperandSize::S64,
|
490
|
+
&mut |masm: &mut M, dst, src1, src2, size| {
|
491
|
+
masm.float_cmp_with_set(src1, src2, dst, FloatCmpKind::Ne, size);
|
492
|
+
},
|
493
|
+
);
|
494
|
+
}
|
495
|
+
|
496
|
+
fn visit_f32_lt(&mut self) {
|
497
|
+
self.context.float_cmp_op(
|
498
|
+
self.masm,
|
499
|
+
OperandSize::S32,
|
500
|
+
&mut |masm: &mut M, dst, src1, src2, size| {
|
501
|
+
masm.float_cmp_with_set(src1, src2, dst, FloatCmpKind::Lt, size);
|
502
|
+
},
|
503
|
+
);
|
504
|
+
}
|
505
|
+
|
506
|
+
fn visit_f64_lt(&mut self) {
|
507
|
+
self.context.float_cmp_op(
|
508
|
+
self.masm,
|
509
|
+
OperandSize::S64,
|
510
|
+
&mut |masm: &mut M, dst, src1, src2, size| {
|
511
|
+
masm.float_cmp_with_set(src1, src2, dst, FloatCmpKind::Lt, size);
|
512
|
+
},
|
513
|
+
);
|
514
|
+
}
|
515
|
+
|
516
|
+
fn visit_f32_gt(&mut self) {
|
517
|
+
self.context.float_cmp_op(
|
518
|
+
self.masm,
|
519
|
+
OperandSize::S32,
|
520
|
+
&mut |masm: &mut M, dst, src1, src2, size| {
|
521
|
+
masm.float_cmp_with_set(src1, src2, dst, FloatCmpKind::Gt, size);
|
522
|
+
},
|
523
|
+
);
|
524
|
+
}
|
525
|
+
|
526
|
+
fn visit_f64_gt(&mut self) {
|
527
|
+
self.context.float_cmp_op(
|
528
|
+
self.masm,
|
529
|
+
OperandSize::S64,
|
530
|
+
&mut |masm: &mut M, dst, src1, src2, size| {
|
531
|
+
masm.float_cmp_with_set(src1, src2, dst, FloatCmpKind::Gt, size);
|
532
|
+
},
|
533
|
+
);
|
534
|
+
}
|
535
|
+
|
536
|
+
fn visit_f32_le(&mut self) {
|
537
|
+
self.context.float_cmp_op(
|
538
|
+
self.masm,
|
539
|
+
OperandSize::S32,
|
540
|
+
&mut |masm: &mut M, dst, src1, src2, size| {
|
541
|
+
masm.float_cmp_with_set(src1, src2, dst, FloatCmpKind::Le, size);
|
542
|
+
},
|
543
|
+
);
|
544
|
+
}
|
545
|
+
|
546
|
+
fn visit_f64_le(&mut self) {
|
547
|
+
self.context.float_cmp_op(
|
548
|
+
self.masm,
|
549
|
+
OperandSize::S64,
|
550
|
+
&mut |masm: &mut M, dst, src1, src2, size| {
|
551
|
+
masm.float_cmp_with_set(src1, src2, dst, FloatCmpKind::Le, size);
|
552
|
+
},
|
553
|
+
);
|
554
|
+
}
|
555
|
+
|
556
|
+
fn visit_f32_ge(&mut self) {
|
557
|
+
self.context.float_cmp_op(
|
558
|
+
self.masm,
|
559
|
+
OperandSize::S32,
|
560
|
+
&mut |masm: &mut M, dst, src1, src2, size| {
|
561
|
+
masm.float_cmp_with_set(src1, src2, dst, FloatCmpKind::Ge, size);
|
562
|
+
},
|
563
|
+
);
|
564
|
+
}
|
565
|
+
|
566
|
+
fn visit_f64_ge(&mut self) {
|
567
|
+
self.context.float_cmp_op(
|
568
|
+
self.masm,
|
569
|
+
OperandSize::S64,
|
570
|
+
&mut |masm: &mut M, dst, src1, src2, size| {
|
571
|
+
masm.float_cmp_with_set(src1, src2, dst, FloatCmpKind::Ge, size);
|
572
|
+
},
|
573
|
+
);
|
574
|
+
}
|
575
|
+
|
576
|
+
fn visit_i32_add(&mut self) {
|
577
|
+
self.context.i32_binop(self.masm, |masm, dst, src, size| {
|
578
|
+
masm.add(dst, dst, src, size);
|
579
|
+
TypedReg::i32(dst)
|
580
|
+
});
|
581
|
+
}
|
582
|
+
|
583
|
+
fn visit_i64_add(&mut self) {
|
584
|
+
self.context.i64_binop(self.masm, |masm, dst, src, size| {
|
585
|
+
masm.add(dst, dst, src, size);
|
586
|
+
TypedReg::i64(dst)
|
587
|
+
});
|
588
|
+
}
|
589
|
+
|
590
|
+
fn visit_i32_sub(&mut self) {
|
591
|
+
self.context.i32_binop(self.masm, |masm, dst, src, size| {
|
592
|
+
masm.sub(dst, dst, src, size);
|
593
|
+
TypedReg::i32(dst)
|
594
|
+
});
|
595
|
+
}
|
596
|
+
|
597
|
+
fn visit_i64_sub(&mut self) {
|
598
|
+
self.context.i64_binop(self.masm, |masm, dst, src, size| {
|
599
|
+
masm.sub(dst, dst, src, size);
|
600
|
+
TypedReg::i64(dst)
|
601
|
+
});
|
602
|
+
}
|
603
|
+
|
604
|
+
fn visit_i32_mul(&mut self) {
|
605
|
+
self.context.i32_binop(self.masm, |masm, dst, src, size| {
|
606
|
+
masm.mul(dst, dst, src, size);
|
607
|
+
TypedReg::i32(dst)
|
608
|
+
});
|
609
|
+
}
|
610
|
+
|
611
|
+
fn visit_i64_mul(&mut self) {
|
612
|
+
self.context.i64_binop(self.masm, |masm, dst, src, size| {
|
613
|
+
masm.mul(dst, dst, src, size);
|
614
|
+
TypedReg::i64(dst)
|
615
|
+
});
|
616
|
+
}
|
617
|
+
|
618
|
+
fn visit_i32_div_s(&mut self) {
|
619
|
+
use DivKind::*;
|
620
|
+
use OperandSize::*;
|
621
|
+
|
622
|
+
self.masm.div(&mut self.context, Signed, S32);
|
623
|
+
}
|
624
|
+
|
625
|
+
fn visit_i32_div_u(&mut self) {
|
626
|
+
use DivKind::*;
|
627
|
+
use OperandSize::*;
|
628
|
+
|
629
|
+
self.masm.div(&mut self.context, Unsigned, S32);
|
630
|
+
}
|
631
|
+
|
632
|
+
fn visit_i64_div_s(&mut self) {
|
633
|
+
use DivKind::*;
|
634
|
+
use OperandSize::*;
|
635
|
+
|
636
|
+
self.masm.div(&mut self.context, Signed, S64);
|
637
|
+
}
|
638
|
+
|
639
|
+
fn visit_i64_div_u(&mut self) {
|
640
|
+
use DivKind::*;
|
641
|
+
use OperandSize::*;
|
642
|
+
|
643
|
+
self.masm.div(&mut self.context, Unsigned, S64);
|
644
|
+
}
|
645
|
+
|
646
|
+
fn visit_i32_rem_s(&mut self) {
|
647
|
+
use OperandSize::*;
|
648
|
+
use RemKind::*;
|
649
|
+
|
650
|
+
self.masm.rem(&mut self.context, Signed, S32);
|
651
|
+
}
|
652
|
+
|
653
|
+
fn visit_i32_rem_u(&mut self) {
|
654
|
+
use OperandSize::*;
|
655
|
+
use RemKind::*;
|
656
|
+
|
657
|
+
self.masm.rem(&mut self.context, Unsigned, S32);
|
658
|
+
}
|
659
|
+
|
660
|
+
fn visit_i64_rem_s(&mut self) {
|
661
|
+
use OperandSize::*;
|
662
|
+
use RemKind::*;
|
663
|
+
|
664
|
+
self.masm.rem(&mut self.context, Signed, S64);
|
665
|
+
}
|
666
|
+
|
667
|
+
fn visit_i64_rem_u(&mut self) {
|
668
|
+
use OperandSize::*;
|
669
|
+
use RemKind::*;
|
670
|
+
|
671
|
+
self.masm.rem(&mut self.context, Unsigned, S64);
|
672
|
+
}
|
673
|
+
|
674
|
+
fn visit_i32_eq(&mut self) {
|
675
|
+
self.cmp_i32s(IntCmpKind::Eq);
|
676
|
+
}
|
677
|
+
|
678
|
+
fn visit_i64_eq(&mut self) {
|
679
|
+
self.cmp_i64s(IntCmpKind::Eq);
|
680
|
+
}
|
681
|
+
|
682
|
+
fn visit_i32_ne(&mut self) {
|
683
|
+
self.cmp_i32s(IntCmpKind::Ne);
|
684
|
+
}
|
685
|
+
|
686
|
+
fn visit_i64_ne(&mut self) {
|
687
|
+
self.cmp_i64s(IntCmpKind::Ne);
|
688
|
+
}
|
689
|
+
|
690
|
+
fn visit_i32_lt_s(&mut self) {
|
691
|
+
self.cmp_i32s(IntCmpKind::LtS);
|
692
|
+
}
|
693
|
+
|
694
|
+
fn visit_i64_lt_s(&mut self) {
|
695
|
+
self.cmp_i64s(IntCmpKind::LtS);
|
696
|
+
}
|
697
|
+
|
698
|
+
fn visit_i32_lt_u(&mut self) {
|
699
|
+
self.cmp_i32s(IntCmpKind::LtU);
|
700
|
+
}
|
701
|
+
|
702
|
+
fn visit_i64_lt_u(&mut self) {
|
703
|
+
self.cmp_i64s(IntCmpKind::LtU);
|
704
|
+
}
|
705
|
+
|
706
|
+
fn visit_i32_le_s(&mut self) {
|
707
|
+
self.cmp_i32s(IntCmpKind::LeS);
|
708
|
+
}
|
709
|
+
|
710
|
+
fn visit_i64_le_s(&mut self) {
|
711
|
+
self.cmp_i64s(IntCmpKind::LeS);
|
712
|
+
}
|
713
|
+
|
714
|
+
fn visit_i32_le_u(&mut self) {
|
715
|
+
self.cmp_i32s(IntCmpKind::LeU);
|
716
|
+
}
|
717
|
+
|
718
|
+
fn visit_i64_le_u(&mut self) {
|
719
|
+
self.cmp_i64s(IntCmpKind::LeU);
|
720
|
+
}
|
721
|
+
|
722
|
+
fn visit_i32_gt_s(&mut self) {
|
723
|
+
self.cmp_i32s(IntCmpKind::GtS);
|
724
|
+
}
|
725
|
+
|
726
|
+
fn visit_i64_gt_s(&mut self) {
|
727
|
+
self.cmp_i64s(IntCmpKind::GtS);
|
728
|
+
}
|
729
|
+
|
730
|
+
fn visit_i32_gt_u(&mut self) {
|
731
|
+
self.cmp_i32s(IntCmpKind::GtU);
|
732
|
+
}
|
733
|
+
|
734
|
+
fn visit_i64_gt_u(&mut self) {
|
735
|
+
self.cmp_i64s(IntCmpKind::GtU);
|
736
|
+
}
|
737
|
+
|
738
|
+
fn visit_i32_ge_s(&mut self) {
|
739
|
+
self.cmp_i32s(IntCmpKind::GeS);
|
740
|
+
}
|
741
|
+
|
742
|
+
fn visit_i64_ge_s(&mut self) {
|
743
|
+
self.cmp_i64s(IntCmpKind::GeS);
|
744
|
+
}
|
745
|
+
|
746
|
+
fn visit_i32_ge_u(&mut self) {
|
747
|
+
self.cmp_i32s(IntCmpKind::GeU);
|
748
|
+
}
|
749
|
+
|
750
|
+
fn visit_i64_ge_u(&mut self) {
|
751
|
+
self.cmp_i64s(IntCmpKind::GeU);
|
752
|
+
}
|
753
|
+
|
754
|
+
fn visit_i32_eqz(&mut self) {
|
755
|
+
use OperandSize::*;
|
756
|
+
|
757
|
+
self.context.unop(self.masm, S32, &mut |masm, reg, size| {
|
758
|
+
masm.cmp_with_set(RegImm::i32(0), reg.into(), IntCmpKind::Eq, size);
|
759
|
+
TypedReg::i32(reg)
|
760
|
+
});
|
761
|
+
}
|
762
|
+
|
763
|
+
fn visit_i64_eqz(&mut self) {
|
764
|
+
use OperandSize::*;
|
765
|
+
|
766
|
+
self.context.unop(self.masm, S64, &mut |masm, reg, size| {
|
767
|
+
masm.cmp_with_set(RegImm::i64(0), reg.into(), IntCmpKind::Eq, size);
|
768
|
+
TypedReg::i32(reg) // Return value for `i64.eqz` is an `i32`.
|
769
|
+
});
|
770
|
+
}
|
771
|
+
|
772
|
+
fn visit_i32_clz(&mut self) {
|
773
|
+
use OperandSize::*;
|
774
|
+
|
775
|
+
self.context.unop(self.masm, S32, &mut |masm, reg, size| {
|
776
|
+
masm.clz(reg, reg, size);
|
777
|
+
TypedReg::i32(reg)
|
778
|
+
});
|
779
|
+
}
|
780
|
+
|
781
|
+
fn visit_i64_clz(&mut self) {
|
782
|
+
use OperandSize::*;
|
783
|
+
|
784
|
+
self.context.unop(self.masm, S64, &mut |masm, reg, size| {
|
785
|
+
masm.clz(reg, reg, size);
|
786
|
+
TypedReg::i64(reg)
|
787
|
+
});
|
788
|
+
}
|
789
|
+
|
790
|
+
fn visit_i32_ctz(&mut self) {
|
791
|
+
use OperandSize::*;
|
792
|
+
|
793
|
+
self.context.unop(self.masm, S32, &mut |masm, reg, size| {
|
794
|
+
masm.ctz(reg, reg, size);
|
795
|
+
TypedReg::i32(reg)
|
796
|
+
});
|
797
|
+
}
|
798
|
+
|
799
|
+
fn visit_i64_ctz(&mut self) {
|
800
|
+
use OperandSize::*;
|
801
|
+
|
802
|
+
self.context.unop(self.masm, S64, &mut |masm, reg, size| {
|
803
|
+
masm.ctz(reg, reg, size);
|
804
|
+
TypedReg::i64(reg)
|
805
|
+
});
|
806
|
+
}
|
807
|
+
|
808
|
+
fn visit_i32_and(&mut self) {
|
809
|
+
self.context.i32_binop(self.masm, |masm, dst, src, size| {
|
810
|
+
masm.and(dst, dst, src, size);
|
811
|
+
TypedReg::i32(dst)
|
812
|
+
});
|
813
|
+
}
|
814
|
+
|
815
|
+
fn visit_i64_and(&mut self) {
|
816
|
+
self.context.i64_binop(self.masm, |masm, dst, src, size| {
|
817
|
+
masm.and(dst, dst, src, size);
|
818
|
+
TypedReg::i64(dst)
|
819
|
+
});
|
820
|
+
}
|
821
|
+
|
822
|
+
fn visit_i32_or(&mut self) {
|
823
|
+
self.context.i32_binop(self.masm, |masm, dst, src, size| {
|
824
|
+
masm.or(dst, dst, src, size);
|
825
|
+
TypedReg::i32(dst)
|
826
|
+
});
|
827
|
+
}
|
828
|
+
|
829
|
+
fn visit_i64_or(&mut self) {
|
830
|
+
self.context.i64_binop(self.masm, |masm, dst, src, size| {
|
831
|
+
masm.or(dst, dst, src, size);
|
832
|
+
TypedReg::i64(dst)
|
833
|
+
});
|
834
|
+
}
|
835
|
+
|
836
|
+
fn visit_i32_xor(&mut self) {
|
837
|
+
self.context.i32_binop(self.masm, |masm, dst, src, size| {
|
838
|
+
masm.xor(dst, dst, src, size);
|
839
|
+
TypedReg::i32(dst)
|
840
|
+
});
|
841
|
+
}
|
842
|
+
|
843
|
+
fn visit_i64_xor(&mut self) {
|
844
|
+
self.context.i64_binop(self.masm, |masm, dst, src, size| {
|
845
|
+
masm.xor(dst, dst, src, size);
|
846
|
+
TypedReg::i64(dst)
|
847
|
+
});
|
848
|
+
}
|
849
|
+
|
850
|
+
fn visit_i32_shl(&mut self) {
|
851
|
+
use OperandSize::*;
|
852
|
+
use ShiftKind::*;
|
853
|
+
|
854
|
+
self.masm.shift(&mut self.context, Shl, S32);
|
855
|
+
}
|
856
|
+
|
857
|
+
fn visit_i64_shl(&mut self) {
|
858
|
+
use OperandSize::*;
|
859
|
+
use ShiftKind::*;
|
860
|
+
|
861
|
+
self.masm.shift(&mut self.context, Shl, S64);
|
862
|
+
}
|
863
|
+
|
864
|
+
fn visit_i32_shr_s(&mut self) {
|
865
|
+
use OperandSize::*;
|
866
|
+
use ShiftKind::*;
|
867
|
+
|
868
|
+
self.masm.shift(&mut self.context, ShrS, S32);
|
869
|
+
}
|
870
|
+
|
871
|
+
fn visit_i64_shr_s(&mut self) {
|
872
|
+
use OperandSize::*;
|
873
|
+
use ShiftKind::*;
|
874
|
+
|
875
|
+
self.masm.shift(&mut self.context, ShrS, S64);
|
876
|
+
}
|
877
|
+
|
878
|
+
fn visit_i32_shr_u(&mut self) {
|
879
|
+
use OperandSize::*;
|
880
|
+
use ShiftKind::*;
|
881
|
+
|
882
|
+
self.masm.shift(&mut self.context, ShrU, S32);
|
883
|
+
}
|
884
|
+
|
885
|
+
fn visit_i64_shr_u(&mut self) {
|
886
|
+
use OperandSize::*;
|
887
|
+
use ShiftKind::*;
|
888
|
+
|
889
|
+
self.masm.shift(&mut self.context, ShrU, S64);
|
890
|
+
}
|
891
|
+
|
892
|
+
fn visit_i32_rotl(&mut self) {
|
893
|
+
use OperandSize::*;
|
894
|
+
use ShiftKind::*;
|
895
|
+
|
896
|
+
self.masm.shift(&mut self.context, Rotl, S32);
|
897
|
+
}
|
898
|
+
|
899
|
+
fn visit_i64_rotl(&mut self) {
|
900
|
+
use OperandSize::*;
|
901
|
+
use ShiftKind::*;
|
902
|
+
|
903
|
+
self.masm.shift(&mut self.context, Rotl, S64);
|
904
|
+
}
|
905
|
+
|
906
|
+
fn visit_i32_rotr(&mut self) {
|
907
|
+
use OperandSize::*;
|
908
|
+
use ShiftKind::*;
|
909
|
+
|
910
|
+
self.masm.shift(&mut self.context, Rotr, S32);
|
911
|
+
}
|
912
|
+
|
913
|
+
fn visit_i64_rotr(&mut self) {
|
914
|
+
use OperandSize::*;
|
915
|
+
use ShiftKind::*;
|
916
|
+
|
917
|
+
self.masm.shift(&mut self.context, Rotr, S64);
|
918
|
+
}
|
919
|
+
|
920
|
+
fn visit_end(&mut self) {
|
921
|
+
if !self.context.reachable {
|
922
|
+
self.handle_unreachable_end();
|
923
|
+
} else {
|
924
|
+
let mut control = self.control_frames.pop().unwrap();
|
925
|
+
let is_outermost = self.control_frames.len() == 0;
|
926
|
+
// If it's not the outermost control stack frame, emit the the full "end" sequence,
|
927
|
+
// which involves, popping results from the value stack, pushing results back to the
|
928
|
+
// value stack and binding the exit label.
|
929
|
+
// Else, pop values from the value stack and bind the exit label.
|
930
|
+
if !is_outermost {
|
931
|
+
control.emit_end(self.masm, &mut self.context);
|
932
|
+
} else {
|
933
|
+
if let Some(data) = control.results() {
|
934
|
+
self.context.pop_abi_results(data, self.masm);
|
935
|
+
}
|
936
|
+
control.bind_exit_label(self.masm);
|
937
|
+
}
|
938
|
+
}
|
939
|
+
}
|
940
|
+
|
941
|
+
fn visit_i32_popcnt(&mut self) {
|
942
|
+
use OperandSize::*;
|
943
|
+
self.masm.popcnt(&mut self.context, S32);
|
944
|
+
}
|
945
|
+
|
946
|
+
fn visit_i64_popcnt(&mut self) {
|
947
|
+
use OperandSize::*;
|
948
|
+
|
949
|
+
self.masm.popcnt(&mut self.context, S64);
|
950
|
+
}
|
951
|
+
|
952
|
+
fn visit_i32_wrap_i64(&mut self) {
|
953
|
+
use OperandSize::*;
|
954
|
+
|
955
|
+
self.context.unop(self.masm, S64, &mut |masm, reg, _size| {
|
956
|
+
masm.wrap(reg, reg);
|
957
|
+
TypedReg::i32(reg)
|
958
|
+
});
|
959
|
+
}
|
960
|
+
|
961
|
+
fn visit_i64_extend_i32_s(&mut self) {
|
962
|
+
use OperandSize::*;
|
963
|
+
|
964
|
+
self.context.unop(self.masm, S32, &mut |masm, reg, _size| {
|
965
|
+
masm.extend(reg, reg, ExtendKind::I64ExtendI32S);
|
966
|
+
TypedReg::i64(reg)
|
967
|
+
});
|
968
|
+
}
|
969
|
+
|
970
|
+
fn visit_i64_extend_i32_u(&mut self) {
|
971
|
+
use OperandSize::*;
|
972
|
+
|
973
|
+
self.context.unop(self.masm, S32, &mut |masm, reg, _size| {
|
974
|
+
masm.extend(reg, reg, ExtendKind::I64ExtendI32U);
|
975
|
+
TypedReg::i64(reg)
|
976
|
+
});
|
977
|
+
}
|
978
|
+
|
979
|
+
fn visit_i32_extend8_s(&mut self) {
|
980
|
+
use OperandSize::*;
|
981
|
+
|
982
|
+
self.context.unop(self.masm, S32, &mut |masm, reg, _size| {
|
983
|
+
masm.extend(reg, reg, ExtendKind::I32Extend8S);
|
984
|
+
TypedReg::i32(reg)
|
985
|
+
});
|
986
|
+
}
|
987
|
+
|
988
|
+
fn visit_i32_extend16_s(&mut self) {
|
989
|
+
use OperandSize::*;
|
990
|
+
|
991
|
+
self.context.unop(self.masm, S32, &mut |masm, reg, _size| {
|
992
|
+
masm.extend(reg, reg, ExtendKind::I32Extend16S);
|
993
|
+
TypedReg::i32(reg)
|
994
|
+
});
|
995
|
+
}
|
996
|
+
|
997
|
+
fn visit_i64_extend8_s(&mut self) {
|
998
|
+
use OperandSize::*;
|
999
|
+
|
1000
|
+
self.context.unop(self.masm, S64, &mut |masm, reg, _size| {
|
1001
|
+
masm.extend(reg, reg, ExtendKind::I64Extend8S);
|
1002
|
+
TypedReg::i64(reg)
|
1003
|
+
});
|
1004
|
+
}
|
1005
|
+
|
1006
|
+
fn visit_i64_extend16_s(&mut self) {
|
1007
|
+
use OperandSize::*;
|
1008
|
+
|
1009
|
+
self.context.unop(self.masm, S64, &mut |masm, reg, _size| {
|
1010
|
+
masm.extend(reg, reg, ExtendKind::I64Extend16S);
|
1011
|
+
TypedReg::i64(reg)
|
1012
|
+
});
|
1013
|
+
}
|
1014
|
+
|
1015
|
+
fn visit_i64_extend32_s(&mut self) {
|
1016
|
+
use OperandSize::*;
|
1017
|
+
|
1018
|
+
self.context.unop(self.masm, S64, &mut |masm, reg, _size| {
|
1019
|
+
masm.extend(reg, reg, ExtendKind::I64Extend32S);
|
1020
|
+
TypedReg::i64(reg)
|
1021
|
+
});
|
1022
|
+
}
|
1023
|
+
|
1024
|
+
fn visit_local_get(&mut self, index: u32) {
|
1025
|
+
use WasmType::*;
|
1026
|
+
let context = &mut self.context;
|
1027
|
+
let slot = context
|
1028
|
+
.frame
|
1029
|
+
.get_local(index)
|
1030
|
+
.unwrap_or_else(|| panic!("valid local at slot = {}", index));
|
1031
|
+
match slot.ty {
|
1032
|
+
I32 | I64 | F32 | F64 => context.stack.push(Val::local(index, slot.ty)),
|
1033
|
+
Ref(rt) => match rt.heap_type {
|
1034
|
+
WasmHeapType::Func => context.stack.push(Val::local(index, slot.ty)),
|
1035
|
+
ht => unimplemented!("Support for WasmHeapType: {ht}"),
|
1036
|
+
},
|
1037
|
+
t => unimplemented!("Support local type: {t}"),
|
1038
|
+
}
|
1039
|
+
}
|
1040
|
+
|
1041
|
+
fn visit_local_set(&mut self, index: u32) {
|
1042
|
+
let src = self.emit_set_local(index);
|
1043
|
+
self.context.free_reg(src);
|
1044
|
+
}
|
1045
|
+
|
1046
|
+
fn visit_call(&mut self, index: u32) {
|
1047
|
+
let callee = self.env.callee_from_index(FuncIndex::from_u32(index));
|
1048
|
+
FnCall::emit::<M, M::Ptr, _>(self.masm, &mut self.context, |_| callee.clone());
|
1049
|
+
}
|
1050
|
+
|
1051
|
+
fn visit_call_indirect(&mut self, type_index: u32, table_index: u32, _: u8) {
|
1052
|
+
// Spill now because `emit_lazy_init_funcref` and the `FnCall::emit`
|
1053
|
+
// invocations will both trigger spills since they both call functions.
|
1054
|
+
// However, the machine instructions for the spill emitted by
|
1055
|
+
// `emit_lazy_funcref` will be jumped over if the funcref was previously
|
1056
|
+
// initialized which may result in the machine stack becoming
|
1057
|
+
// unbalanced.
|
1058
|
+
self.context.spill(self.masm);
|
1059
|
+
|
1060
|
+
let type_index = TypeIndex::from_u32(type_index);
|
1061
|
+
let table_index = TableIndex::from_u32(table_index);
|
1062
|
+
|
1063
|
+
self.emit_lazy_init_funcref(table_index);
|
1064
|
+
|
1065
|
+
// Perform the indirect call.
|
1066
|
+
// This code assumes that [`Self::emit_lazy_init_funcref`] will
|
1067
|
+
// push the funcref to the value stack.
|
1068
|
+
match self.env.translation.module.table_plans[table_index].style {
|
1069
|
+
TableStyle::CallerChecksSignature => {
|
1070
|
+
let funcref_ptr = self.context.stack.peek().map(|v| v.unwrap_reg()).unwrap();
|
1071
|
+
self.masm
|
1072
|
+
.trapz(funcref_ptr.into(), TrapCode::IndirectCallToNull);
|
1073
|
+
self.emit_typecheck_funcref(funcref_ptr.into(), type_index);
|
1074
|
+
}
|
1075
|
+
}
|
1076
|
+
|
1077
|
+
FnCall::emit::<M, M::Ptr, _>(self.masm, &mut self.context, |_| {
|
1078
|
+
self.env.funcref(type_index)
|
1079
|
+
})
|
1080
|
+
}
|
1081
|
+
|
1082
|
+
fn visit_table_init(&mut self, elem: u32, table: u32) {
|
1083
|
+
let ptr_type = self.env.ptr_type();
|
1084
|
+
let vmctx = TypedReg::new(ptr_type, <M::ABI as ABI>::vmctx_reg());
|
1085
|
+
|
1086
|
+
debug_assert!(self.context.stack.len() >= 3);
|
1087
|
+
let at = self.context.stack.len() - 3;
|
1088
|
+
|
1089
|
+
self.context.stack.insert_many(
|
1090
|
+
at,
|
1091
|
+
[
|
1092
|
+
vmctx.into(),
|
1093
|
+
table.try_into().unwrap(),
|
1094
|
+
elem.try_into().unwrap(),
|
1095
|
+
],
|
1096
|
+
);
|
1097
|
+
FnCall::emit::<M, M::Ptr, _>(self.masm, &mut self.context, |cx| {
|
1098
|
+
Callee::Builtin(cx.builtins.table_init::<M::ABI, M::Ptr>())
|
1099
|
+
});
|
1100
|
+
}
|
1101
|
+
|
1102
|
+
fn visit_table_copy(&mut self, dst: u32, src: u32) {
|
1103
|
+
let ptr_type = self.env.ptr_type();
|
1104
|
+
let vmctx = TypedReg::new(ptr_type, <M::ABI as ABI>::vmctx_reg());
|
1105
|
+
debug_assert!(self.context.stack.len() >= 3);
|
1106
|
+
let at = self.context.stack.len() - 3;
|
1107
|
+
self.context.stack.insert_many(
|
1108
|
+
at,
|
1109
|
+
[
|
1110
|
+
vmctx.into(),
|
1111
|
+
dst.try_into().unwrap(),
|
1112
|
+
src.try_into().unwrap(),
|
1113
|
+
],
|
1114
|
+
);
|
1115
|
+
|
1116
|
+
FnCall::emit::<M, M::Ptr, _>(self.masm, &mut self.context, |context| {
|
1117
|
+
Callee::Builtin(context.builtins.table_copy::<M::ABI, M::Ptr>())
|
1118
|
+
});
|
1119
|
+
}
|
1120
|
+
|
1121
|
+
fn visit_table_get(&mut self, table: u32) {
|
1122
|
+
let table_index = TableIndex::from_u32(table);
|
1123
|
+
let plan = self.env.table_plan(table_index);
|
1124
|
+
let heap_type = plan.table.wasm_ty.heap_type;
|
1125
|
+
let style = &plan.style;
|
1126
|
+
|
1127
|
+
match heap_type {
|
1128
|
+
WasmHeapType::Func => match style {
|
1129
|
+
TableStyle::CallerChecksSignature => self.emit_lazy_init_funcref(table_index),
|
1130
|
+
},
|
1131
|
+
t => unimplemented!("Support for WasmHeapType: {t}"),
|
1132
|
+
}
|
1133
|
+
}
|
1134
|
+
|
1135
|
+
fn visit_table_grow(&mut self, table: u32) {
|
1136
|
+
let ptr_type = self.env.ptr_type();
|
1137
|
+
let vmctx = TypedReg::new(ptr_type, <M::ABI as ABI>::vmctx_reg());
|
1138
|
+
let table_index = TableIndex::from_u32(table);
|
1139
|
+
let table_plan = self.env.table_plan(table_index);
|
1140
|
+
let builtin = match table_plan.table.wasm_ty.heap_type {
|
1141
|
+
WasmHeapType::Func => self
|
1142
|
+
.context
|
1143
|
+
.builtins
|
1144
|
+
.table_grow_func_ref::<M::ABI, M::Ptr>(),
|
1145
|
+
ty => unimplemented!("Support for HeapType: {ty}"),
|
1146
|
+
};
|
1147
|
+
|
1148
|
+
let len = self.context.stack.len();
|
1149
|
+
// table.grow` requires at least 2 elements on the value stack.
|
1150
|
+
debug_assert!(len >= 2);
|
1151
|
+
let at = len - 2;
|
1152
|
+
|
1153
|
+
// The table_grow builtin expects the parameters in a different
|
1154
|
+
// order.
|
1155
|
+
// The value stack at this point should contain:
|
1156
|
+
// [ init_value | delta ] (stack top)
|
1157
|
+
// but the builtin function expects the init value as the last
|
1158
|
+
// argument.
|
1159
|
+
self.context.stack.inner_mut().swap(len - 1, len - 2);
|
1160
|
+
self.context
|
1161
|
+
.stack
|
1162
|
+
.insert_many(at, [vmctx.into(), table.try_into().unwrap()]);
|
1163
|
+
|
1164
|
+
FnCall::emit::<M, M::Ptr, _>(self.masm, &mut self.context, |_| {
|
1165
|
+
Callee::Builtin(builtin.clone())
|
1166
|
+
});
|
1167
|
+
}
|
1168
|
+
|
1169
|
+
fn visit_table_size(&mut self, table: u32) {
|
1170
|
+
let table_index = TableIndex::from_u32(table);
|
1171
|
+
let table_data = self.env.resolve_table_data(table_index);
|
1172
|
+
self.masm.table_size(&table_data, &mut self.context);
|
1173
|
+
}
|
1174
|
+
|
1175
|
+
fn visit_table_fill(&mut self, table: u32) {
|
1176
|
+
let ptr_type = self.env.ptr_type();
|
1177
|
+
let vmctx = TypedReg::new(ptr_type, <M::ABI as ABI>::vmctx_reg());
|
1178
|
+
let table_index = TableIndex::from_u32(table);
|
1179
|
+
let table_plan = self.env.table_plan(table_index);
|
1180
|
+
let builtin = match table_plan.table.wasm_ty.heap_type {
|
1181
|
+
WasmHeapType::Func => self
|
1182
|
+
.context
|
1183
|
+
.builtins
|
1184
|
+
.table_fill_func_ref::<M::ABI, M::Ptr>(),
|
1185
|
+
ty => unimplemented!("Support for heap type: {ty}"),
|
1186
|
+
};
|
1187
|
+
|
1188
|
+
let len = self.context.stack.len();
|
1189
|
+
debug_assert!(len >= 3);
|
1190
|
+
let at = len - 3;
|
1191
|
+
self.context
|
1192
|
+
.stack
|
1193
|
+
.insert_many(at, [vmctx.into(), table.try_into().unwrap()]);
|
1194
|
+
FnCall::emit::<M, M::Ptr, _>(self.masm, &mut self.context, |_| {
|
1195
|
+
Callee::Builtin(builtin.clone())
|
1196
|
+
})
|
1197
|
+
}
|
1198
|
+
|
1199
|
+
fn visit_table_set(&mut self, table: u32) {
|
1200
|
+
let ptr_type = self.env.ptr_type();
|
1201
|
+
let table_index = TableIndex::from_u32(table);
|
1202
|
+
let table_data = self.env.resolve_table_data(table_index);
|
1203
|
+
let plan = self.env.table_plan(table_index);
|
1204
|
+
match plan.table.wasm_ty.heap_type {
|
1205
|
+
WasmHeapType::Func => match plan.style {
|
1206
|
+
TableStyle::CallerChecksSignature => {
|
1207
|
+
let value = self.context.pop_to_reg(self.masm, None);
|
1208
|
+
let index = self.context.pop_to_reg(self.masm, None);
|
1209
|
+
let base = self.context.any_gpr(self.masm);
|
1210
|
+
let elem_addr = self.masm.table_elem_address(
|
1211
|
+
index.into(),
|
1212
|
+
base,
|
1213
|
+
&table_data,
|
1214
|
+
&mut self.context,
|
1215
|
+
);
|
1216
|
+
|
1217
|
+
// Set the initialized bit.
|
1218
|
+
self.masm.or(
|
1219
|
+
value.into(),
|
1220
|
+
value.into(),
|
1221
|
+
RegImm::i64(FUNCREF_INIT_BIT as i64),
|
1222
|
+
ptr_type.into(),
|
1223
|
+
);
|
1224
|
+
|
1225
|
+
self.masm.store_ptr(value.into(), elem_addr);
|
1226
|
+
|
1227
|
+
self.context.free_reg(value);
|
1228
|
+
self.context.free_reg(index);
|
1229
|
+
self.context.free_reg(base);
|
1230
|
+
}
|
1231
|
+
},
|
1232
|
+
ty => unimplemented!("Support for WasmHeapType: {ty}"),
|
1233
|
+
};
|
1234
|
+
}
|
1235
|
+
|
1236
|
+
fn visit_elem_drop(&mut self, index: u32) {
|
1237
|
+
let ptr_type = self.env.ptr_type();
|
1238
|
+
let elem_drop = self.context.builtins.elem_drop::<M::ABI, M::Ptr>();
|
1239
|
+
let vmctx = TypedReg::new(ptr_type, <M::ABI as ABI>::vmctx_reg());
|
1240
|
+
self.context
|
1241
|
+
.stack
|
1242
|
+
.extend([vmctx.into(), index.try_into().unwrap()]);
|
1243
|
+
FnCall::emit::<M, M::Ptr, _>(self.masm, &mut self.context, |_| {
|
1244
|
+
Callee::Builtin(elem_drop.clone())
|
1245
|
+
});
|
1246
|
+
}
|
1247
|
+
|
1248
|
+
fn visit_memory_init(&mut self, data_index: u32, mem: u32) {
|
1249
|
+
debug_assert!(self.context.stack.len() >= 3);
|
1250
|
+
let ptr_type = self.env.ptr_type();
|
1251
|
+
let at = self.context.stack.len() - 3;
|
1252
|
+
let vmctx = TypedReg::new(ptr_type, <M::ABI as ABI>::vmctx_reg());
|
1253
|
+
self.context.stack.insert_many(
|
1254
|
+
at,
|
1255
|
+
[
|
1256
|
+
vmctx.into(),
|
1257
|
+
mem.try_into().unwrap(),
|
1258
|
+
data_index.try_into().unwrap(),
|
1259
|
+
],
|
1260
|
+
);
|
1261
|
+
FnCall::emit::<M, M::Ptr, _>(self.masm, &mut self.context, |cx| {
|
1262
|
+
Callee::Builtin(cx.builtins.memory_init::<M::ABI, M::Ptr>())
|
1263
|
+
});
|
1264
|
+
}
|
1265
|
+
|
1266
|
+
fn visit_memory_copy(&mut self, dst_mem: u32, src_mem: u32) {
|
1267
|
+
// At this point, the stack is expected to contain:
|
1268
|
+
// [ dst_offset, src_offset, len ]
|
1269
|
+
// The following code inserts the missing params, so that stack contains:
|
1270
|
+
// [ vmctx, dst_mem, dst_offset, src_mem, src_offset, len ]
|
1271
|
+
// Which is the order expected by the builtin function.
|
1272
|
+
debug_assert!(self.context.stack.len() >= 3);
|
1273
|
+
let ptr_type = self.env.ptr_type();
|
1274
|
+
let vmctx = TypedReg::new(ptr_type, <M::ABI as ABI>::vmctx_reg());
|
1275
|
+
let at = self.context.stack.len() - 2;
|
1276
|
+
self.context
|
1277
|
+
.stack
|
1278
|
+
.insert_many(at, [src_mem.try_into().unwrap()]);
|
1279
|
+
|
1280
|
+
// One element was inserted above, so instead of 3, we use 4.
|
1281
|
+
let at = self.context.stack.len() - 4;
|
1282
|
+
self.context
|
1283
|
+
.stack
|
1284
|
+
.insert_many(at, [vmctx.into(), dst_mem.try_into().unwrap()]);
|
1285
|
+
|
1286
|
+
FnCall::emit::<M, M::Ptr, _>(self.masm, &mut self.context, |cx| {
|
1287
|
+
Callee::Builtin(cx.builtins.memory_copy::<M::ABI, M::Ptr>())
|
1288
|
+
});
|
1289
|
+
}
|
1290
|
+
|
1291
|
+
fn visit_memory_fill(&mut self, mem: u32) {
|
1292
|
+
debug_assert!(self.context.stack.len() >= 3);
|
1293
|
+
let ptr_type = self.env.ptr_type();
|
1294
|
+
let vmctx = TypedReg::new(ptr_type, <M::ABI as ABI>::vmctx_reg());
|
1295
|
+
let at = self.context.stack.len() - 3;
|
1296
|
+
|
1297
|
+
self.context
|
1298
|
+
.stack
|
1299
|
+
.insert_many(at, [vmctx.into(), mem.try_into().unwrap()]);
|
1300
|
+
|
1301
|
+
FnCall::emit::<M, M::Ptr, _>(self.masm, &mut self.context, |cx| {
|
1302
|
+
Callee::Builtin(cx.builtins.memory_fill::<M::ABI, M::Ptr>())
|
1303
|
+
});
|
1304
|
+
}
|
1305
|
+
|
1306
|
+
fn visit_memory_size(&mut self, mem: u32, _: u8) {
|
1307
|
+
let heap = self.env.resolve_heap(MemoryIndex::from_u32(mem));
|
1308
|
+
self.masm.memory_size(&heap, &mut self.context);
|
1309
|
+
}
|
1310
|
+
|
1311
|
+
fn visit_memory_grow(&mut self, mem: u32, _: u8) {
|
1312
|
+
debug_assert!(self.context.stack.len() >= 1);
|
1313
|
+
let ptr_type = self.env.ptr_type();
|
1314
|
+
let vmctx = TypedReg::new(ptr_type, <M::ABI as ABI>::vmctx_reg());
|
1315
|
+
let at = self.context.stack.len() - 1;
|
1316
|
+
// The stack at this point contains: [ delta ]
|
1317
|
+
// The desired state is
|
1318
|
+
// [ vmctx, delta, index ]
|
1319
|
+
self.context.stack.insert_many(at, [vmctx.into()]);
|
1320
|
+
self.context.stack.extend([mem.try_into().unwrap()]);
|
1321
|
+
|
1322
|
+
FnCall::emit::<M, M::Ptr, _>(self.masm, &mut self.context, |cx| {
|
1323
|
+
Callee::Builtin(cx.builtins.memory32_grow::<M::ABI, M::Ptr>())
|
1324
|
+
});
|
1325
|
+
}
|
1326
|
+
|
1327
|
+
fn visit_data_drop(&mut self, data_index: u32) {
|
1328
|
+
let ptr_type = self.env.ptr_type();
|
1329
|
+
let vmctx = TypedReg::new(ptr_type, <M::ABI as ABI>::vmctx_reg());
|
1330
|
+
self.context
|
1331
|
+
.stack
|
1332
|
+
.extend([vmctx.into(), data_index.try_into().unwrap()]);
|
1333
|
+
|
1334
|
+
FnCall::emit::<M, M::Ptr, _>(self.masm, &mut self.context, |cx| {
|
1335
|
+
Callee::Builtin(cx.builtins.data_drop::<M::ABI, M::Ptr>())
|
1336
|
+
});
|
1337
|
+
}
|
1338
|
+
|
1339
|
+
fn visit_nop(&mut self) {}
|
1340
|
+
|
1341
|
+
fn visit_if(&mut self, blockty: BlockType) {
|
1342
|
+
self.control_frames.push(ControlStackFrame::r#if(
|
1343
|
+
self.env.resolve_block_results_data::<M::ABI>(blockty),
|
1344
|
+
self.env.resolve_block_type_info(blockty),
|
1345
|
+
self.masm,
|
1346
|
+
&mut self.context,
|
1347
|
+
));
|
1348
|
+
}
|
1349
|
+
|
1350
|
+
fn visit_else(&mut self) {
|
1351
|
+
if !self.context.reachable {
|
1352
|
+
self.handle_unreachable_else();
|
1353
|
+
} else {
|
1354
|
+
let control = self
|
1355
|
+
.control_frames
|
1356
|
+
.last_mut()
|
1357
|
+
.unwrap_or_else(|| panic!("Expected active control stack frame for else"));
|
1358
|
+
control.emit_else(self.masm, &mut self.context);
|
1359
|
+
}
|
1360
|
+
}
|
1361
|
+
|
1362
|
+
fn visit_block(&mut self, blockty: BlockType) {
|
1363
|
+
self.control_frames.push(ControlStackFrame::block(
|
1364
|
+
self.env.resolve_block_results_data::<M::ABI>(blockty),
|
1365
|
+
self.env.resolve_block_type_info(blockty),
|
1366
|
+
self.masm,
|
1367
|
+
&mut self.context,
|
1368
|
+
));
|
1369
|
+
}
|
1370
|
+
|
1371
|
+
fn visit_loop(&mut self, blockty: BlockType) {
|
1372
|
+
self.control_frames.push(ControlStackFrame::r#loop(
|
1373
|
+
self.env.resolve_block_type_info(blockty),
|
1374
|
+
self.masm,
|
1375
|
+
&mut self.context,
|
1376
|
+
));
|
1377
|
+
}
|
1378
|
+
|
1379
|
+
fn visit_br(&mut self, depth: u32) {
|
1380
|
+
let index = control_index(depth, self.control_frames.len());
|
1381
|
+
let frame = &mut self.control_frames[index];
|
1382
|
+
self.context
|
1383
|
+
.unconditional_jump(frame, self.masm, |masm, cx, frame| {
|
1384
|
+
if let Some(r) = frame.as_target_results() {
|
1385
|
+
cx.pop_abi_results(r, masm);
|
1386
|
+
}
|
1387
|
+
});
|
1388
|
+
}
|
1389
|
+
|
1390
|
+
fn visit_br_if(&mut self, depth: u32) {
|
1391
|
+
let index = control_index(depth, self.control_frames.len());
|
1392
|
+
let frame = &mut self.control_frames[index];
|
1393
|
+
frame.set_as_target();
|
1394
|
+
|
1395
|
+
let top = if let Some(data) = frame.as_target_results() {
|
1396
|
+
let top = self.context.without::<TypedReg, M, _>(
|
1397
|
+
data.results.regs(),
|
1398
|
+
self.masm,
|
1399
|
+
|ctx, masm| ctx.pop_to_reg(masm, None),
|
1400
|
+
);
|
1401
|
+
self.context.top_abi_results(data, self.masm);
|
1402
|
+
top
|
1403
|
+
} else {
|
1404
|
+
self.context.pop_to_reg(self.masm, None)
|
1405
|
+
};
|
1406
|
+
|
1407
|
+
// Emit instructions to balance the machine stack if the frame has
|
1408
|
+
// a different offset.
|
1409
|
+
let current_sp_offset = self.masm.sp_offset();
|
1410
|
+
let (_, frame_sp_offset) = frame.base_stack_len_and_sp();
|
1411
|
+
let (label, cmp, needs_cleanup) = if current_sp_offset > frame_sp_offset {
|
1412
|
+
(self.masm.get_label(), IntCmpKind::Eq, true)
|
1413
|
+
} else {
|
1414
|
+
(*frame.label(), IntCmpKind::Ne, false)
|
1415
|
+
};
|
1416
|
+
|
1417
|
+
self.masm
|
1418
|
+
.branch(cmp, top.reg.into(), top.reg.into(), label, OperandSize::S32);
|
1419
|
+
self.context.free_reg(top);
|
1420
|
+
|
1421
|
+
if needs_cleanup {
|
1422
|
+
// Emit instructions to balance the stack and jump if not falling
|
1423
|
+
// through.
|
1424
|
+
self.masm.ensure_sp_for_jump(frame_sp_offset);
|
1425
|
+
self.masm.jmp(*frame.label());
|
1426
|
+
|
1427
|
+
// Restore sp_offset to what it was for falling through and emit
|
1428
|
+
// fallthrough label.
|
1429
|
+
self.masm.reset_stack_pointer(current_sp_offset);
|
1430
|
+
self.masm.bind(label);
|
1431
|
+
}
|
1432
|
+
}
|
1433
|
+
|
1434
|
+
fn visit_br_table(&mut self, targets: BrTable<'a>) {
|
1435
|
+
// +1 to account for the default target.
|
1436
|
+
let len = targets.len() + 1;
|
1437
|
+
// SmallVec<[_; 5]> to match the binary emission layer (e.g
|
1438
|
+
// see `JmpTableSeq'), but here we use 5 instead since we
|
1439
|
+
// bundle the default target as the last element in the array.
|
1440
|
+
let labels: SmallVec<[_; 5]> = (0..len).map(|_| self.masm.get_label()).collect();
|
1441
|
+
|
1442
|
+
let default_index = control_index(targets.default(), self.control_frames.len());
|
1443
|
+
let default_result = self.control_frames[default_index].as_target_results();
|
1444
|
+
|
1445
|
+
let (index, tmp) = if let Some(data) = default_result {
|
1446
|
+
let index_and_tmp = self.context.without::<(TypedReg, _), M, _>(
|
1447
|
+
data.results.regs(),
|
1448
|
+
self.masm,
|
1449
|
+
|cx, masm| (cx.pop_to_reg(masm, None), cx.any_gpr(masm)),
|
1450
|
+
);
|
1451
|
+
|
1452
|
+
// Materialize any constants or locals into their result representation,
|
1453
|
+
// so that when reachability is restored, they are correctly located.
|
1454
|
+
self.context.top_abi_results(data, self.masm);
|
1455
|
+
index_and_tmp
|
1456
|
+
} else {
|
1457
|
+
(
|
1458
|
+
self.context.pop_to_reg(self.masm, None),
|
1459
|
+
self.context.any_gpr(self.masm),
|
1460
|
+
)
|
1461
|
+
};
|
1462
|
+
|
1463
|
+
self.masm.jmp_table(&labels, index.into(), tmp);
|
1464
|
+
// Save the original stack pointer offset; we will reset the stack
|
1465
|
+
// pointer to this offset after jumping to each of the targets. Each
|
1466
|
+
// jump might adjust the stack according to the base offset of the
|
1467
|
+
// target.
|
1468
|
+
let current_sp = self.masm.sp_offset();
|
1469
|
+
|
1470
|
+
for (t, l) in targets
|
1471
|
+
.targets()
|
1472
|
+
.into_iter()
|
1473
|
+
.chain(std::iter::once(Ok(targets.default())))
|
1474
|
+
.zip(labels.iter())
|
1475
|
+
{
|
1476
|
+
let control_index = control_index(t.unwrap(), self.control_frames.len());
|
1477
|
+
let frame = &mut self.control_frames[control_index];
|
1478
|
+
// Reset the stack pointer to its original offset. This is needed
|
1479
|
+
// because each jump will potentially adjust the stack pointer
|
1480
|
+
// according to the base offset of the target.
|
1481
|
+
self.masm.reset_stack_pointer(current_sp);
|
1482
|
+
|
1483
|
+
// NB: We don't perform any result handling as it was
|
1484
|
+
// already taken care of above before jumping to the
|
1485
|
+
// jump table.
|
1486
|
+
self.masm.bind(*l);
|
1487
|
+
// Ensure that the stack pointer is correctly positioned before
|
1488
|
+
// jumping to the jump table code.
|
1489
|
+
let (_, offset) = frame.base_stack_len_and_sp();
|
1490
|
+
self.masm.ensure_sp_for_jump(offset);
|
1491
|
+
self.masm.jmp(*frame.label());
|
1492
|
+
frame.set_as_target();
|
1493
|
+
}
|
1494
|
+
// Finally reset the stack pointer to the original location.
|
1495
|
+
// The reachability analysis, will ensure it's correctly located
|
1496
|
+
// once reachability is restored.
|
1497
|
+
self.masm.reset_stack_pointer(current_sp);
|
1498
|
+
self.context.reachable = false;
|
1499
|
+
self.context.free_reg(index.reg);
|
1500
|
+
self.context.free_reg(tmp);
|
1501
|
+
}
|
1502
|
+
|
1503
|
+
fn visit_return(&mut self) {
|
1504
|
+
// Grab the outermost frame, which is the function's body
|
1505
|
+
// frame. We don't rely on [`codegen::control_index`] since
|
1506
|
+
// this frame is implicit and we know that it should exist at
|
1507
|
+
// index 0.
|
1508
|
+
let outermost = &mut self.control_frames[0];
|
1509
|
+
self.context
|
1510
|
+
.unconditional_jump(outermost, self.masm, |masm, cx, frame| {
|
1511
|
+
if let Some(data) = frame.as_target_results() {
|
1512
|
+
cx.pop_abi_results(data, masm);
|
1513
|
+
}
|
1514
|
+
});
|
1515
|
+
}
|
1516
|
+
|
1517
|
+
fn visit_unreachable(&mut self) {
|
1518
|
+
self.masm.unreachable();
|
1519
|
+
self.context.reachable = false;
|
1520
|
+
// Set the implicit outermost frame as target to perform the necessary
|
1521
|
+
// stack clean up.
|
1522
|
+
let outermost = &mut self.control_frames[0];
|
1523
|
+
outermost.set_as_target();
|
1524
|
+
}
|
1525
|
+
|
1526
|
+
fn visit_local_tee(&mut self, index: u32) {
|
1527
|
+
let typed_reg = self.emit_set_local(index);
|
1528
|
+
self.context.stack.push(typed_reg.into());
|
1529
|
+
}
|
1530
|
+
|
1531
|
+
fn visit_global_get(&mut self, global_index: u32) {
|
1532
|
+
let index = GlobalIndex::from_u32(global_index);
|
1533
|
+
let (ty, offset) = self.env.resolve_global_type_and_offset(index);
|
1534
|
+
let addr = self
|
1535
|
+
.masm
|
1536
|
+
.address_at_reg(<M::ABI as ABI>::vmctx_reg(), offset);
|
1537
|
+
let dst = self.context.reg_for_type(ty, self.masm);
|
1538
|
+
self.masm.load(addr, dst, ty.into());
|
1539
|
+
self.context.stack.push(Val::reg(dst, ty));
|
1540
|
+
}
|
1541
|
+
|
1542
|
+
fn visit_global_set(&mut self, global_index: u32) {
|
1543
|
+
let index = GlobalIndex::from_u32(global_index);
|
1544
|
+
let (ty, offset) = self.env.resolve_global_type_and_offset(index);
|
1545
|
+
let addr = self
|
1546
|
+
.masm
|
1547
|
+
.address_at_reg(<M::ABI as ABI>::vmctx_reg(), offset);
|
1548
|
+
let typed_reg = self.context.pop_to_reg(self.masm, None);
|
1549
|
+
self.context.free_reg(typed_reg.reg);
|
1550
|
+
self.masm.store(typed_reg.reg.into(), addr, ty.into());
|
1551
|
+
}
|
1552
|
+
|
1553
|
+
fn visit_drop(&mut self) {
|
1554
|
+
self.context.drop_last(1, |regalloc, val| match val {
|
1555
|
+
Val::Reg(tr) => regalloc.free(tr.reg.into()),
|
1556
|
+
Val::Memory(m) => self.masm.free_stack(m.slot.size),
|
1557
|
+
_ => {}
|
1558
|
+
});
|
1559
|
+
}
|
1560
|
+
|
1561
|
+
fn visit_select(&mut self) {
|
1562
|
+
let cond = self.context.pop_to_reg(self.masm, None);
|
1563
|
+
let val2 = self.context.pop_to_reg(self.masm, None);
|
1564
|
+
let val1 = self.context.pop_to_reg(self.masm, None);
|
1565
|
+
self.masm
|
1566
|
+
.cmp(RegImm::i32(0), cond.reg.into(), OperandSize::S32);
|
1567
|
+
// Conditionally move val1 to val2 if the the comparision is
|
1568
|
+
// not zero.
|
1569
|
+
self.masm
|
1570
|
+
.cmov(val1.into(), val2.into(), IntCmpKind::Ne, val1.ty.into());
|
1571
|
+
self.context.stack.push(val2.into());
|
1572
|
+
self.context.free_reg(val1.reg);
|
1573
|
+
self.context.free_reg(cond);
|
1574
|
+
}
|
1575
|
+
|
1576
|
+
wasmparser::for_each_operator!(def_unsupported);
|
1577
|
+
}
|
1578
|
+
|
1579
|
+
impl<'a, 'translation, 'data, M> CodeGen<'a, 'translation, 'data, M>
|
1580
|
+
where
|
1581
|
+
M: MacroAssembler,
|
1582
|
+
{
|
1583
|
+
fn cmp_i32s(&mut self, kind: IntCmpKind) {
|
1584
|
+
self.context.i32_binop(self.masm, |masm, dst, src, size| {
|
1585
|
+
masm.cmp_with_set(src, dst, kind, size);
|
1586
|
+
TypedReg::i32(dst)
|
1587
|
+
});
|
1588
|
+
}
|
1589
|
+
|
1590
|
+
fn cmp_i64s(&mut self, kind: IntCmpKind) {
|
1591
|
+
self.context
|
1592
|
+
.i64_binop(self.masm, move |masm, dst, src, size| {
|
1593
|
+
masm.cmp_with_set(src, dst, kind, size);
|
1594
|
+
TypedReg::i32(dst) // Return value for comparisons is an `i32`.
|
1595
|
+
});
|
1596
|
+
}
|
1597
|
+
}
|
1598
|
+
|
1599
|
+
impl From<WasmType> for OperandSize {
|
1600
|
+
fn from(ty: WasmType) -> OperandSize {
|
1601
|
+
match ty {
|
1602
|
+
WasmType::I32 | WasmType::F32 => OperandSize::S32,
|
1603
|
+
WasmType::I64 | WasmType::F64 => OperandSize::S64,
|
1604
|
+
WasmType::Ref(rt) => {
|
1605
|
+
match rt.heap_type {
|
1606
|
+
// TODO: Harcoded size, assuming 64-bit support only. Once
|
1607
|
+
// Wasmtime supports 32-bit architectures, this will need
|
1608
|
+
// to be updated in such a way that the calculation of the
|
1609
|
+
// OperandSize will depend on the target's pointer size.
|
1610
|
+
WasmHeapType::Func => OperandSize::S64,
|
1611
|
+
t => unimplemented!("Support for WasmHeapType: {t}"),
|
1612
|
+
}
|
1613
|
+
}
|
1614
|
+
ty => unimplemented!("Support for WasmType {ty}"),
|
1615
|
+
}
|
1616
|
+
}
|
1617
|
+
}
|