wasmtime 16.0.0 → 17.0.0

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Files changed (1111) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +103 -79
  3. data/ext/Cargo.toml +7 -6
  4. data/ext/cargo-vendor/cranelift-bforest-0.104.0/.cargo-checksum.json +1 -0
  5. data/ext/cargo-vendor/cranelift-bforest-0.104.0/Cargo.toml +40 -0
  6. data/ext/cargo-vendor/cranelift-codegen-0.104.0/.cargo-checksum.json +1 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.104.0/Cargo.toml +175 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.104.0/build.rs +392 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/isa/aarch64/inst.isle +4197 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/isa/aarch64/lower/isle.rs +882 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/isa/x64/abi.rs +1305 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/isle_prelude.rs +957 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/machinst/isle.rs +908 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/machinst/mod.rs +558 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/machinst/pcc.rs +159 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/arithmetic.isle +169 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/bitops.isle +188 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/cprop.isle +248 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/extends.isle +116 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/icmp.isle +197 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/selects.isle +77 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/shifts.isle +307 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts/spaceship.isle +194 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/opts.rs +265 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/prelude.isle +641 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/prelude_lower.isle +1073 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.104.0/src/prelude_opt.isle +134 -0
  28. data/ext/cargo-vendor/cranelift-codegen-meta-0.104.0/.cargo-checksum.json +1 -0
  29. data/ext/cargo-vendor/cranelift-codegen-meta-0.104.0/Cargo.toml +35 -0
  30. data/ext/cargo-vendor/cranelift-codegen-shared-0.104.0/.cargo-checksum.json +1 -0
  31. data/ext/cargo-vendor/cranelift-codegen-shared-0.104.0/Cargo.toml +22 -0
  32. data/ext/cargo-vendor/cranelift-control-0.104.0/.cargo-checksum.json +1 -0
  33. data/ext/cargo-vendor/cranelift-control-0.104.0/Cargo.toml +30 -0
  34. data/ext/cargo-vendor/cranelift-entity-0.104.0/.cargo-checksum.json +1 -0
  35. data/ext/cargo-vendor/cranelift-entity-0.104.0/Cargo.toml +50 -0
  36. data/ext/cargo-vendor/cranelift-entity-0.104.0/src/primary.rs +541 -0
  37. data/ext/cargo-vendor/cranelift-frontend-0.104.0/.cargo-checksum.json +1 -0
  38. data/ext/cargo-vendor/cranelift-frontend-0.104.0/Cargo.toml +68 -0
  39. data/ext/cargo-vendor/cranelift-isle-0.104.0/.cargo-checksum.json +1 -0
  40. data/ext/cargo-vendor/cranelift-isle-0.104.0/Cargo.toml +46 -0
  41. data/ext/cargo-vendor/cranelift-native-0.104.0/.cargo-checksum.json +1 -0
  42. data/ext/cargo-vendor/cranelift-native-0.104.0/Cargo.toml +43 -0
  43. data/ext/cargo-vendor/cranelift-wasm-0.104.0/.cargo-checksum.json +1 -0
  44. data/ext/cargo-vendor/cranelift-wasm-0.104.0/Cargo.toml +106 -0
  45. data/ext/cargo-vendor/cranelift-wasm-0.104.0/src/code_translator.rs +3646 -0
  46. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/.cargo-checksum.json +1 -0
  47. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/Cargo.toml +49 -0
  48. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/README.md +52 -0
  49. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/src/clocks.rs +56 -0
  50. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/src/lib.rs +24 -0
  51. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/src/noop_scheduler.rs +25 -0
  52. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/tests/clocks.rs +33 -0
  53. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/tests/common/mod.rs +33 -0
  54. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/tests/random.rs +17 -0
  55. data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.18/tests/scheduler.rs +24 -0
  56. data/ext/cargo-vendor/rand_pcg-0.3.1/.cargo-checksum.json +1 -0
  57. data/ext/cargo-vendor/rand_pcg-0.3.1/CHANGELOG.md +37 -0
  58. data/ext/cargo-vendor/rand_pcg-0.3.1/COPYRIGHT +12 -0
  59. data/ext/cargo-vendor/rand_pcg-0.3.1/Cargo.toml +37 -0
  60. data/ext/cargo-vendor/rand_pcg-0.3.1/LICENSE-APACHE +201 -0
  61. data/ext/cargo-vendor/rand_pcg-0.3.1/LICENSE-MIT +26 -0
  62. data/ext/cargo-vendor/rand_pcg-0.3.1/README.md +42 -0
  63. data/ext/cargo-vendor/rand_pcg-0.3.1/src/lib.rs +45 -0
  64. data/ext/cargo-vendor/rand_pcg-0.3.1/src/pcg128.rs +296 -0
  65. data/ext/cargo-vendor/rand_pcg-0.3.1/src/pcg64.rs +166 -0
  66. data/ext/cargo-vendor/rand_pcg-0.3.1/tests/lcg128xsl64.rs +77 -0
  67. data/ext/cargo-vendor/rand_pcg-0.3.1/tests/lcg64xsh32.rs +70 -0
  68. data/ext/cargo-vendor/rand_pcg-0.3.1/tests/mcg128xsl64.rs +75 -0
  69. data/ext/cargo-vendor/wasi-cap-std-sync-17.0.0/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/wasi-cap-std-sync-17.0.0/Cargo.toml +102 -0
  71. data/ext/cargo-vendor/wasi-common-17.0.0/.cargo-checksum.json +1 -0
  72. data/ext/cargo-vendor/wasi-common-17.0.0/Cargo.toml +131 -0
  73. data/ext/cargo-vendor/wasi-common-17.0.0/src/error.rs +26 -0
  74. data/ext/cargo-vendor/wasi-common-17.0.0/src/snapshots/preview_1/error.rs +266 -0
  75. data/ext/cargo-vendor/wasmtime-17.0.0/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/wasmtime-17.0.0/Cargo.toml +211 -0
  77. data/ext/cargo-vendor/wasmtime-17.0.0/src/component/component.rs +545 -0
  78. data/ext/cargo-vendor/wasmtime-17.0.0/src/component/instance.rs +815 -0
  79. data/ext/cargo-vendor/wasmtime-17.0.0/src/component/linker.rs +580 -0
  80. data/ext/cargo-vendor/wasmtime-17.0.0/src/component/matching.rs +215 -0
  81. data/ext/cargo-vendor/wasmtime-17.0.0/src/component/mod.rs +351 -0
  82. data/ext/cargo-vendor/wasmtime-17.0.0/src/component/resource_table.rs +350 -0
  83. data/ext/cargo-vendor/wasmtime-17.0.0/src/component/resources.rs +823 -0
  84. data/ext/cargo-vendor/wasmtime-17.0.0/src/config.rs +2428 -0
  85. data/ext/cargo-vendor/wasmtime-17.0.0/src/func/typed.rs +638 -0
  86. data/ext/cargo-vendor/wasmtime-17.0.0/src/lib.rs +526 -0
  87. data/ext/cargo-vendor/wasmtime-17.0.0/src/store.rs +2389 -0
  88. data/ext/cargo-vendor/wasmtime-asm-macros-17.0.0/.cargo-checksum.json +1 -0
  89. data/ext/cargo-vendor/wasmtime-asm-macros-17.0.0/Cargo.toml +22 -0
  90. data/ext/cargo-vendor/wasmtime-cache-17.0.0/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/wasmtime-cache-17.0.0/Cargo.toml +81 -0
  92. data/ext/cargo-vendor/wasmtime-component-macro-17.0.0/.cargo-checksum.json +1 -0
  93. data/ext/cargo-vendor/wasmtime-component-macro-17.0.0/Cargo.toml +67 -0
  94. data/ext/cargo-vendor/wasmtime-component-macro-17.0.0/src/bindgen.rs +371 -0
  95. data/ext/cargo-vendor/wasmtime-component-macro-17.0.0/tests/codegen/multiversion/root.wit +8 -0
  96. data/ext/cargo-vendor/wasmtime-component-util-17.0.0/.cargo-checksum.json +1 -0
  97. data/ext/cargo-vendor/wasmtime-component-util-17.0.0/Cargo.toml +25 -0
  98. data/ext/cargo-vendor/wasmtime-cranelift-17.0.0/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/wasmtime-cranelift-17.0.0/Cargo.toml +112 -0
  100. data/ext/cargo-vendor/wasmtime-cranelift-shared-17.0.0/.cargo-checksum.json +1 -0
  101. data/ext/cargo-vendor/wasmtime-cranelift-shared-17.0.0/Cargo.toml +71 -0
  102. data/ext/cargo-vendor/wasmtime-environ-17.0.0/.cargo-checksum.json +1 -0
  103. data/ext/cargo-vendor/wasmtime-environ-17.0.0/Cargo.lock +726 -0
  104. data/ext/cargo-vendor/wasmtime-environ-17.0.0/Cargo.toml +125 -0
  105. data/ext/cargo-vendor/wasmtime-environ-17.0.0/examples/factc.rs +205 -0
  106. data/ext/cargo-vendor/wasmtime-fiber-17.0.0/.cargo-checksum.json +1 -0
  107. data/ext/cargo-vendor/wasmtime-fiber-17.0.0/Cargo.toml +63 -0
  108. data/ext/cargo-vendor/wasmtime-jit-17.0.0/.cargo-checksum.json +1 -0
  109. data/ext/cargo-vendor/wasmtime-jit-17.0.0/Cargo.toml +125 -0
  110. data/ext/cargo-vendor/wasmtime-jit-debug-17.0.0/.cargo-checksum.json +1 -0
  111. data/ext/cargo-vendor/wasmtime-jit-debug-17.0.0/Cargo.toml +67 -0
  112. data/ext/cargo-vendor/wasmtime-jit-icache-coherence-17.0.0/.cargo-checksum.json +1 -0
  113. data/ext/cargo-vendor/wasmtime-jit-icache-coherence-17.0.0/Cargo.toml +46 -0
  114. data/ext/cargo-vendor/wasmtime-runtime-17.0.0/.cargo-checksum.json +1 -0
  115. data/ext/cargo-vendor/wasmtime-runtime-17.0.0/Cargo.toml +139 -0
  116. data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/instance/allocator/pooling/memory_pool.rs +997 -0
  117. data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/instance/allocator/pooling.rs +658 -0
  118. data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/memory.rs +973 -0
  119. data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/parking_spot.rs +622 -0
  120. data/ext/cargo-vendor/wasmtime-runtime-17.0.0/src/sys/windows/mmap.rs +216 -0
  121. data/ext/cargo-vendor/wasmtime-types-17.0.0/.cargo-checksum.json +1 -0
  122. data/ext/cargo-vendor/wasmtime-types-17.0.0/Cargo.toml +36 -0
  123. data/ext/cargo-vendor/wasmtime-versioned-export-macros-17.0.0/.cargo-checksum.json +1 -0
  124. data/ext/cargo-vendor/wasmtime-versioned-export-macros-17.0.0/Cargo.toml +32 -0
  125. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/.cargo-checksum.json +1 -0
  126. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/Cargo.toml +261 -0
  127. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/ctx.rs +333 -0
  128. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/filesystem.rs +325 -0
  129. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/clocks.rs +103 -0
  130. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/filesystem.rs +1069 -0
  131. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/instance_network.rs +15 -0
  132. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/network.rs +625 -0
  133. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/tcp.rs +605 -0
  134. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/host/udp.rs +530 -0
  135. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/mod.rs +327 -0
  136. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/network.rs +108 -0
  137. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/poll.rs +175 -0
  138. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/preview1.rs +2362 -0
  139. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/stream.rs +181 -0
  140. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/tcp.rs +335 -0
  141. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/src/preview2/udp.rs +125 -0
  142. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/tests/all/api.rs +217 -0
  143. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/tests/all/async_.rs +364 -0
  144. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/tests/all/main.rs +112 -0
  145. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/tests/all/preview1.rs +243 -0
  146. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/tests/all/sync.rs +303 -0
  147. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/command-extended.wit +6 -0
  148. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/cli/command.wit +7 -0
  149. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/cli/imports.wit +20 -0
  150. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/cli/stdio.wit +17 -0
  151. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/cli/terminal.wit +49 -0
  152. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/clocks/monotonic-clock.wit +45 -0
  153. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/clocks/wall-clock.wit +42 -0
  154. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/clocks/world.wit +6 -0
  155. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/filesystem/preopens.wit +8 -0
  156. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/filesystem/types.wit +634 -0
  157. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/filesystem/world.wit +6 -0
  158. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/http/proxy.wit +32 -0
  159. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/http/types.wit +570 -0
  160. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/io/error.wit +34 -0
  161. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/io/poll.wit +41 -0
  162. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/io/streams.wit +251 -0
  163. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/io/world.wit +6 -0
  164. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/random/insecure-seed.wit +25 -0
  165. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/random/insecure.wit +22 -0
  166. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/random/random.wit +26 -0
  167. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/random/world.wit +7 -0
  168. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/sockets/ip-name-lookup.wit +51 -0
  169. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/sockets/network.wit +145 -0
  170. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/sockets/tcp-create-socket.wit +27 -0
  171. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/sockets/tcp.wit +309 -0
  172. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/sockets/udp-create-socket.wit +27 -0
  173. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/sockets/udp.wit +264 -0
  174. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/deps/sockets/world.wit +11 -0
  175. data/ext/cargo-vendor/wasmtime-wasi-17.0.0/wit/test.wit +22 -0
  176. data/ext/cargo-vendor/wasmtime-winch-17.0.0/.cargo-checksum.json +1 -0
  177. data/ext/cargo-vendor/wasmtime-winch-17.0.0/Cargo.toml +77 -0
  178. data/ext/cargo-vendor/wasmtime-wit-bindgen-17.0.0/.cargo-checksum.json +1 -0
  179. data/ext/cargo-vendor/wasmtime-wit-bindgen-17.0.0/Cargo.toml +41 -0
  180. data/ext/cargo-vendor/wasmtime-wit-bindgen-17.0.0/src/lib.rs +2097 -0
  181. data/ext/cargo-vendor/wasmtime-wmemcheck-17.0.0/.cargo-checksum.json +1 -0
  182. data/ext/cargo-vendor/wasmtime-wmemcheck-17.0.0/Cargo.toml +29 -0
  183. data/ext/cargo-vendor/wiggle-17.0.0/.cargo-checksum.json +1 -0
  184. data/ext/cargo-vendor/wiggle-17.0.0/Cargo.toml +115 -0
  185. data/ext/cargo-vendor/wiggle-generate-17.0.0/.cargo-checksum.json +1 -0
  186. data/ext/cargo-vendor/wiggle-generate-17.0.0/Cargo.toml +65 -0
  187. data/ext/cargo-vendor/wiggle-macro-17.0.0/.cargo-checksum.json +1 -0
  188. data/ext/cargo-vendor/wiggle-macro-17.0.0/Cargo.toml +55 -0
  189. data/ext/cargo-vendor/winch-codegen-0.15.0/.cargo-checksum.json +1 -0
  190. data/ext/cargo-vendor/winch-codegen-0.15.0/Cargo.toml +76 -0
  191. data/ext/cargo-vendor/winch-codegen-0.15.0/src/codegen/context.rs +553 -0
  192. data/ext/cargo-vendor/winch-codegen-0.15.0/src/codegen/env.rs +309 -0
  193. data/ext/cargo-vendor/winch-codegen-0.15.0/src/isa/aarch64/masm.rs +457 -0
  194. data/ext/cargo-vendor/winch-codegen-0.15.0/src/isa/x64/asm.rs +1149 -0
  195. data/ext/cargo-vendor/winch-codegen-0.15.0/src/isa/x64/masm.rs +1044 -0
  196. data/ext/cargo-vendor/winch-codegen-0.15.0/src/masm.rs +708 -0
  197. data/ext/cargo-vendor/winch-codegen-0.15.0/src/stack.rs +452 -0
  198. data/ext/cargo-vendor/winch-codegen-0.15.0/src/visitor.rs +1617 -0
  199. data/ext/src/helpers/mod.rs +4 -0
  200. data/ext/src/helpers/nogvl.rs +29 -0
  201. data/ext/src/helpers/tmplock.rs +45 -0
  202. data/ext/src/ruby_api/engine.rs +7 -3
  203. data/ext/src/ruby_api/mod.rs +3 -0
  204. data/ext/src/ruby_api/module.rs +22 -8
  205. data/ext/src/ruby_api/store.rs +66 -12
  206. data/ext/src/ruby_api/wasi_ctx.rs +110 -0
  207. data/ext/src/ruby_api/wasi_ctx_builder.rs +10 -7
  208. data/lib/wasmtime/version.rb +1 -1
  209. metadata +931 -904
  210. data/ext/cargo-vendor/cranelift-bforest-0.103.0/.cargo-checksum.json +0 -1
  211. data/ext/cargo-vendor/cranelift-bforest-0.103.0/Cargo.toml +0 -40
  212. data/ext/cargo-vendor/cranelift-codegen-0.103.0/.cargo-checksum.json +0 -1
  213. data/ext/cargo-vendor/cranelift-codegen-0.103.0/Cargo.toml +0 -175
  214. data/ext/cargo-vendor/cranelift-codegen-0.103.0/build.rs +0 -391
  215. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/aarch64/inst.isle +0 -4193
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  389. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/LICENSE +0 -0
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  410. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/fx.rs +0 -0
  411. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/incremental_cache.rs +0 -0
  412. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/inst_predicates.rs +0 -0
  413. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/atomic_rmw_op.rs +0 -0
  414. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/builder.rs +0 -0
  415. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/condcodes.rs +0 -0
  416. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/constant.rs +0 -0
  417. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/dfg.rs +0 -0
  418. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/dynamic_type.rs +0 -0
  419. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/entities.rs +0 -0
  420. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/extfunc.rs +0 -0
  421. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/extname.rs +0 -0
  422. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/function.rs +0 -0
  423. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/globalvalue.rs +0 -0
  424. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/immediates.rs +0 -0
  425. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/instructions.rs +0 -0
  426. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/jumptable.rs +0 -0
  427. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/known_symbol.rs +0 -0
  428. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/layout.rs +0 -0
  429. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/libcall.rs +0 -0
  430. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/memflags.rs +0 -0
  431. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/memtype.rs +0 -0
  432. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/mod.rs +0 -0
  433. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/pcc.rs +0 -0
  434. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/progpoint.rs +0 -0
  435. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/sourceloc.rs +0 -0
  436. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/stackslot.rs +0 -0
  437. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/table.rs +0 -0
  438. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/trapcode.rs +0 -0
  439. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/ir/types.rs +0 -0
  440. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/abi.rs +0 -0
  441. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/inst/args.rs +0 -0
  442. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/inst/emit.rs +0 -0
  443. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/inst/emit_tests.rs +0 -0
  444. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/inst/imms.rs +0 -0
  445. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/inst/mod.rs +0 -0
  446. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/inst/regs.rs +0 -0
  447. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  448. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/inst/unwind.rs +0 -0
  449. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/inst_neon.isle +0 -0
  450. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  451. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/lower.isle +0 -0
  452. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/lower.rs +0 -0
  453. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  454. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/mod.rs +0 -0
  455. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/pcc.rs +0 -0
  456. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/aarch64/settings.rs +0 -0
  457. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/call_conv.rs +0 -0
  458. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/mod.rs +0 -0
  459. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/abi.rs +0 -0
  460. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/inst/args.rs +0 -0
  461. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/inst/emit.rs +0 -0
  462. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/inst/emit_tests.rs +0 -0
  463. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/inst/encode.rs +0 -0
  464. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/inst/imms.rs +0 -0
  465. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/inst/mod.rs +0 -0
  466. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/inst/regs.rs +0 -0
  467. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/inst/unwind/systemv.rs +0 -0
  468. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/inst/unwind.rs +0 -0
  469. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/inst/vector.rs +0 -0
  470. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/inst.isle +0 -0
  471. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/inst_vector.isle +0 -0
  472. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  473. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/lower/isle.rs +0 -0
  474. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/lower.isle +0 -0
  475. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/lower.rs +0 -0
  476. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/mod.rs +0 -0
  477. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/riscv64/settings.rs +0 -0
  478. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/abi.rs +0 -0
  479. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/inst/args.rs +0 -0
  480. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/inst/emit.rs +0 -0
  481. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/inst/emit_tests.rs +0 -0
  482. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/inst/imms.rs +0 -0
  483. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/inst/mod.rs +0 -0
  484. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/inst/regs.rs +0 -0
  485. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  486. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/inst/unwind.rs +0 -0
  487. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/inst.isle +0 -0
  488. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  489. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/lower/isle.rs +0 -0
  490. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/lower.isle +0 -0
  491. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/lower.rs +0 -0
  492. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/mod.rs +0 -0
  493. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/s390x/settings.rs +0 -0
  494. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/unwind/systemv.rs +0 -0
  495. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/unwind/winx64.rs +0 -0
  496. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/unwind.rs +0 -0
  497. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/encoding/evex.rs +0 -0
  498. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/encoding/mod.rs +0 -0
  499. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/encoding/rex.rs +0 -0
  500. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/encoding/vex.rs +0 -0
  501. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/inst/args.rs +0 -0
  502. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/inst/emit.rs +0 -0
  503. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/inst/emit_state.rs +0 -0
  504. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/inst/emit_tests.rs +0 -0
  505. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/inst/mod.rs +0 -0
  506. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/inst/regs.rs +0 -0
  507. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  508. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  509. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/inst/unwind.rs +0 -0
  510. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/inst.isle +0 -0
  511. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  512. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/lower/isle.rs +0 -0
  513. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/lower.isle +0 -0
  514. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/lower.rs +0 -0
  515. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/mod.rs +0 -0
  516. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/pcc.rs +0 -0
  517. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/isa/x64/settings.rs +0 -0
  518. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/iterators.rs +0 -0
  519. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/legalizer/globalvalue.rs +0 -0
  520. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/legalizer/mod.rs +0 -0
  521. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/legalizer/table.rs +0 -0
  522. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/lib.rs +0 -0
  523. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/loop_analysis.rs +0 -0
  524. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/machinst/abi.rs +0 -0
  525. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/machinst/blockorder.rs +0 -0
  526. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/machinst/buffer.rs +0 -0
  527. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/machinst/compile.rs +0 -0
  528. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/machinst/helpers.rs +0 -0
  529. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/machinst/inst_common.rs +0 -0
  530. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/machinst/lower.rs +0 -0
  531. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/machinst/reg.rs +0 -0
  532. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/machinst/valueregs.rs +0 -0
  533. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/machinst/vcode.rs +0 -0
  534. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/nan_canonicalization.rs +0 -0
  535. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/opts/README.md +0 -0
  536. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/opts/generated_code.rs +0 -0
  537. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/opts/remat.isle +0 -0
  538. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/opts/vector.isle +0 -0
  539. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/print_errors.rs +0 -0
  540. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/remove_constant_phis.rs +0 -0
  541. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/result.rs +0 -0
  542. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/scoped_hash_map.rs +0 -0
  543. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/settings.rs +0 -0
  544. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/souper_harvest.rs +0 -0
  545. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/timing.rs +0 -0
  546. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/unionfind.rs +0 -0
  547. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/unreachable_code.rs +0 -0
  548. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/value_label.rs +0 -0
  549. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/verifier/mod.rs +0 -0
  550. /data/ext/cargo-vendor/{cranelift-codegen-0.103.0 → cranelift-codegen-0.104.0}/src/write.rs +0 -0
  551. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/LICENSE +0 -0
  552. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/README.md +0 -0
  553. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/cdsl/formats.rs +0 -0
  554. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/cdsl/instructions.rs +0 -0
  555. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/cdsl/isa.rs +0 -0
  556. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/cdsl/mod.rs +0 -0
  557. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/cdsl/operands.rs +0 -0
  558. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/cdsl/settings.rs +0 -0
  559. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/cdsl/types.rs +0 -0
  560. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/cdsl/typevar.rs +0 -0
  561. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/constant_hash.rs +0 -0
  562. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/error.rs +0 -0
  563. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/gen_inst.rs +0 -0
  564. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/gen_settings.rs +0 -0
  565. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/gen_types.rs +0 -0
  566. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/isa/arm64.rs +0 -0
  567. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/isa/mod.rs +0 -0
  568. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/isa/riscv64.rs +0 -0
  569. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/isa/s390x.rs +0 -0
  570. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/isa/x86.rs +0 -0
  571. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/lib.rs +0 -0
  572. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/shared/entities.rs +0 -0
  573. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/shared/formats.rs +0 -0
  574. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/shared/immediates.rs +0 -0
  575. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/shared/instructions.rs +0 -0
  576. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/shared/mod.rs +0 -0
  577. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/shared/settings.rs +0 -0
  578. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/shared/types.rs +0 -0
  579. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/srcgen.rs +0 -0
  580. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.103.0 → cranelift-codegen-meta-0.104.0}/src/unique_table.rs +0 -0
  581. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.103.0 → cranelift-codegen-shared-0.104.0}/LICENSE +0 -0
  582. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.103.0 → cranelift-codegen-shared-0.104.0}/README.md +0 -0
  583. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.103.0 → cranelift-codegen-shared-0.104.0}/src/constant_hash.rs +0 -0
  584. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.103.0 → cranelift-codegen-shared-0.104.0}/src/constants.rs +0 -0
  585. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.103.0 → cranelift-codegen-shared-0.104.0}/src/lib.rs +0 -0
  586. /data/ext/cargo-vendor/{cranelift-control-0.103.0 → cranelift-control-0.104.0}/LICENSE +0 -0
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  588. /data/ext/cargo-vendor/{cranelift-control-0.103.0 → cranelift-control-0.104.0}/src/chaos.rs +0 -0
  589. /data/ext/cargo-vendor/{cranelift-control-0.103.0 → cranelift-control-0.104.0}/src/lib.rs +0 -0
  590. /data/ext/cargo-vendor/{cranelift-control-0.103.0 → cranelift-control-0.104.0}/src/zero_sized.rs +0 -0
  591. /data/ext/cargo-vendor/{cranelift-entity-0.103.0 → cranelift-entity-0.104.0}/LICENSE +0 -0
  592. /data/ext/cargo-vendor/{cranelift-entity-0.103.0 → cranelift-entity-0.104.0}/README.md +0 -0
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  599. /data/ext/cargo-vendor/{cranelift-entity-0.103.0 → cranelift-entity-0.104.0}/src/packed_option.rs +0 -0
  600. /data/ext/cargo-vendor/{cranelift-entity-0.103.0 → cranelift-entity-0.104.0}/src/set.rs +0 -0
  601. /data/ext/cargo-vendor/{cranelift-entity-0.103.0 → cranelift-entity-0.104.0}/src/sparse.rs +0 -0
  602. /data/ext/cargo-vendor/{cranelift-entity-0.103.0 → cranelift-entity-0.104.0}/src/unsigned.rs +0 -0
  603. /data/ext/cargo-vendor/{cranelift-frontend-0.103.0 → cranelift-frontend-0.104.0}/LICENSE +0 -0
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  631. /data/ext/cargo-vendor/{cranelift-isle-0.103.0 → cranelift-isle-0.104.0}/isle_examples/pass/bound_var.isle +0 -0
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  647. /data/ext/cargo-vendor/{cranelift-isle-0.103.0 → cranelift-isle-0.104.0}/src/codegen.rs +0 -0
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  657. /data/ext/cargo-vendor/{cranelift-isle-0.103.0 → cranelift-isle-0.104.0}/src/trie_again.rs +0 -0
  658. /data/ext/cargo-vendor/{cranelift-isle-0.103.0 → cranelift-isle-0.104.0}/tests/run_tests.rs +0 -0
  659. /data/ext/cargo-vendor/{cranelift-native-0.103.0 → cranelift-native-0.104.0}/LICENSE +0 -0
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  662. /data/ext/cargo-vendor/{cranelift-native-0.103.0 → cranelift-native-0.104.0}/src/riscv.rs +0 -0
  663. /data/ext/cargo-vendor/{cranelift-wasm-0.103.0 → cranelift-wasm-0.104.0}/LICENSE +0 -0
  664. /data/ext/cargo-vendor/{cranelift-wasm-0.103.0 → cranelift-wasm-0.104.0}/README.md +0 -0
  665. /data/ext/cargo-vendor/{cranelift-wasm-0.103.0 → cranelift-wasm-0.104.0}/src/code_translator/bounds_checks.rs +0 -0
  666. /data/ext/cargo-vendor/{cranelift-wasm-0.103.0 → cranelift-wasm-0.104.0}/src/environ/dummy.rs +0 -0
  667. /data/ext/cargo-vendor/{cranelift-wasm-0.103.0 → cranelift-wasm-0.104.0}/src/environ/mod.rs +0 -0
  668. /data/ext/cargo-vendor/{cranelift-wasm-0.103.0 → cranelift-wasm-0.104.0}/src/environ/spec.rs +0 -0
  669. /data/ext/cargo-vendor/{cranelift-wasm-0.103.0 → cranelift-wasm-0.104.0}/src/func_translator.rs +0 -0
  670. /data/ext/cargo-vendor/{cranelift-wasm-0.103.0 → cranelift-wasm-0.104.0}/src/heap.rs +0 -0
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  674. /data/ext/cargo-vendor/{cranelift-wasm-0.103.0 → cranelift-wasm-0.104.0}/src/state.rs +0 -0
  675. /data/ext/cargo-vendor/{cranelift-wasm-0.103.0 → cranelift-wasm-0.104.0}/src/translation_utils.rs +0 -0
  676. /data/ext/cargo-vendor/{cranelift-wasm-0.103.0 → cranelift-wasm-0.104.0}/tests/wasm_testsuite.rs +0 -0
  677. /data/ext/cargo-vendor/{cranelift-wasm-0.103.0 → cranelift-wasm-0.104.0}/wasmtests/arith.wat +0 -0
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  856. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/rename.wit +0 -0
  857. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/resources-export.wit +0 -0
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  859. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/share-types.wit +0 -0
  860. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/simple-functions.wit +0 -0
  861. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/simple-lists.wit +0 -0
  862. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/simple-wasi.wit +0 -0
  863. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/small-anonymous.wit +0 -0
  864. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/smoke-default.wit +0 -0
  865. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/smoke-export.wit +0 -0
  866. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/smoke.wit +0 -0
  867. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/strings.wit +0 -0
  868. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/use-paths.wit +0 -0
  869. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/variants.wit +0 -0
  870. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen/worlds-with-types.wit +0 -0
  871. /data/ext/cargo-vendor/{wasmtime-component-macro-16.0.0 → wasmtime-component-macro-17.0.0}/tests/codegen.rs +0 -0
  872. /data/ext/cargo-vendor/{wasmtime-component-util-16.0.0 → wasmtime-component-util-17.0.0}/src/lib.rs +0 -0
  873. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/LICENSE +0 -0
  874. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/SECURITY.md +0 -0
  875. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/builder.rs +0 -0
  876. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/compiler/component.rs +0 -0
  877. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/compiler.rs +0 -0
  878. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug/gc.rs +0 -0
  879. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug/transform/address_transform.rs +0 -0
  880. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug/transform/attr.rs +0 -0
  881. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug/transform/expression.rs +0 -0
  882. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug/transform/line_program.rs +0 -0
  883. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug/transform/mod.rs +0 -0
  884. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug/transform/range_info_builder.rs +0 -0
  885. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug/transform/refs.rs +0 -0
  886. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug/transform/simulate.rs +0 -0
  887. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug/transform/unit.rs +0 -0
  888. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug/transform/utils.rs +0 -0
  889. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug/write_debuginfo.rs +0 -0
  890. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/debug.rs +0 -0
  891. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/func_environ.rs +0 -0
  892. /data/ext/cargo-vendor/{wasmtime-cranelift-16.0.0 → wasmtime-cranelift-17.0.0}/src/lib.rs +0 -0
  893. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-16.0.0 → wasmtime-cranelift-shared-17.0.0}/src/compiled_function.rs +0 -0
  894. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-16.0.0 → wasmtime-cranelift-shared-17.0.0}/src/isa_builder.rs +0 -0
  895. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-16.0.0 → wasmtime-cranelift-shared-17.0.0}/src/lib.rs +0 -0
  896. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-16.0.0 → wasmtime-cranelift-shared-17.0.0}/src/obj.rs +0 -0
  897. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/LICENSE +0 -0
  898. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/address_map.rs +0 -0
  899. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/builtin.rs +0 -0
  900. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/compilation.rs +0 -0
  901. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/component/compiler.rs +0 -0
  902. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/component/dfg.rs +0 -0
  903. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/component/info.rs +0 -0
  904. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/component/translate/adapt.rs +0 -0
  905. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/component/translate/inline.rs +0 -0
  906. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/component/translate.rs +0 -0
  907. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/component/types/resources.rs +0 -0
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  913. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/fact/trampoline.rs +0 -0
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  921. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/obj.rs +0 -0
  922. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/ref_bits.rs +0 -0
  923. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/scopevec.rs +0 -0
  924. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/stack_map.rs +0 -0
  925. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/trap_encoding.rs +0 -0
  926. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/tunables.rs +0 -0
  927. /data/ext/cargo-vendor/{wasmtime-environ-16.0.0 → wasmtime-environ-17.0.0}/src/vmoffsets.rs +0 -0
  928. /data/ext/cargo-vendor/{wasmtime-fiber-16.0.0 → wasmtime-fiber-17.0.0}/LICENSE +0 -0
  929. /data/ext/cargo-vendor/{wasmtime-fiber-16.0.0 → wasmtime-fiber-17.0.0}/build.rs +0 -0
  930. /data/ext/cargo-vendor/{wasmtime-fiber-16.0.0 → wasmtime-fiber-17.0.0}/src/lib.rs +0 -0
  931. /data/ext/cargo-vendor/{wasmtime-fiber-16.0.0 → wasmtime-fiber-17.0.0}/src/unix/aarch64.rs +0 -0
  932. /data/ext/cargo-vendor/{wasmtime-fiber-16.0.0 → wasmtime-fiber-17.0.0}/src/unix/arm.rs +0 -0
  933. /data/ext/cargo-vendor/{wasmtime-fiber-16.0.0 → wasmtime-fiber-17.0.0}/src/unix/riscv64.rs +0 -0
  934. /data/ext/cargo-vendor/{wasmtime-fiber-16.0.0 → wasmtime-fiber-17.0.0}/src/unix/s390x.S +0 -0
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  938. /data/ext/cargo-vendor/{wasmtime-fiber-16.0.0 → wasmtime-fiber-17.0.0}/src/windows.c +0 -0
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  940. /data/ext/cargo-vendor/{wasmtime-jit-16.0.0 → wasmtime-jit-17.0.0}/LICENSE +0 -0
  941. /data/ext/cargo-vendor/{wasmtime-jit-16.0.0 → wasmtime-jit-17.0.0}/src/code_memory.rs +0 -0
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  948. /data/ext/cargo-vendor/{wasmtime-jit-16.0.0 → wasmtime-jit-17.0.0}/src/profiling/vtune.rs +0 -0
  949. /data/ext/cargo-vendor/{wasmtime-jit-16.0.0 → wasmtime-jit-17.0.0}/src/profiling.rs +0 -0
  950. /data/ext/cargo-vendor/{wasmtime-jit-debug-16.0.0 → wasmtime-jit-debug-17.0.0}/README.md +0 -0
  951. /data/ext/cargo-vendor/{wasmtime-jit-debug-16.0.0 → wasmtime-jit-debug-17.0.0}/src/gdb_jit_int.rs +0 -0
  952. /data/ext/cargo-vendor/{wasmtime-jit-debug-16.0.0 → wasmtime-jit-debug-17.0.0}/src/lib.rs +0 -0
  953. /data/ext/cargo-vendor/{wasmtime-jit-debug-16.0.0 → wasmtime-jit-debug-17.0.0}/src/perf_jitdump.rs +0 -0
  954. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-16.0.0 → wasmtime-jit-icache-coherence-17.0.0}/src/lib.rs +0 -0
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  957. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-16.0.0 → wasmtime-jit-icache-coherence-17.0.0}/src/win.rs +0 -0
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  961. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/arch/aarch64.rs +0 -0
  962. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/arch/mod.rs +0 -0
  963. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/arch/riscv64.rs +0 -0
  964. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/arch/s390x.S +0 -0
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  966. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/arch/x86_64.rs +0 -0
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  972. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/export.rs +0 -0
  973. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/externref.rs +0 -0
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  976. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/instance/allocator/on_demand.rs +0 -0
  977. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/instance/allocator/pooling/index_allocator.rs +0 -0
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  981. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/instance.rs +0 -0
  982. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/lib.rs +0 -0
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  984. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/mmap.rs +0 -0
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  986. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/module_id.rs +0 -0
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  1002. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/sys/unix/mmap.rs +0 -0
  1003. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/sys/unix/mod.rs +0 -0
  1004. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/sys/unix/signals.rs +0 -0
  1005. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/sys/unix/unwind.rs +0 -0
  1006. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/sys/unix/vm.rs +0 -0
  1007. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/sys/windows/mod.rs +0 -0
  1008. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/sys/windows/traphandlers.rs +0 -0
  1009. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/sys/windows/unwind.rs +0 -0
  1010. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/sys/windows/vm.rs +0 -0
  1011. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/table.rs +0 -0
  1012. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/traphandlers/backtrace.rs +0 -0
  1013. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/traphandlers/coredump.rs +0 -0
  1014. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/traphandlers.rs +0 -0
  1015. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/vmcontext/vm_host_func_context.rs +0 -0
  1016. /data/ext/cargo-vendor/{wasmtime-runtime-16.0.0 → wasmtime-runtime-17.0.0}/src/vmcontext.rs +0 -0
  1017. /data/ext/cargo-vendor/{wasmtime-types-16.0.0 → wasmtime-types-17.0.0}/LICENSE +0 -0
  1018. /data/ext/cargo-vendor/{wasmtime-types-16.0.0 → wasmtime-types-17.0.0}/src/error.rs +0 -0
  1019. /data/ext/cargo-vendor/{wasmtime-types-16.0.0 → wasmtime-types-17.0.0}/src/lib.rs +0 -0
  1020. /data/ext/cargo-vendor/{wasmtime-versioned-export-macros-16.0.0 → wasmtime-versioned-export-macros-17.0.0}/src/lib.rs +0 -0
  1021. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/LICENSE +0 -0
  1022. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/README.md +0 -0
  1023. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/build.rs +0 -0
  1024. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/lib.rs +0 -0
  1025. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/clocks/host.rs +0 -0
  1026. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/clocks.rs +0 -0
  1027. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/command.rs +0 -0
  1028. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/error.rs +0 -0
  1029. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/host/env.rs +0 -0
  1030. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/host/exit.rs +0 -0
  1031. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/host/filesystem/sync.rs +0 -0
  1032. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/host/io.rs +0 -0
  1033. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/host/mod.rs +0 -0
  1034. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/host/random.rs +0 -0
  1035. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/host/tcp_create_socket.rs +0 -0
  1036. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/host/udp_create_socket.rs +0 -0
  1037. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/ip_name_lookup.rs +0 -0
  1038. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/pipe.rs +0 -0
  1039. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/preview0.rs +0 -0
  1040. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/random.rs +0 -0
  1041. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/stdio/worker_thread_stdin.rs +0 -0
  1042. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/stdio.rs +0 -0
  1043. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/src/preview2/write_stream.rs +0 -0
  1044. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/tests/process_stdin.rs +0 -0
  1045. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/cli/environment.wit +0 -0
  1046. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/cli/exit.wit +0 -0
  1047. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/cli/run.wit +0 -0
  1048. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/http/handler.wit +0 -0
  1049. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/wit/deps/sockets/instance-network.wit +0 -0
  1050. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/witx/preview0/typenames.witx +0 -0
  1051. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/witx/preview0/wasi_unstable.witx +0 -0
  1052. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/witx/preview1/typenames.witx +0 -0
  1053. /data/ext/cargo-vendor/{wasmtime-wasi-16.0.0 → wasmtime-wasi-17.0.0}/witx/preview1/wasi_snapshot_preview1.witx +0 -0
  1054. /data/ext/cargo-vendor/{wasmtime-winch-16.0.0 → wasmtime-winch-17.0.0}/LICENSE +0 -0
  1055. /data/ext/cargo-vendor/{wasmtime-winch-16.0.0 → wasmtime-winch-17.0.0}/src/builder.rs +0 -0
  1056. /data/ext/cargo-vendor/{wasmtime-winch-16.0.0 → wasmtime-winch-17.0.0}/src/compiler.rs +0 -0
  1057. /data/ext/cargo-vendor/{wasmtime-winch-16.0.0 → wasmtime-winch-17.0.0}/src/lib.rs +0 -0
  1058. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-16.0.0 → wasmtime-wit-bindgen-17.0.0}/src/rust.rs +0 -0
  1059. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-16.0.0 → wasmtime-wit-bindgen-17.0.0}/src/source.rs +0 -0
  1060. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-16.0.0 → wasmtime-wit-bindgen-17.0.0}/src/types.rs +0 -0
  1061. /data/ext/cargo-vendor/{wasmtime-wmemcheck-16.0.0 → wasmtime-wmemcheck-17.0.0}/src/lib.rs +0 -0
  1062. /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/LICENSE +0 -0
  1063. /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/README.md +0 -0
  1064. /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/borrow.rs +0 -0
  1065. /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/error.rs +0 -0
  1066. /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/guest_type.rs +0 -0
  1067. /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/lib.rs +0 -0
  1068. /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/region.rs +0 -0
  1069. /data/ext/cargo-vendor/{wiggle-16.0.0 → wiggle-17.0.0}/src/wasmtime.rs +0 -0
  1070. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/LICENSE +0 -0
  1071. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/README.md +0 -0
  1072. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/codegen_settings.rs +0 -0
  1073. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/config.rs +0 -0
  1074. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/funcs.rs +0 -0
  1075. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/lib.rs +0 -0
  1076. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/lifetimes.rs +0 -0
  1077. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/module_trait.rs +0 -0
  1078. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/names.rs +0 -0
  1079. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/error.rs +0 -0
  1080. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/flags.rs +0 -0
  1081. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/handle.rs +0 -0
  1082. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/mod.rs +0 -0
  1083. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/record.rs +0 -0
  1084. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/types/variant.rs +0 -0
  1085. /data/ext/cargo-vendor/{wiggle-generate-16.0.0 → wiggle-generate-17.0.0}/src/wasmtime.rs +0 -0
  1086. /data/ext/cargo-vendor/{wiggle-macro-16.0.0 → wiggle-macro-17.0.0}/LICENSE +0 -0
  1087. /data/ext/cargo-vendor/{wiggle-macro-16.0.0 → wiggle-macro-17.0.0}/src/lib.rs +0 -0
  1088. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/LICENSE +0 -0
  1089. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/build.rs +0 -0
  1090. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/abi/local.rs +0 -0
  1091. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/abi/mod.rs +0 -0
  1092. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/codegen/builtin.rs +0 -0
  1093. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/codegen/call.rs +0 -0
  1094. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/codegen/control.rs +0 -0
  1095. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/codegen/mod.rs +0 -0
  1096. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/frame/mod.rs +0 -0
  1097. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/abi.rs +0 -0
  1098. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/address.rs +0 -0
  1099. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/asm.rs +0 -0
  1100. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/mod.rs +0 -0
  1101. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/aarch64/regs.rs +0 -0
  1102. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/mod.rs +0 -0
  1103. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/reg.rs +0 -0
  1104. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/x64/abi.rs +0 -0
  1105. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/x64/address.rs +0 -0
  1106. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/x64/mod.rs +0 -0
  1107. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/isa/x64/regs.rs +0 -0
  1108. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/lib.rs +0 -0
  1109. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/regalloc.rs +0 -0
  1110. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/regset.rs +0 -0
  1111. /data/ext/cargo-vendor/{winch-codegen-0.14.0 → winch-codegen-0.15.0}/src/trampoline.rs +0 -0
@@ -1,4193 +0,0 @@
1
- ;; Instruction formats.
2
- (type MInst
3
- (enum
4
- ;; A no-op of zero size.
5
- (Nop0)
6
-
7
- ;; A no-op that is one instruction large.
8
- (Nop4)
9
-
10
- ;; An ALU operation with two register sources and a register destination.
11
- (AluRRR
12
- (alu_op ALUOp)
13
- (size OperandSize)
14
- (rd WritableReg)
15
- (rn Reg)
16
- (rm Reg))
17
-
18
- ;; An ALU operation with three register sources and a register destination.
19
- (AluRRRR
20
- (alu_op ALUOp3)
21
- (size OperandSize)
22
- (rd WritableReg)
23
- (rn Reg)
24
- (rm Reg)
25
- (ra Reg))
26
-
27
- ;; An ALU operation with a register source and an immediate-12 source, and a register
28
- ;; destination.
29
- (AluRRImm12
30
- (alu_op ALUOp)
31
- (size OperandSize)
32
- (rd WritableReg)
33
- (rn Reg)
34
- (imm12 Imm12))
35
-
36
- ;; An ALU operation with a register source and an immediate-logic source, and a register destination.
37
- (AluRRImmLogic
38
- (alu_op ALUOp)
39
- (size OperandSize)
40
- (rd WritableReg)
41
- (rn Reg)
42
- (imml ImmLogic))
43
-
44
- ;; An ALU operation with a register source and an immediate-shiftamt source, and a register destination.
45
- (AluRRImmShift
46
- (alu_op ALUOp)
47
- (size OperandSize)
48
- (rd WritableReg)
49
- (rn Reg)
50
- (immshift ImmShift))
51
-
52
- ;; An ALU operation with two register sources, one of which can be shifted, and a register
53
- ;; destination.
54
- (AluRRRShift
55
- (alu_op ALUOp)
56
- (size OperandSize)
57
- (rd WritableReg)
58
- (rn Reg)
59
- (rm Reg)
60
- (shiftop ShiftOpAndAmt))
61
-
62
- ;; An ALU operation with two register sources, one of which can be {zero,sign}-extended and
63
- ;; shifted, and a register destination.
64
- (AluRRRExtend
65
- (alu_op ALUOp)
66
- (size OperandSize)
67
- (rd WritableReg)
68
- (rn Reg)
69
- (rm Reg)
70
- (extendop ExtendOp))
71
-
72
- ;; A bit op instruction with a single register source.
73
- (BitRR
74
- (op BitOp)
75
- (size OperandSize)
76
- (rd WritableReg)
77
- (rn Reg))
78
-
79
- ;; An unsigned (zero-extending) 8-bit load.
80
- (ULoad8
81
- (rd WritableReg)
82
- (mem AMode)
83
- (flags MemFlags))
84
-
85
- ;; A signed (sign-extending) 8-bit load.
86
- (SLoad8
87
- (rd WritableReg)
88
- (mem AMode)
89
- (flags MemFlags))
90
-
91
- ;; An unsigned (zero-extending) 16-bit load.
92
- (ULoad16
93
- (rd WritableReg)
94
- (mem AMode)
95
- (flags MemFlags))
96
-
97
- ;; A signed (sign-extending) 16-bit load.
98
- (SLoad16
99
- (rd WritableReg)
100
- (mem AMode)
101
- (flags MemFlags))
102
-
103
- ;; An unsigned (zero-extending) 32-bit load.
104
- (ULoad32
105
- (rd WritableReg)
106
- (mem AMode)
107
- (flags MemFlags))
108
-
109
- ;; A signed (sign-extending) 32-bit load.
110
- (SLoad32
111
- (rd WritableReg)
112
- (mem AMode)
113
- (flags MemFlags))
114
-
115
- ;; A 64-bit load.
116
- (ULoad64
117
- (rd WritableReg)
118
- (mem AMode)
119
- (flags MemFlags))
120
-
121
- ;; An 8-bit store.
122
- (Store8
123
- (rd Reg)
124
- (mem AMode)
125
- (flags MemFlags))
126
-
127
- ;; A 16-bit store.
128
- (Store16
129
- (rd Reg)
130
- (mem AMode)
131
- (flags MemFlags))
132
-
133
- ;; A 32-bit store.
134
- (Store32
135
- (rd Reg)
136
- (mem AMode)
137
- (flags MemFlags))
138
-
139
- ;; A 64-bit store.
140
- (Store64
141
- (rd Reg)
142
- (mem AMode)
143
- (flags MemFlags))
144
-
145
- ;; A store of a pair of registers.
146
- (StoreP64
147
- (rt Reg)
148
- (rt2 Reg)
149
- (mem PairAMode)
150
- (flags MemFlags))
151
-
152
- ;; A load of a pair of registers.
153
- (LoadP64
154
- (rt WritableReg)
155
- (rt2 WritableReg)
156
- (mem PairAMode)
157
- (flags MemFlags))
158
-
159
- ;; A MOV instruction. These are encoded as ORR's (AluRRR form).
160
- ;; The 32-bit version zeroes the top 32 bits of the
161
- ;; destination, which is effectively an alias for an unsigned
162
- ;; 32-to-64-bit extension.
163
- (Mov
164
- (size OperandSize)
165
- (rd WritableReg)
166
- (rm Reg))
167
-
168
- ;; Like `Move` but with a particular `PReg` source (for implementing CLIF
169
- ;; instructions like `get_stack_pointer`).
170
- (MovFromPReg
171
- (rd WritableReg)
172
- (rm PReg))
173
-
174
- ;; Like `Move` but with a particular `PReg` destination (for
175
- ;; implementing CLIF instructions like `set_pinned_reg`).
176
- (MovToPReg
177
- (rd PReg)
178
- (rm Reg))
179
-
180
- ;; A MOV[Z,N] with a 16-bit immediate.
181
- (MovWide
182
- (op MoveWideOp)
183
- (rd WritableReg)
184
- (imm MoveWideConst)
185
- (size OperandSize))
186
-
187
- ;; A MOVK with a 16-bit immediate. Modifies its register; we
188
- ;; model this with a seprate input `rn` and output `rd` virtual
189
- ;; register, with a regalloc constraint to tie them together.
190
- (MovK
191
- (rd WritableReg)
192
- (rn Reg)
193
- (imm MoveWideConst)
194
- (size OperandSize))
195
-
196
-
197
- ;; A sign- or zero-extend operation.
198
- (Extend
199
- (rd WritableReg)
200
- (rn Reg)
201
- (signed bool)
202
- (from_bits u8)
203
- (to_bits u8))
204
-
205
- ;; A conditional-select operation.
206
- (CSel
207
- (rd WritableReg)
208
- (cond Cond)
209
- (rn Reg)
210
- (rm Reg))
211
-
212
- ;; A conditional-select negation operation.
213
- (CSNeg
214
- (rd WritableReg)
215
- (cond Cond)
216
- (rn Reg)
217
- (rm Reg))
218
-
219
- ;; A conditional-set operation.
220
- (CSet
221
- (rd WritableReg)
222
- (cond Cond))
223
-
224
- ;; A conditional-set-mask operation.
225
- (CSetm
226
- (rd WritableReg)
227
- (cond Cond))
228
-
229
- ;; A conditional comparison with a second register.
230
- (CCmp
231
- (size OperandSize)
232
- (rn Reg)
233
- (rm Reg)
234
- (nzcv NZCV)
235
- (cond Cond))
236
-
237
- ;; A conditional comparison with an immediate.
238
- (CCmpImm
239
- (size OperandSize)
240
- (rn Reg)
241
- (imm UImm5)
242
- (nzcv NZCV)
243
- (cond Cond))
244
-
245
- ;; A synthetic insn, which is a load-linked store-conditional loop, that has the overall
246
- ;; effect of atomically modifying a memory location in a particular way. Because we have
247
- ;; no way to explain to the regalloc about earlyclobber registers, this instruction has
248
- ;; completely fixed operand registers, and we rely on the RA's coalescing to remove copies
249
- ;; in the surrounding code to the extent it can. Load- and store-exclusive instructions,
250
- ;; with acquire-release semantics, are used to access memory. The operand conventions are:
251
- ;;
252
- ;; x25 (rd) address
253
- ;; x26 (rd) second operand for `op`
254
- ;; x27 (wr) old value
255
- ;; x24 (wr) scratch reg; value afterwards has no meaning
256
- ;; x28 (wr) scratch reg; value afterwards has no meaning
257
- (AtomicRMWLoop
258
- (ty Type) ;; I8, I16, I32 or I64
259
- (op AtomicRMWLoopOp)
260
- (flags MemFlags)
261
- (addr Reg)
262
- (operand Reg)
263
- (oldval WritableReg)
264
- (scratch1 WritableReg)
265
- (scratch2 WritableReg))
266
-
267
- ;; Similar to AtomicRMWLoop, a compare-and-swap operation implemented using a load-linked
268
- ;; store-conditional loop, with acquire-release semantics.
269
- ;; Note that the operand conventions, although very similar to AtomicRMWLoop, are different:
270
- ;;
271
- ;; x25 (rd) address
272
- ;; x26 (rd) expected value
273
- ;; x28 (rd) replacement value
274
- ;; x27 (wr) old value
275
- ;; x24 (wr) scratch reg; value afterwards has no meaning
276
- (AtomicCASLoop
277
- (ty Type) ;; I8, I16, I32 or I64
278
- (flags MemFlags)
279
- (addr Reg)
280
- (expected Reg)
281
- (replacement Reg)
282
- (oldval WritableReg)
283
- (scratch WritableReg))
284
-
285
- ;; An atomic read-modify-write operation. These instructions require the
286
- ;; Large System Extension (LSE) ISA support (FEAT_LSE). The instructions have
287
- ;; acquire-release semantics.
288
- (AtomicRMW
289
- (op AtomicRMWOp)
290
- (rs Reg)
291
- (rt WritableReg)
292
- (rn Reg)
293
- (ty Type)
294
- (flags MemFlags))
295
-
296
- ;; An atomic compare-and-swap operation. These instructions require the
297
- ;; Large System Extension (LSE) ISA support (FEAT_LSE). The instructions have
298
- ;; acquire-release semantics.
299
- (AtomicCAS
300
- ;; `rd` is really `rs` in the encoded instruction (so `rd` == `rs`); we separate
301
- ;; them here to have separate use and def vregs for regalloc.
302
- (rd WritableReg)
303
- (rs Reg)
304
- (rt Reg)
305
- (rn Reg)
306
- (ty Type)
307
- (flags MemFlags))
308
-
309
- ;; Read `access_ty` bits from address `rt`, either 8, 16, 32 or 64-bits, and put
310
- ;; it in `rn`, optionally zero-extending to fill a word or double word result.
311
- ;; This instruction is sequentially consistent.
312
- (LoadAcquire
313
- (access_ty Type) ;; I8, I16, I32 or I64
314
- (rt WritableReg)
315
- (rn Reg)
316
- (flags MemFlags))
317
-
318
- ;; Write the lowest `ty` bits of `rt` to address `rn`.
319
- ;; This instruction is sequentially consistent.
320
- (StoreRelease
321
- (access_ty Type) ;; I8, I16, I32 or I64
322
- (rt Reg)
323
- (rn Reg)
324
- (flags MemFlags))
325
-
326
- ;; A memory fence. This must provide ordering to ensure that, at a minimum, neither loads
327
- ;; nor stores may move forwards or backwards across the fence. Currently emitted as "dmb
328
- ;; ish". This instruction is sequentially consistent.
329
- (Fence)
330
-
331
- ;; Consumption of speculative data barrier.
332
- (Csdb)
333
-
334
- ;; FPU move. Note that this is distinct from a vector-register
335
- ;; move; moving just 64 bits seems to be significantly faster.
336
- (FpuMove64
337
- (rd WritableReg)
338
- (rn Reg))
339
-
340
- ;; Vector register move.
341
- (FpuMove128
342
- (rd WritableReg)
343
- (rn Reg))
344
-
345
- ;; Move to scalar from a vector element.
346
- (FpuMoveFromVec
347
- (rd WritableReg)
348
- (rn Reg)
349
- (idx u8)
350
- (size VectorSize))
351
-
352
- ;; Zero-extend a SIMD & FP scalar to the full width of a vector register.
353
- ;; 16-bit scalars require half-precision floating-point support (FEAT_FP16).
354
- (FpuExtend
355
- (rd WritableReg)
356
- (rn Reg)
357
- (size ScalarSize))
358
-
359
- ;; 1-op FPU instruction.
360
- (FpuRR
361
- (fpu_op FPUOp1)
362
- (size ScalarSize)
363
- (rd WritableReg)
364
- (rn Reg))
365
-
366
- ;; 2-op FPU instruction.
367
- (FpuRRR
368
- (fpu_op FPUOp2)
369
- (size ScalarSize)
370
- (rd WritableReg)
371
- (rn Reg)
372
- (rm Reg))
373
-
374
- (FpuRRI
375
- (fpu_op FPUOpRI)
376
- (rd WritableReg)
377
- (rn Reg))
378
-
379
- ;; Variant of FpuRRI that modifies its `rd`, and so we name the
380
- ;; input state `ri` (for "input") and constrain the two
381
- ;; together.
382
- (FpuRRIMod
383
- (fpu_op FPUOpRIMod)
384
- (rd WritableReg)
385
- (ri Reg)
386
- (rn Reg))
387
-
388
-
389
- ;; 3-op FPU instruction.
390
- ;; 16-bit scalars require half-precision floating-point support (FEAT_FP16).
391
- (FpuRRRR
392
- (fpu_op FPUOp3)
393
- (size ScalarSize)
394
- (rd WritableReg)
395
- (rn Reg)
396
- (rm Reg)
397
- (ra Reg))
398
-
399
- ;; FPU comparison.
400
- (FpuCmp
401
- (size ScalarSize)
402
- (rn Reg)
403
- (rm Reg))
404
-
405
- ;; Floating-point load, single-precision (32 bit).
406
- (FpuLoad32
407
- (rd WritableReg)
408
- (mem AMode)
409
- (flags MemFlags))
410
-
411
- ;; Floating-point store, single-precision (32 bit).
412
- (FpuStore32
413
- (rd Reg)
414
- (mem AMode)
415
- (flags MemFlags))
416
-
417
- ;; Floating-point load, double-precision (64 bit).
418
- (FpuLoad64
419
- (rd WritableReg)
420
- (mem AMode)
421
- (flags MemFlags))
422
-
423
- ;; Floating-point store, double-precision (64 bit).
424
- (FpuStore64
425
- (rd Reg)
426
- (mem AMode)
427
- (flags MemFlags))
428
-
429
- ;; Floating-point/vector load, 128 bit.
430
- (FpuLoad128
431
- (rd WritableReg)
432
- (mem AMode)
433
- (flags MemFlags))
434
-
435
- ;; Floating-point/vector store, 128 bit.
436
- (FpuStore128
437
- (rd Reg)
438
- (mem AMode)
439
- (flags MemFlags))
440
-
441
- ;; A load of a pair of floating-point registers, double precision (64-bit).
442
- (FpuLoadP64
443
- (rt WritableReg)
444
- (rt2 WritableReg)
445
- (mem PairAMode)
446
- (flags MemFlags))
447
-
448
- ;; A store of a pair of floating-point registers, double precision (64-bit).
449
- (FpuStoreP64
450
- (rt Reg)
451
- (rt2 Reg)
452
- (mem PairAMode)
453
- (flags MemFlags))
454
-
455
- ;; A load of a pair of floating-point registers, 128-bit.
456
- (FpuLoadP128
457
- (rt WritableReg)
458
- (rt2 WritableReg)
459
- (mem PairAMode)
460
- (flags MemFlags))
461
-
462
- ;; A store of a pair of floating-point registers, 128-bit.
463
- (FpuStoreP128
464
- (rt Reg)
465
- (rt2 Reg)
466
- (mem PairAMode)
467
- (flags MemFlags))
468
-
469
- ;; Conversion: FP -> integer.
470
- (FpuToInt
471
- (op FpuToIntOp)
472
- (rd WritableReg)
473
- (rn Reg))
474
-
475
- ;; Conversion: integer -> FP.
476
- (IntToFpu
477
- (op IntToFpuOp)
478
- (rd WritableReg)
479
- (rn Reg))
480
-
481
- ;; FP conditional select, 32 bit.
482
- (FpuCSel32
483
- (rd WritableReg)
484
- (rn Reg)
485
- (rm Reg)
486
- (cond Cond))
487
-
488
- ;; FP conditional select, 64 bit.
489
- (FpuCSel64
490
- (rd WritableReg)
491
- (rn Reg)
492
- (rm Reg)
493
- (cond Cond))
494
-
495
- ;; Round to integer.
496
- (FpuRound
497
- (op FpuRoundMode)
498
- (rd WritableReg)
499
- (rn Reg))
500
-
501
- ;; Move from a GPR to a vector register. The scalar value is parked in the lowest lane
502
- ;; of the destination, and all other lanes are zeroed out. Currently only 32- and 64-bit
503
- ;; transactions are supported.
504
- (MovToFpu
505
- (rd WritableReg)
506
- (rn Reg)
507
- (size ScalarSize))
508
-
509
- ;; Loads a floating-point immediate.
510
- (FpuMoveFPImm
511
- (rd WritableReg)
512
- (imm ASIMDFPModImm)
513
- (size ScalarSize))
514
-
515
- ;; Move to a vector element from a GPR.
516
- (MovToVec
517
- (rd WritableReg)
518
- (ri Reg)
519
- (rn Reg)
520
- (idx u8)
521
- (size VectorSize))
522
-
523
- ;; Unsigned move from a vector element to a GPR.
524
- (MovFromVec
525
- (rd WritableReg)
526
- (rn Reg)
527
- (idx u8)
528
- (size ScalarSize))
529
-
530
- ;; Signed move from a vector element to a GPR.
531
- (MovFromVecSigned
532
- (rd WritableReg)
533
- (rn Reg)
534
- (idx u8)
535
- (size VectorSize)
536
- (scalar_size OperandSize))
537
-
538
- ;; Duplicate general-purpose register to vector.
539
- (VecDup
540
- (rd WritableReg)
541
- (rn Reg)
542
- (size VectorSize))
543
-
544
- ;; Duplicate scalar to vector.
545
- (VecDupFromFpu
546
- (rd WritableReg)
547
- (rn Reg)
548
- (size VectorSize)
549
- (lane u8))
550
-
551
- ;; Duplicate FP immediate to vector.
552
- (VecDupFPImm
553
- (rd WritableReg)
554
- (imm ASIMDFPModImm)
555
- (size VectorSize))
556
-
557
- ;; Duplicate immediate to vector.
558
- (VecDupImm
559
- (rd WritableReg)
560
- (imm ASIMDMovModImm)
561
- (invert bool)
562
- (size VectorSize))
563
-
564
- ;; Vector extend.
565
- (VecExtend
566
- (t VecExtendOp)
567
- (rd WritableReg)
568
- (rn Reg)
569
- (high_half bool)
570
- (lane_size ScalarSize))
571
-
572
- ;; Move vector element to another vector element.
573
- (VecMovElement
574
- (rd WritableReg)
575
- (ri Reg)
576
- (rn Reg)
577
- (dest_idx u8)
578
- (src_idx u8)
579
- (size VectorSize))
580
-
581
- ;; Vector widening operation.
582
- (VecRRLong
583
- (op VecRRLongOp)
584
- (rd WritableReg)
585
- (rn Reg)
586
- (high_half bool))
587
-
588
- ;; Vector narrowing operation -- low half.
589
- (VecRRNarrowLow
590
- (op VecRRNarrowOp)
591
- (rd WritableReg)
592
- (rn Reg)
593
- (lane_size ScalarSize))
594
-
595
- ;; Vector narrowing operation -- high half.
596
- (VecRRNarrowHigh
597
- (op VecRRNarrowOp)
598
- (rd WritableReg)
599
- (ri Reg)
600
- (rn Reg)
601
- (lane_size ScalarSize))
602
-
603
- ;; 1-operand vector instruction that operates on a pair of elements.
604
- (VecRRPair
605
- (op VecPairOp)
606
- (rd WritableReg)
607
- (rn Reg))
608
-
609
- ;; 2-operand vector instruction that produces a result with twice the
610
- ;; lane width and half the number of lanes.
611
- (VecRRRLong
612
- (alu_op VecRRRLongOp)
613
- (rd WritableReg)
614
- (rn Reg)
615
- (rm Reg)
616
- (high_half bool))
617
-
618
- ;; 2-operand vector instruction that produces a result with
619
- ;; twice the lane width and half the number of lanes. Variant
620
- ;; that modifies `rd` (so takes its initial state as `ri`).
621
- (VecRRRLongMod
622
- (alu_op VecRRRLongModOp)
623
- (rd WritableReg)
624
- (ri Reg)
625
- (rn Reg)
626
- (rm Reg)
627
- (high_half bool))
628
-
629
- ;; 1-operand vector instruction that extends elements of the input
630
- ;; register and operates on a pair of elements. The output lane width
631
- ;; is double that of the input.
632
- (VecRRPairLong
633
- (op VecRRPairLongOp)
634
- (rd WritableReg)
635
- (rn Reg))
636
-
637
- ;; A vector ALU op.
638
- (VecRRR
639
- (alu_op VecALUOp)
640
- (rd WritableReg)
641
- (rn Reg)
642
- (rm Reg)
643
- (size VectorSize))
644
-
645
- ;; A vector ALU op modifying a source register.
646
- (VecRRRMod
647
- (alu_op VecALUModOp)
648
- (rd WritableReg)
649
- (ri Reg)
650
- (rn Reg)
651
- (rm Reg)
652
- (size VectorSize))
653
-
654
- ;; A vector ALU op modifying a source register.
655
- (VecFmlaElem
656
- (alu_op VecALUModOp)
657
- (rd WritableReg)
658
- (ri Reg)
659
- (rn Reg)
660
- (rm Reg)
661
- (size VectorSize)
662
- (idx u8))
663
-
664
- ;; Vector two register miscellaneous instruction.
665
- (VecMisc
666
- (op VecMisc2)
667
- (rd WritableReg)
668
- (rn Reg)
669
- (size VectorSize))
670
-
671
- ;; Vector instruction across lanes.
672
- (VecLanes
673
- (op VecLanesOp)
674
- (rd WritableReg)
675
- (rn Reg)
676
- (size VectorSize))
677
-
678
- ;; Vector shift by immediate Shift Left (immediate), Unsigned Shift Right (immediate)
679
- ;; Signed Shift Right (immediate). These are somewhat unusual in that, for right shifts,
680
- ;; the allowed range of `imm` values is 1 to lane-size-in-bits, inclusive. A zero
681
- ;; right-shift cannot be encoded. Left shifts are "normal", though, having valid `imm`
682
- ;; values from 0 to lane-size-in-bits - 1 inclusive.
683
- (VecShiftImm
684
- (op VecShiftImmOp)
685
- (rd WritableReg)
686
- (rn Reg)
687
- (size VectorSize)
688
- (imm u8))
689
-
690
- ;; Destructive vector shift by immediate.
691
- (VecShiftImmMod
692
- (op VecShiftImmModOp)
693
- (rd WritableReg)
694
- (ri Reg)
695
- (rn Reg)
696
- (size VectorSize)
697
- (imm u8))
698
-
699
- ;; Vector extract - create a new vector, being the concatenation of the lowest `imm4` bytes
700
- ;; of `rm` followed by the uppermost `16 - imm4` bytes of `rn`.
701
- (VecExtract
702
- (rd WritableReg)
703
- (rn Reg)
704
- (rm Reg)
705
- (imm4 u8))
706
-
707
- ;; Table vector lookup - single register table. The table
708
- ;; consists of 8-bit elements and is stored in `rn`, while `rm`
709
- ;; contains 8-bit element indices. This variant emits `TBL`,
710
- ;; which sets elements that correspond to out-of-range indices
711
- ;; (greater than 15) to 0.
712
- (VecTbl
713
- (rd WritableReg)
714
- (rn Reg)
715
- (rm Reg))
716
-
717
- ;; Table vector lookup - single register table. The table
718
- ;; consists of 8-bit elements and is stored in `rn`, while `rm`
719
- ;; contains 8-bit element indices. This variant emits `TBX`,
720
- ;; which leaves elements that correspond to out-of-range indices
721
- ;; (greater than 15) unmodified. Hence, it takes an input vreg in
722
- ;; `ri` that is constrained to the same allocation as `rd`.
723
- (VecTblExt
724
- (rd WritableReg)
725
- (ri Reg)
726
- (rn Reg)
727
- (rm Reg))
728
-
729
- ;; Table vector lookup - two register table. The table consists
730
- ;; of 8-bit elements and is stored in `rn` and `rn2`, while
731
- ;; `rm` contains 8-bit element indices. The table registers
732
- ;; `rn` and `rn2` must have consecutive numbers modulo 32, that
733
- ;; is v31 and v0 (in that order) are consecutive registers.
734
- ;; This variant emits `TBL`, which sets out-of-range results to
735
- ;; 0.
736
- (VecTbl2
737
- (rd WritableReg)
738
- (rn Reg)
739
- (rn2 Reg)
740
- (rm Reg))
741
-
742
- ;; Table vector lookup - two register table. The table consists
743
- ;; of 8-bit elements and is stored in `rn` and `rn2`, while
744
- ;; `rm` contains 8-bit element indices. The table registers
745
- ;; `rn` and `rn2` must have consecutive numbers modulo 32, that
746
- ;; is v31 and v0 (in that order) are consecutive registers.
747
- ;; This variant emits `TBX`, which leaves out-of-range results
748
- ;; unmodified, hence takes the initial state of the result
749
- ;; register in vreg `ri`.
750
- (VecTbl2Ext
751
- (rd WritableReg)
752
- (ri Reg)
753
- (rn Reg)
754
- (rn2 Reg)
755
- (rm Reg))
756
-
757
- ;; Load an element and replicate to all lanes of a vector.
758
- (VecLoadReplicate
759
- (rd WritableReg)
760
- (rn Reg)
761
- (size VectorSize)
762
- (flags MemFlags))
763
-
764
- ;; Vector conditional select, 128 bit. A synthetic instruction, which generates a 4-insn
765
- ;; control-flow diamond.
766
- (VecCSel
767
- (rd WritableReg)
768
- (rn Reg)
769
- (rm Reg)
770
- (cond Cond))
771
-
772
- ;; Move to the NZCV flags (actually a `MSR NZCV, Xn` insn).
773
- (MovToNZCV
774
- (rn Reg))
775
-
776
- ;; Move from the NZCV flags (actually a `MRS Xn, NZCV` insn).
777
- (MovFromNZCV
778
- (rd WritableReg))
779
-
780
- ;; A machine call instruction. N.B.: this allows only a +/- 128MB offset (it uses a relocation
781
- ;; of type `Reloc::Arm64Call`); if the destination distance is not `RelocDistance::Near`, the
782
- ;; code should use a `LoadExtName` / `CallInd` sequence instead, allowing an arbitrary 64-bit
783
- ;; target.
784
- (Call
785
- (info BoxCallInfo))
786
-
787
- ;; A machine indirect-call instruction.
788
- (CallInd
789
- (info BoxCallIndInfo))
790
-
791
- ;; A return-call macro instruction.
792
- (ReturnCall
793
- (callee BoxExternalName)
794
- (info BoxReturnCallInfo))
795
-
796
- ;; An indirect return-call macro instruction.
797
- (ReturnCallInd
798
- (callee Reg)
799
- (info BoxReturnCallInfo))
800
-
801
- ;; A pseudo-instruction that captures register arguments in vregs.
802
- (Args
803
- (args VecArgPair))
804
-
805
- ;; A pseudo-instruction that moves vregs to return registers.
806
- (Rets
807
- (rets VecRetPair))
808
-
809
- ;; ---- branches (exactly one must appear at end of BB) ----
810
-
811
- ;; A machine return instruction.
812
- (Ret)
813
-
814
- ;; A machine return instruction with pointer authentication using SP as the
815
- ;; modifier. This instruction requires pointer authentication support
816
- ;; (FEAT_PAuth) unless `is_hint` is true, in which case it is equivalent to
817
- ;; the combination of a no-op and a return instruction on platforms without
818
- ;; the relevant support.
819
- (AuthenticatedRet
820
- (key APIKey)
821
- (is_hint bool))
822
-
823
- ;; An unconditional branch.
824
- (Jump
825
- (dest BranchTarget))
826
-
827
- ;; A conditional branch. Contains two targets; at emission time, both are emitted, but
828
- ;; the MachBuffer knows to truncate the trailing branch if fallthrough. We optimize the
829
- ;; choice of taken/not_taken (inverting the branch polarity as needed) based on the
830
- ;; fallthrough at the time of lowering.
831
- (CondBr
832
- (taken BranchTarget)
833
- (not_taken BranchTarget)
834
- (kind CondBrKind))
835
-
836
- ;; A conditional branch which tests the `bit` of `rn` and branches
837
- ;; depending on `kind`.
838
- (TestBitAndBranch
839
- (kind TestBitAndBranchKind)
840
- (taken BranchTarget)
841
- (not_taken BranchTarget)
842
- (rn Reg)
843
- (bit u8))
844
-
845
- ;; A conditional trap: execute a `udf` if the condition is true. This is
846
- ;; one VCode instruction because it uses embedded control flow; it is
847
- ;; logically a single-in, single-out region, but needs to appear as one
848
- ;; unit to the register allocator.
849
- ;;
850
- ;; The `CondBrKind` gives the conditional-branch condition that will
851
- ;; *execute* the embedded `Inst`. (In the emitted code, we use the inverse
852
- ;; of this condition in a branch that skips the trap instruction.)
853
- (TrapIf
854
- (kind CondBrKind)
855
- (trap_code TrapCode))
856
-
857
- ;; An indirect branch through a register, augmented with set of all
858
- ;; possible successors.
859
- (IndirectBr
860
- (rn Reg)
861
- (targets VecMachLabel))
862
-
863
- ;; A "break" instruction, used for e.g. traps and debug breakpoints.
864
- (Brk)
865
-
866
- ;; An instruction guaranteed to always be undefined and to trigger an illegal instruction at
867
- ;; runtime.
868
- (Udf
869
- (trap_code TrapCode))
870
-
871
- ;; Compute the address (using a PC-relative offset) of a memory location, using the `ADR`
872
- ;; instruction. Note that we take a simple offset, not a `MemLabel`, here, because `Adr` is
873
- ;; only used for now in fixed lowering sequences with hardcoded offsets. In the future we may
874
- ;; need full `MemLabel` support.
875
- (Adr
876
- (rd WritableReg)
877
- ;; Offset in range -2^20 .. 2^20.
878
- (off i32))
879
-
880
- ;; Compute the address (using a PC-relative offset) of a 4KB page.
881
- (Adrp
882
- (rd WritableReg)
883
- (off i32))
884
-
885
- ;; Raw 32-bit word, used for inline constants and jump-table entries.
886
- (Word4
887
- (data u32))
888
-
889
- ;; Raw 64-bit word, used for inline constants.
890
- (Word8
891
- (data u64))
892
-
893
- ;; Jump-table sequence, as one compound instruction (see note in lower_inst.rs for rationale).
894
- (JTSequence
895
- (default MachLabel)
896
- (targets BoxVecMachLabel)
897
- (ridx Reg)
898
- (rtmp1 WritableReg)
899
- (rtmp2 WritableReg))
900
-
901
- ;; Load an inline symbol reference.
902
- (LoadExtName
903
- (rd WritableReg)
904
- (name BoxExternalName)
905
- (offset i64))
906
-
907
- ;; Load address referenced by `mem` into `rd`.
908
- (LoadAddr
909
- (rd WritableReg)
910
- (mem AMode))
911
-
912
- ;; Pointer authentication code for instruction address with modifier in SP;
913
- ;; equivalent to a no-op if Pointer authentication (FEAT_PAuth) is not
914
- ;; supported.
915
- (Paci
916
- (key APIKey))
917
-
918
- ;; Strip pointer authentication code from instruction address in LR;
919
- ;; equivalent to a no-op if Pointer authentication (FEAT_PAuth) is not
920
- ;; supported.
921
- (Xpaclri)
922
-
923
- ;; Branch target identification; equivalent to a no-op if Branch Target
924
- ;; Identification (FEAT_BTI) is not supported.
925
- (Bti
926
- (targets BranchTargetType))
927
-
928
- ;; Marker, no-op in generated code: SP "virtual offset" is adjusted. This
929
- ;; controls how AMode::NominalSPOffset args are lowered.
930
- (VirtualSPOffsetAdj
931
- (offset i64))
932
-
933
- ;; Meta-insn, no-op in generated code: emit constant/branch veneer island
934
- ;; at this point (with a guard jump around it) if less than the needed
935
- ;; space is available before the next branch deadline. See the `MachBuffer`
936
- ;; implementation in `machinst/buffer.rs` for the overall algorithm. In
937
- ;; brief, we retain a set of "pending/unresolved label references" from
938
- ;; branches as we scan forward through instructions to emit machine code;
939
- ;; if we notice we're about to go out of range on an unresolved reference,
940
- ;; we stop, emit a bunch of "veneers" (branches in a form that has a longer
941
- ;; range, e.g. a 26-bit-offset unconditional jump), and point the original
942
- ;; label references to those. This is an "island" because it comes in the
943
- ;; middle of the code.
944
- ;;
945
- ;; This meta-instruction is a necessary part of the logic that determines
946
- ;; where to place islands. Ordinarily, we want to place them between basic
947
- ;; blocks, so we compute the worst-case size of each block, and emit the
948
- ;; island before starting a block if we would exceed a deadline before the
949
- ;; end of the block. However, some sequences (such as an inline jumptable)
950
- ;; are variable-length and not accounted for by this logic; so these
951
- ;; lowered sequences include an `EmitIsland` to trigger island generation
952
- ;; where necessary.
953
- (EmitIsland
954
- ;; The needed space before the next deadline.
955
- (needed_space CodeOffset))
956
-
957
- ;; A call to the `ElfTlsGetAddr` libcall. Returns address of TLS symbol in x0.
958
- (ElfTlsGetAddr
959
- (symbol BoxExternalName)
960
- (rd WritableReg)
961
- (tmp WritableReg))
962
-
963
- (MachOTlsGetAddr
964
- (symbol ExternalName)
965
- (rd WritableReg))
966
-
967
- ;; An unwind pseudo-instruction.
968
- (Unwind
969
- (inst UnwindInst))
970
-
971
- ;; A dummy use, useful to keep a value alive.
972
- (DummyUse
973
- (reg Reg))
974
-
975
- ;; Emits an inline stack probe loop.
976
- ;;
977
- ;; Note that this is emitted post-regalloc so `start` and `end` can be
978
- ;; temporary registers such as the spilltmp and tmp2 registers. This also
979
- ;; means that the internal codegen can't use these registers.
980
- (StackProbeLoop (start WritableReg)
981
- (end Reg)
982
- (step Imm12))))
983
-
984
- ;; An ALU operation. This can be paired with several instruction formats
985
- ;; below (see `Inst`) in any combination.
986
- (type ALUOp
987
- (enum
988
- (Add)
989
- (Sub)
990
- (Orr)
991
- (OrrNot)
992
- (And)
993
- (AndS)
994
- (AndNot)
995
- ;; XOR (AArch64 calls this "EOR")
996
- (Eor)
997
- ;; XNOR (AArch64 calls this "EOR-NOT")
998
- (EorNot)
999
- ;; Add, setting flags
1000
- (AddS)
1001
- ;; Sub, setting flags
1002
- (SubS)
1003
- ;; Signed multiply, high-word result
1004
- (SMulH)
1005
- ;; Unsigned multiply, high-word result
1006
- (UMulH)
1007
- (SDiv)
1008
- (UDiv)
1009
- (RotR)
1010
- (Lsr)
1011
- (Asr)
1012
- (Lsl)
1013
- ;; Add with carry
1014
- (Adc)
1015
- ;; Add with carry, settings flags
1016
- (AdcS)
1017
- ;; Subtract with carry
1018
- (Sbc)
1019
- ;; Subtract with carry, settings flags
1020
- (SbcS)
1021
- ))
1022
-
1023
- ;; An ALU operation with three arguments.
1024
- (type ALUOp3
1025
- (enum
1026
- ;; Multiply-add
1027
- (MAdd)
1028
- ;; Multiply-sub
1029
- (MSub)
1030
- ;; Unsigned-Multiply-add
1031
- (UMAddL)
1032
- ;; Signed-Multiply-add
1033
- (SMAddL)
1034
- ))
1035
-
1036
- (type MoveWideOp
1037
- (enum
1038
- (MovZ)
1039
- (MovN)
1040
- ))
1041
-
1042
- (type UImm5 (primitive UImm5))
1043
- (type Imm12 (primitive Imm12))
1044
- (type ImmLogic (primitive ImmLogic))
1045
- (type ImmShift (primitive ImmShift))
1046
- (type ShiftOpAndAmt (primitive ShiftOpAndAmt))
1047
- (type MoveWideConst (primitive MoveWideConst))
1048
- (type NZCV (primitive NZCV))
1049
- (type ASIMDFPModImm (primitive ASIMDFPModImm))
1050
- (type ASIMDMovModImm (primitive ASIMDMovModImm))
1051
- (type SImm7Scaled (primitive SImm7Scaled))
1052
-
1053
- (type BoxCallInfo (primitive BoxCallInfo))
1054
- (type BoxCallIndInfo (primitive BoxCallIndInfo))
1055
- (type BoxReturnCallInfo (primitive BoxReturnCallInfo))
1056
- (type CondBrKind (primitive CondBrKind))
1057
- (type BranchTarget (primitive BranchTarget))
1058
- (type BoxJTSequenceInfo (primitive BoxJTSequenceInfo))
1059
- (type CodeOffset (primitive CodeOffset))
1060
- (type VecMachLabel extern (enum))
1061
-
1062
- (type ExtendOp extern
1063
- (enum
1064
- (UXTB)
1065
- (UXTH)
1066
- (UXTW)
1067
- (UXTX)
1068
- (SXTB)
1069
- (SXTH)
1070
- (SXTW)
1071
- (SXTX)
1072
- ))
1073
-
1074
- ;; An operation on the bits of a register. This can be paired with several instruction formats
1075
- ;; below (see `Inst`) in any combination.
1076
- (type BitOp
1077
- (enum
1078
- ;; Bit reverse
1079
- (RBit)
1080
- (Clz)
1081
- (Cls)
1082
- ;; Byte reverse
1083
- (Rev16)
1084
- (Rev32)
1085
- (Rev64)
1086
- ))
1087
-
1088
- (type MemLabel extern (enum))
1089
- (type SImm9 extern (enum))
1090
- (type UImm12Scaled extern (enum))
1091
-
1092
- ;; An addressing mode specified for a load/store operation.
1093
- (type AMode
1094
- (enum
1095
- ;;
1096
- ;; Real ARM64 addressing modes:
1097
- ;;
1098
- ;; "post-indexed" mode as per AArch64 docs: postincrement reg after
1099
- ;; address computation.
1100
- ;; Specialized here to SP so we don't have to emit regalloc metadata.
1101
- (SPPostIndexed
1102
- (simm9 SImm9))
1103
-
1104
- ;; "pre-indexed" mode as per AArch64 docs: preincrement reg before
1105
- ;; address computation.
1106
- ;; Specialized here to SP so we don't have to emit regalloc metadata.
1107
- (SPPreIndexed
1108
- (simm9 SImm9))
1109
-
1110
- ;; N.B.: RegReg, RegScaled, and RegScaledExtended all correspond to
1111
- ;; what the ISA calls the "register offset" addressing mode. We split
1112
- ;; out several options here for more ergonomic codegen.
1113
- ;;
1114
- ;; Register plus register offset.
1115
- (RegReg
1116
- (rn Reg)
1117
- (rm Reg))
1118
-
1119
- ;; Register plus register offset, scaled by type's size.
1120
- (RegScaled
1121
- (rn Reg)
1122
- (rm Reg)
1123
- (ty Type))
1124
-
1125
- ;; Register plus register offset, scaled by type's size, with index
1126
- ;; sign- or zero-extended first.
1127
- (RegScaledExtended
1128
- (rn Reg)
1129
- (rm Reg)
1130
- (ty Type)
1131
- (extendop ExtendOp))
1132
-
1133
- ;; Register plus register offset, with index sign- or zero-extended
1134
- ;; first.
1135
- (RegExtended
1136
- (rn Reg)
1137
- (rm Reg)
1138
- (extendop ExtendOp))
1139
-
1140
- ;; Unscaled signed 9-bit immediate offset from reg.
1141
- (Unscaled
1142
- (rn Reg)
1143
- (simm9 SImm9))
1144
-
1145
- ;; Scaled (by size of a type) unsigned 12-bit immediate offset from reg.
1146
- (UnsignedOffset
1147
- (rn Reg)
1148
- (uimm12 UImm12Scaled))
1149
-
1150
- ;; virtual addressing modes that are lowered at emission time:
1151
- ;;
1152
- ;; Reference to a "label": e.g., a symbol.
1153
- (Label
1154
- (label MemLabel))
1155
-
1156
- ;; Arbitrary offset from a register. Converted to generation of large
1157
- ;; offsets with multiple instructions as necessary during code emission.
1158
- (RegOffset
1159
- (rn Reg)
1160
- (off i64)
1161
- (ty Type))
1162
-
1163
- ;; Offset from the stack pointer.
1164
- (SPOffset
1165
- (off i64)
1166
- (ty Type))
1167
-
1168
- ;; Offset from the frame pointer.
1169
- (FPOffset
1170
- (off i64)
1171
- (ty Type))
1172
-
1173
- ;; A reference to a constant which is placed outside of the function's
1174
- ;; body, typically at the end.
1175
- (Const
1176
- (addr VCodeConstant))
1177
-
1178
- ;; Offset from the "nominal stack pointer", which is where the real SP is
1179
- ;; just after stack and spill slots are allocated in the function prologue.
1180
- ;; At emission time, this is converted to `SPOffset` with a fixup added to
1181
- ;; the offset constant. The fixup is a running value that is tracked as
1182
- ;; emission iterates through instructions in linear order, and can be
1183
- ;; adjusted up and down with [Inst::VirtualSPOffsetAdj].
1184
- ;;
1185
- ;; The standard ABI is in charge of handling this (by emitting the
1186
- ;; adjustment meta-instructions). It maintains the invariant that "nominal
1187
- ;; SP" is where the actual SP is after the function prologue and before
1188
- ;; clobber pushes. See the diagram in the documentation for
1189
- ;; [crate::isa::aarch64::abi](the ABI module) for more details.
1190
- (NominalSPOffset
1191
- (off i64)
1192
- (ty Type))))
1193
-
1194
- ;; A memory argument to a load/store-pair.
1195
- (type PairAMode (enum
1196
- ;; Signed, scaled 7-bit offset from a register.
1197
- (SignedOffset
1198
- (reg Reg)
1199
- (simm7 SImm7Scaled))
1200
-
1201
- ;; Pre-increment register before address computation.
1202
- (SPPreIndexed (simm7 SImm7Scaled))
1203
-
1204
- ;; Post-increment register after address computation.
1205
- (SPPostIndexed (simm7 SImm7Scaled))
1206
- ))
1207
-
1208
- (type FPUOpRI extern (enum))
1209
- (type FPUOpRIMod extern (enum))
1210
-
1211
- (type OperandSize extern
1212
- (enum Size32
1213
- Size64))
1214
-
1215
- (type TestBitAndBranchKind (enum (Z) (NZ)))
1216
-
1217
- ;; Helper for calculating the `OperandSize` corresponding to a type
1218
- (decl operand_size (Type) OperandSize)
1219
- (rule 1 (operand_size (fits_in_32 _ty)) (OperandSize.Size32))
1220
- (rule (operand_size (fits_in_64 _ty)) (OperandSize.Size64))
1221
-
1222
- (type ScalarSize extern
1223
- (enum Size8
1224
- Size16
1225
- Size32
1226
- Size64
1227
- Size128))
1228
-
1229
- ;; Helper for calculating the `ScalarSize` corresponding to a type
1230
- (decl scalar_size (Type) ScalarSize)
1231
-
1232
- (rule (scalar_size $I8) (ScalarSize.Size8))
1233
- (rule (scalar_size $I16) (ScalarSize.Size16))
1234
- (rule (scalar_size $I32) (ScalarSize.Size32))
1235
- (rule (scalar_size $I64) (ScalarSize.Size64))
1236
- (rule (scalar_size $I128) (ScalarSize.Size128))
1237
-
1238
- (rule (scalar_size $F32) (ScalarSize.Size32))
1239
- (rule (scalar_size $F64) (ScalarSize.Size64))
1240
-
1241
- ;; Helper for calculating the `ScalarSize` lane type from vector type
1242
- (decl lane_size (Type) ScalarSize)
1243
- (rule 1 (lane_size (multi_lane 8 _)) (ScalarSize.Size8))
1244
- (rule 1 (lane_size (multi_lane 16 _)) (ScalarSize.Size16))
1245
- (rule 1 (lane_size (multi_lane 32 _)) (ScalarSize.Size32))
1246
- (rule 1 (lane_size (multi_lane 64 _)) (ScalarSize.Size64))
1247
- (rule (lane_size (dynamic_lane 8 _)) (ScalarSize.Size8))
1248
- (rule (lane_size (dynamic_lane 16 _)) (ScalarSize.Size16))
1249
- (rule (lane_size (dynamic_lane 32 _)) (ScalarSize.Size32))
1250
- (rule (lane_size (dynamic_lane 64 _)) (ScalarSize.Size64))
1251
-
1252
- ;; Helper for extracting the size of a lane from the input `VectorSize`
1253
- (decl pure vector_lane_size (VectorSize) ScalarSize)
1254
- (rule (vector_lane_size (VectorSize.Size8x16)) (ScalarSize.Size8))
1255
- (rule (vector_lane_size (VectorSize.Size8x8)) (ScalarSize.Size8))
1256
- (rule (vector_lane_size (VectorSize.Size16x8)) (ScalarSize.Size16))
1257
- (rule (vector_lane_size (VectorSize.Size16x4)) (ScalarSize.Size16))
1258
- (rule (vector_lane_size (VectorSize.Size32x4)) (ScalarSize.Size32))
1259
- (rule (vector_lane_size (VectorSize.Size32x2)) (ScalarSize.Size32))
1260
- (rule (vector_lane_size (VectorSize.Size64x2)) (ScalarSize.Size64))
1261
-
1262
- (type Cond extern
1263
- (enum
1264
- (Eq)
1265
- (Ne)
1266
- (Hs)
1267
- (Lo)
1268
- (Mi)
1269
- (Pl)
1270
- (Vs)
1271
- (Vc)
1272
- (Hi)
1273
- (Ls)
1274
- (Ge)
1275
- (Lt)
1276
- (Gt)
1277
- (Le)
1278
- (Al)
1279
- (Nv)
1280
- ))
1281
-
1282
- (type VectorSize extern
1283
- (enum
1284
- (Size8x8)
1285
- (Size8x16)
1286
- (Size16x4)
1287
- (Size16x8)
1288
- (Size32x2)
1289
- (Size32x4)
1290
- (Size64x2)
1291
- ))
1292
-
1293
- ;; Helper for calculating the `VectorSize` corresponding to a type
1294
- (decl vector_size (Type) VectorSize)
1295
- (rule 1 (vector_size (multi_lane 8 8)) (VectorSize.Size8x8))
1296
- (rule 1 (vector_size (multi_lane 8 16)) (VectorSize.Size8x16))
1297
- (rule 1 (vector_size (multi_lane 16 4)) (VectorSize.Size16x4))
1298
- (rule 1 (vector_size (multi_lane 16 8)) (VectorSize.Size16x8))
1299
- (rule 1 (vector_size (multi_lane 32 2)) (VectorSize.Size32x2))
1300
- (rule 1 (vector_size (multi_lane 32 4)) (VectorSize.Size32x4))
1301
- (rule 1 (vector_size (multi_lane 64 2)) (VectorSize.Size64x2))
1302
- (rule (vector_size (dynamic_lane 8 8)) (VectorSize.Size8x8))
1303
- (rule (vector_size (dynamic_lane 8 16)) (VectorSize.Size8x16))
1304
- (rule (vector_size (dynamic_lane 16 4)) (VectorSize.Size16x4))
1305
- (rule (vector_size (dynamic_lane 16 8)) (VectorSize.Size16x8))
1306
- (rule (vector_size (dynamic_lane 32 2)) (VectorSize.Size32x2))
1307
- (rule (vector_size (dynamic_lane 32 4)) (VectorSize.Size32x4))
1308
- (rule (vector_size (dynamic_lane 64 2)) (VectorSize.Size64x2))
1309
-
1310
- ;; A floating-point unit (FPU) operation with one arg.
1311
- (type FPUOp1
1312
- (enum
1313
- (Abs)
1314
- (Neg)
1315
- (Sqrt)
1316
- (Cvt32To64)
1317
- (Cvt64To32)
1318
- ))
1319
-
1320
- ;; A floating-point unit (FPU) operation with two args.
1321
- (type FPUOp2
1322
- (enum
1323
- (Add)
1324
- (Sub)
1325
- (Mul)
1326
- (Div)
1327
- (Max)
1328
- (Min)
1329
- ))
1330
-
1331
- ;; A floating-point unit (FPU) operation with three args.
1332
- (type FPUOp3
1333
- (enum
1334
- (MAdd)
1335
- ))
1336
-
1337
- ;; A conversion from an FP to an integer value.
1338
- (type FpuToIntOp
1339
- (enum
1340
- (F32ToU32)
1341
- (F32ToI32)
1342
- (F32ToU64)
1343
- (F32ToI64)
1344
- (F64ToU32)
1345
- (F64ToI32)
1346
- (F64ToU64)
1347
- (F64ToI64)
1348
- ))
1349
-
1350
- ;; A conversion from an integer to an FP value.
1351
- (type IntToFpuOp
1352
- (enum
1353
- (U32ToF32)
1354
- (I32ToF32)
1355
- (U32ToF64)
1356
- (I32ToF64)
1357
- (U64ToF32)
1358
- (I64ToF32)
1359
- (U64ToF64)
1360
- (I64ToF64)
1361
- ))
1362
-
1363
- ;; Modes for FP rounding ops: round down (floor) or up (ceil), or toward zero (trunc), or to
1364
- ;; nearest, and for 32- or 64-bit FP values.
1365
- (type FpuRoundMode
1366
- (enum
1367
- (Minus32)
1368
- (Minus64)
1369
- (Plus32)
1370
- (Plus64)
1371
- (Zero32)
1372
- (Zero64)
1373
- (Nearest32)
1374
- (Nearest64)
1375
- ))
1376
-
1377
- ;; Type of vector element extensions.
1378
- (type VecExtendOp
1379
- (enum
1380
- ;; Signed extension
1381
- (Sxtl)
1382
- ;; Unsigned extension
1383
- (Uxtl)
1384
- ))
1385
-
1386
- ;; A vector ALU operation.
1387
- (type VecALUOp
1388
- (enum
1389
- ;; Signed saturating add
1390
- (Sqadd)
1391
- ;; Unsigned saturating add
1392
- (Uqadd)
1393
- ;; Signed saturating subtract
1394
- (Sqsub)
1395
- ;; Unsigned saturating subtract
1396
- (Uqsub)
1397
- ;; Compare bitwise equal
1398
- (Cmeq)
1399
- ;; Compare signed greater than or equal
1400
- (Cmge)
1401
- ;; Compare signed greater than
1402
- (Cmgt)
1403
- ;; Compare unsigned higher
1404
- (Cmhs)
1405
- ;; Compare unsigned higher or same
1406
- (Cmhi)
1407
- ;; Floating-point compare equal
1408
- (Fcmeq)
1409
- ;; Floating-point compare greater than
1410
- (Fcmgt)
1411
- ;; Floating-point compare greater than or equal
1412
- (Fcmge)
1413
- ;; Bitwise and
1414
- (And)
1415
- ;; Bitwise bit clear
1416
- (Bic)
1417
- ;; Bitwise inclusive or
1418
- (Orr)
1419
- ;; Bitwise exclusive or
1420
- (Eor)
1421
- ;; Unsigned maximum pairwise
1422
- (Umaxp)
1423
- ;; Add
1424
- (Add)
1425
- ;; Subtract
1426
- (Sub)
1427
- ;; Multiply
1428
- (Mul)
1429
- ;; Signed shift left
1430
- (Sshl)
1431
- ;; Unsigned shift left
1432
- (Ushl)
1433
- ;; Unsigned minimum
1434
- (Umin)
1435
- ;; Signed minimum
1436
- (Smin)
1437
- ;; Unsigned maximum
1438
- (Umax)
1439
- ;; Signed maximum
1440
- (Smax)
1441
- ;; Unsigned rounding halving add
1442
- (Urhadd)
1443
- ;; Floating-point add
1444
- (Fadd)
1445
- ;; Floating-point subtract
1446
- (Fsub)
1447
- ;; Floating-point divide
1448
- (Fdiv)
1449
- ;; Floating-point maximum
1450
- (Fmax)
1451
- ;; Floating-point minimum
1452
- (Fmin)
1453
- ;; Floating-point multiply
1454
- (Fmul)
1455
- ;; Add pairwise
1456
- (Addp)
1457
- ;; Zip vectors (primary) [meaning, high halves]
1458
- (Zip1)
1459
- ;; Zip vectors (secondary)
1460
- (Zip2)
1461
- ;; Signed saturating rounding doubling multiply returning high half
1462
- (Sqrdmulh)
1463
- ;; Unzip vectors (primary)
1464
- (Uzp1)
1465
- ;; Unzip vectors (secondary)
1466
- (Uzp2)
1467
- ;; Transpose vectors (primary)
1468
- (Trn1)
1469
- ;; Transpose vectors (secondary)
1470
- (Trn2)
1471
- ))
1472
-
1473
- ;; A Vector ALU operation which modifies a source register.
1474
- (type VecALUModOp
1475
- (enum
1476
- ;; Bitwise select
1477
- (Bsl)
1478
- ;; Floating-point fused multiply-add vectors
1479
- (Fmla)
1480
- ;; Floating-point fused multiply-subtract vectors
1481
- (Fmls)
1482
- ))
1483
-
1484
- ;; A Vector miscellaneous operation with two registers.
1485
- (type VecMisc2
1486
- (enum
1487
- ;; Bitwise NOT
1488
- (Not)
1489
- ;; Negate
1490
- (Neg)
1491
- ;; Absolute value
1492
- (Abs)
1493
- ;; Floating-point absolute value
1494
- (Fabs)
1495
- ;; Floating-point negate
1496
- (Fneg)
1497
- ;; Floating-point square root
1498
- (Fsqrt)
1499
- ;; Reverse elements in 16-bit lanes
1500
- (Rev16)
1501
- ;; Reverse elements in 32-bit lanes
1502
- (Rev32)
1503
- ;; Reverse elements in 64-bit doublewords
1504
- (Rev64)
1505
- ;; Floating-point convert to signed integer, rounding toward zero
1506
- (Fcvtzs)
1507
- ;; Floating-point convert to unsigned integer, rounding toward zero
1508
- (Fcvtzu)
1509
- ;; Signed integer convert to floating-point
1510
- (Scvtf)
1511
- ;; Unsigned integer convert to floating-point
1512
- (Ucvtf)
1513
- ;; Floating point round to integral, rounding towards nearest
1514
- (Frintn)
1515
- ;; Floating point round to integral, rounding towards zero
1516
- (Frintz)
1517
- ;; Floating point round to integral, rounding towards minus infinity
1518
- (Frintm)
1519
- ;; Floating point round to integral, rounding towards plus infinity
1520
- (Frintp)
1521
- ;; Population count per byte
1522
- (Cnt)
1523
- ;; Compare bitwise equal to 0
1524
- (Cmeq0)
1525
- ;; Compare signed greater than or equal to 0
1526
- (Cmge0)
1527
- ;; Compare signed greater than 0
1528
- (Cmgt0)
1529
- ;; Compare signed less than or equal to 0
1530
- (Cmle0)
1531
- ;; Compare signed less than 0
1532
- (Cmlt0)
1533
- ;; Floating point compare equal to 0
1534
- (Fcmeq0)
1535
- ;; Floating point compare greater than or equal to 0
1536
- (Fcmge0)
1537
- ;; Floating point compare greater than 0
1538
- (Fcmgt0)
1539
- ;; Floating point compare less than or equal to 0
1540
- (Fcmle0)
1541
- ;; Floating point compare less than 0
1542
- (Fcmlt0)
1543
- ))
1544
-
1545
- ;; A vector widening operation with one argument.
1546
- (type VecRRLongOp
1547
- (enum
1548
- ;; Floating-point convert to higher precision long, 16-bit elements
1549
- (Fcvtl16)
1550
- ;; Floating-point convert to higher precision long, 32-bit elements
1551
- (Fcvtl32)
1552
- ;; Shift left long (by element size), 8-bit elements
1553
- (Shll8)
1554
- ;; Shift left long (by element size), 16-bit elements
1555
- (Shll16)
1556
- ;; Shift left long (by element size), 32-bit elements
1557
- (Shll32)
1558
- ))
1559
-
1560
- ;; A vector narrowing operation with one argument.
1561
- (type VecRRNarrowOp
1562
- (enum
1563
- ;; Extract narrow.
1564
- (Xtn)
1565
- ;; Signed saturating extract narrow.
1566
- (Sqxtn)
1567
- ;; Signed saturating extract unsigned narrow.
1568
- (Sqxtun)
1569
- ;; Unsigned saturating extract narrow.
1570
- (Uqxtn)
1571
- ;; Floating-point convert to lower precision narrow.
1572
- (Fcvtn)
1573
- ))
1574
-
1575
- (type VecRRRLongOp
1576
- (enum
1577
- ;; Signed multiply long.
1578
- (Smull8)
1579
- (Smull16)
1580
- (Smull32)
1581
- ;; Unsigned multiply long.
1582
- (Umull8)
1583
- (Umull16)
1584
- (Umull32)
1585
- ))
1586
-
1587
- (type VecRRRLongModOp
1588
- (enum
1589
- ;; Unsigned multiply add long
1590
- (Umlal8)
1591
- (Umlal16)
1592
- (Umlal32)
1593
- ))
1594
-
1595
- ;; A vector operation on a pair of elements with one register.
1596
- (type VecPairOp
1597
- (enum
1598
- ;; Add pair of elements
1599
- (Addp)
1600
- ))
1601
-
1602
- ;; 1-operand vector instruction that extends elements of the input register
1603
- ;; and operates on a pair of elements.
1604
- (type VecRRPairLongOp
1605
- (enum
1606
- ;; Sign extend and add pair of elements
1607
- (Saddlp8)
1608
- (Saddlp16)
1609
- ;; Unsigned extend and add pair of elements
1610
- (Uaddlp8)
1611
- (Uaddlp16)
1612
- ))
1613
-
1614
- ;; An operation across the lanes of vectors.
1615
- (type VecLanesOp
1616
- (enum
1617
- ;; Integer addition across a vector
1618
- (Addv)
1619
- ;; Unsigned minimum across a vector
1620
- (Uminv)
1621
- ))
1622
-
1623
- ;; A shift-by-immediate operation on each lane of a vector.
1624
- (type VecShiftImmOp
1625
- (enum
1626
- ;; Unsigned shift left
1627
- (Shl)
1628
- ;; Unsigned shift right
1629
- (Ushr)
1630
- ;; Signed shift right
1631
- (Sshr)
1632
- ))
1633
-
1634
- ;; Destructive shift-by-immediate operation on each lane of a vector.
1635
- (type VecShiftImmModOp
1636
- (enum
1637
- ;; Shift left and insert
1638
- (Sli)
1639
- ))
1640
-
1641
- ;; Atomic read-modify-write operations with acquire-release semantics
1642
- (type AtomicRMWOp
1643
- (enum
1644
- (Add)
1645
- (Clr)
1646
- (Eor)
1647
- (Set)
1648
- (Smax)
1649
- (Smin)
1650
- (Umax)
1651
- (Umin)
1652
- (Swp)
1653
- ))
1654
-
1655
- ;; Atomic read-modify-write operations, with acquire-release semantics,
1656
- ;; implemented with a loop.
1657
- (type AtomicRMWLoopOp
1658
- (enum
1659
- (Add)
1660
- (Sub)
1661
- (And)
1662
- (Nand)
1663
- (Eor)
1664
- (Orr)
1665
- (Smax)
1666
- (Smin)
1667
- (Umax)
1668
- (Umin)
1669
- (Xchg)
1670
- ))
1671
-
1672
- ;; Keys for instruction address PACs
1673
- (type APIKey
1674
- (enum
1675
- ;; API key A with the modifier of SP
1676
- (ASP)
1677
- ;; API key B with the modifier of SP
1678
- (BSP)
1679
- ;; API key A with the modifier of zero
1680
- (AZ)
1681
- ;; API key B with the modifier of zero
1682
- (BZ)
1683
- ))
1684
-
1685
- ;; Branch target types
1686
- (type BranchTargetType
1687
- (enum
1688
- (None)
1689
- (C)
1690
- (J)
1691
- (JC)
1692
- ))
1693
-
1694
- ;; Extractors for target features ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1695
- (decl pure partial sign_return_address_disabled () Unit)
1696
- (extern constructor sign_return_address_disabled sign_return_address_disabled)
1697
-
1698
- (decl use_lse () Inst)
1699
- (extern extractor use_lse use_lse)
1700
-
1701
- ;; Extractor helpers for various immmediate constants ;;;;;;;;;;;;;;;;;;;;;;;;;;
1702
-
1703
- (decl pure partial move_wide_const_from_u64 (Type u64) MoveWideConst)
1704
- (extern constructor move_wide_const_from_u64 move_wide_const_from_u64)
1705
-
1706
- (decl pure partial move_wide_const_from_inverted_u64 (Type u64) MoveWideConst)
1707
- (extern constructor move_wide_const_from_inverted_u64 move_wide_const_from_inverted_u64)
1708
-
1709
- (decl pure partial imm_logic_from_u64 (Type u64) ImmLogic)
1710
- (extern constructor imm_logic_from_u64 imm_logic_from_u64)
1711
-
1712
- (decl pure partial imm_logic_from_imm64 (Type Imm64) ImmLogic)
1713
- (extern constructor imm_logic_from_imm64 imm_logic_from_imm64)
1714
-
1715
- (decl pure partial imm_shift_from_imm64 (Type Imm64) ImmShift)
1716
- (extern constructor imm_shift_from_imm64 imm_shift_from_imm64)
1717
-
1718
- (decl imm_shift_from_u8 (u8) ImmShift)
1719
- (extern constructor imm_shift_from_u8 imm_shift_from_u8)
1720
-
1721
- (decl imm12_from_u64 (Imm12) u64)
1722
- (extern extractor imm12_from_u64 imm12_from_u64)
1723
-
1724
- (decl u8_into_uimm5 (u8) UImm5)
1725
- (extern constructor u8_into_uimm5 u8_into_uimm5)
1726
-
1727
- (decl u8_into_imm12 (u8) Imm12)
1728
- (extern constructor u8_into_imm12 u8_into_imm12)
1729
-
1730
- (decl u64_into_imm_logic (Type u64) ImmLogic)
1731
- (extern constructor u64_into_imm_logic u64_into_imm_logic)
1732
-
1733
- (decl branch_target (MachLabel) BranchTarget)
1734
- (extern constructor branch_target branch_target)
1735
- (convert MachLabel BranchTarget branch_target)
1736
-
1737
- (decl targets_jt_space (BoxVecMachLabel) CodeOffset)
1738
- (extern constructor targets_jt_space targets_jt_space)
1739
-
1740
- ;; Calculate the minimum floating-point bound for a conversion to floating
1741
- ;; point from an integer type.
1742
- ;; Accepts whether the output is signed, the size of the input
1743
- ;; floating point type in bits, and the size of the output integer type
1744
- ;; in bits.
1745
- (decl min_fp_value (bool u8 u8) Reg)
1746
- (extern constructor min_fp_value min_fp_value)
1747
-
1748
- ;; Calculate the maximum floating-point bound for a conversion to floating
1749
- ;; point from an integer type.
1750
- ;; Accepts whether the output is signed, the size of the input
1751
- ;; floating point type in bits, and the size of the output integer type
1752
- ;; in bits.
1753
- (decl max_fp_value (bool u8 u8) Reg)
1754
- (extern constructor max_fp_value max_fp_value)
1755
-
1756
- ;; Constructs an FPUOpRI.Ushr* given the size in bits of the value (or lane)
1757
- ;; and the amount to shift by.
1758
- (decl fpu_op_ri_ushr (u8 u8) FPUOpRI)
1759
- (extern constructor fpu_op_ri_ushr fpu_op_ri_ushr)
1760
-
1761
- ;; Constructs an FPUOpRIMod.Sli* given the size in bits of the value (or lane)
1762
- ;; and the amount to shift by.
1763
- (decl fpu_op_ri_sli (u8 u8) FPUOpRIMod)
1764
- (extern constructor fpu_op_ri_sli fpu_op_ri_sli)
1765
-
1766
- (decl pure partial lshr_from_u64 (Type u64) ShiftOpAndAmt)
1767
- (extern constructor lshr_from_u64 lshr_from_u64)
1768
-
1769
- (decl pure partial lshl_from_imm64 (Type Imm64) ShiftOpAndAmt)
1770
- (extern constructor lshl_from_imm64 lshl_from_imm64)
1771
-
1772
- (decl pure partial lshl_from_u64 (Type u64) ShiftOpAndAmt)
1773
- (extern constructor lshl_from_u64 lshl_from_u64)
1774
-
1775
- (decl pure partial ashr_from_u64 (Type u64) ShiftOpAndAmt)
1776
- (extern constructor ashr_from_u64 ashr_from_u64)
1777
-
1778
- (decl integral_ty (Type) Type)
1779
- (extern extractor integral_ty integral_ty)
1780
-
1781
- (decl valid_atomic_transaction (Type) Type)
1782
- (extern extractor valid_atomic_transaction valid_atomic_transaction)
1783
-
1784
- (decl pure partial is_zero_simm9 (SImm9) Unit)
1785
- (extern constructor is_zero_simm9 is_zero_simm9)
1786
-
1787
- (decl pure partial is_zero_uimm12 (UImm12Scaled) Unit)
1788
- (extern constructor is_zero_uimm12 is_zero_uimm12)
1789
-
1790
- ;; Helper to go directly from a `Value`, when it's an `iconst`, to an `Imm12`.
1791
- (decl imm12_from_value (Imm12) Value)
1792
- (extractor
1793
- (imm12_from_value n)
1794
- (iconst (u64_from_imm64 (imm12_from_u64 n))))
1795
-
1796
- ;; Conceptually the same as `imm12_from_value`, but tries negating the constant
1797
- ;; value (first sign-extending to handle narrow widths).
1798
- (decl pure partial imm12_from_negated_value (Value) Imm12)
1799
- (rule
1800
- (imm12_from_negated_value (has_type ty (iconst n)))
1801
- (if-let (imm12_from_u64 imm) (i64_as_u64 (i64_neg (i64_sextend_imm64 ty n))))
1802
- imm)
1803
-
1804
- ;; Helper type to represent a value and an extend operation fused together.
1805
- (type ExtendedValue extern (enum))
1806
- (decl extended_value_from_value (ExtendedValue) Value)
1807
- (extern extractor extended_value_from_value extended_value_from_value)
1808
-
1809
- ;; Constructors used to poke at the fields of an `ExtendedValue`.
1810
- (decl put_extended_in_reg (ExtendedValue) Reg)
1811
- (extern constructor put_extended_in_reg put_extended_in_reg)
1812
- (decl get_extended_op (ExtendedValue) ExtendOp)
1813
- (extern constructor get_extended_op get_extended_op)
1814
-
1815
- (decl nzcv (bool bool bool bool) NZCV)
1816
- (extern constructor nzcv nzcv)
1817
-
1818
- (decl cond_br_zero (Reg) CondBrKind)
1819
- (extern constructor cond_br_zero cond_br_zero)
1820
-
1821
- (decl cond_br_not_zero (Reg) CondBrKind)
1822
- (extern constructor cond_br_not_zero cond_br_not_zero)
1823
-
1824
- (decl cond_br_cond (Cond) CondBrKind)
1825
- (extern constructor cond_br_cond cond_br_cond)
1826
-
1827
- ;; Instruction creation helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1828
-
1829
- ;; Helper for creating the zero register.
1830
- (decl zero_reg () Reg)
1831
- (extern constructor zero_reg zero_reg)
1832
-
1833
- (decl fp_reg () Reg)
1834
- (extern constructor fp_reg fp_reg)
1835
-
1836
- (decl stack_reg () Reg)
1837
- (extern constructor stack_reg stack_reg)
1838
-
1839
- (decl writable_link_reg () WritableReg)
1840
- (extern constructor writable_link_reg writable_link_reg)
1841
-
1842
- (decl writable_zero_reg () WritableReg)
1843
- (extern constructor writable_zero_reg writable_zero_reg)
1844
-
1845
- (decl value_regs_zero () ValueRegs)
1846
- (rule (value_regs_zero)
1847
- (value_regs
1848
- (imm $I64 (ImmExtend.Zero) 0)
1849
- (imm $I64 (ImmExtend.Zero) 0)))
1850
-
1851
-
1852
- ;; Helper for emitting `MInst.Mov` instructions.
1853
- (decl mov (Reg Type) Reg)
1854
- (rule (mov src ty)
1855
- (let ((dst WritableReg (temp_writable_reg $I64))
1856
- (_ Unit (emit (MInst.Mov (operand_size ty) dst src))))
1857
- dst))
1858
-
1859
- ;; Helper for emitting `MInst.MovZ` instructions.
1860
- (decl movz (MoveWideConst OperandSize) Reg)
1861
- (rule (movz imm size)
1862
- (let ((dst WritableReg (temp_writable_reg $I64))
1863
- (_ Unit (emit (MInst.MovWide (MoveWideOp.MovZ) dst imm size))))
1864
- dst))
1865
-
1866
- ;; Helper for emitting `MInst.MovN` instructions.
1867
- (decl movn (MoveWideConst OperandSize) Reg)
1868
- (rule (movn imm size)
1869
- (let ((dst WritableReg (temp_writable_reg $I64))
1870
- (_ Unit (emit (MInst.MovWide (MoveWideOp.MovN) dst imm size))))
1871
- dst))
1872
-
1873
- ;; Helper for emitting `MInst.AluRRImmLogic` instructions.
1874
- (decl alu_rr_imm_logic (ALUOp Type Reg ImmLogic) Reg)
1875
- (rule (alu_rr_imm_logic op ty src imm)
1876
- (let ((dst WritableReg (temp_writable_reg $I64))
1877
- (_ Unit (emit (MInst.AluRRImmLogic op (operand_size ty) dst src imm))))
1878
- dst))
1879
-
1880
- ;; Helper for emitting `MInst.AluRRImmShift` instructions.
1881
- (decl alu_rr_imm_shift (ALUOp Type Reg ImmShift) Reg)
1882
- (rule (alu_rr_imm_shift op ty src imm)
1883
- (let ((dst WritableReg (temp_writable_reg $I64))
1884
- (_ Unit (emit (MInst.AluRRImmShift op (operand_size ty) dst src imm))))
1885
- dst))
1886
-
1887
- ;; Helper for emitting `MInst.AluRRR` instructions.
1888
- (decl alu_rrr (ALUOp Type Reg Reg) Reg)
1889
- (rule (alu_rrr op ty src1 src2)
1890
- (let ((dst WritableReg (temp_writable_reg $I64))
1891
- (_ Unit (emit (MInst.AluRRR op (operand_size ty) dst src1 src2))))
1892
- dst))
1893
-
1894
- ;; Helper for emitting `MInst.VecRRR` instructions.
1895
- (decl vec_rrr (VecALUOp Reg Reg VectorSize) Reg)
1896
- (rule (vec_rrr op src1 src2 size)
1897
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1898
- (_ Unit (emit (MInst.VecRRR op dst src1 src2 size))))
1899
- dst))
1900
-
1901
- ;; Helper for emitting `MInst.FpuRR` instructions.
1902
- (decl fpu_rr (FPUOp1 Reg ScalarSize) Reg)
1903
- (rule (fpu_rr op src size)
1904
- (let ((dst WritableReg (temp_writable_reg $F64))
1905
- (_ Unit (emit (MInst.FpuRR op size dst src))))
1906
- dst))
1907
-
1908
- ;; Helper for emitting `MInst.VecRRRMod` instructions which use three registers,
1909
- ;; one of which is both source and output.
1910
- (decl vec_rrr_mod (VecALUModOp Reg Reg Reg VectorSize) Reg)
1911
- (rule (vec_rrr_mod op src1 src2 src3 size)
1912
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1913
- (_1 Unit (emit (MInst.VecRRRMod op dst src1 src2 src3 size))))
1914
- dst))
1915
-
1916
- ;; Helper for emitting `MInst.VecFmlaElem` instructions which use three registers,
1917
- ;; one of which is both source and output.
1918
- (decl vec_fmla_elem (VecALUModOp Reg Reg Reg VectorSize u8) Reg)
1919
- (rule (vec_fmla_elem op src1 src2 src3 size idx)
1920
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1921
- (_1 Unit (emit (MInst.VecFmlaElem op dst src1 src2 src3 size idx))))
1922
- dst))
1923
-
1924
- (decl fpu_rri (FPUOpRI Reg) Reg)
1925
- (rule (fpu_rri op src)
1926
- (let ((dst WritableReg (temp_writable_reg $F64))
1927
- (_ Unit (emit (MInst.FpuRRI op dst src))))
1928
- dst))
1929
-
1930
- (decl fpu_rri_mod (FPUOpRIMod Reg Reg) Reg)
1931
- (rule (fpu_rri_mod op dst_src src)
1932
- (let ((dst WritableReg (temp_writable_reg $F64))
1933
- (_ Unit (emit (MInst.FpuRRIMod op dst dst_src src))))
1934
- dst))
1935
-
1936
- ;; Helper for emitting `MInst.FpuRRR` instructions.
1937
- (decl fpu_rrr (FPUOp2 Reg Reg ScalarSize) Reg)
1938
- (rule (fpu_rrr op src1 src2 size)
1939
- (let ((dst WritableReg (temp_writable_reg $F64))
1940
- (_ Unit (emit (MInst.FpuRRR op size dst src1 src2))))
1941
- dst))
1942
-
1943
- ;; Helper for emitting `MInst.FpuRRRR` instructions.
1944
- (decl fpu_rrrr (FPUOp3 ScalarSize Reg Reg Reg) Reg)
1945
- (rule (fpu_rrrr size op src1 src2 src3)
1946
- (let ((dst WritableReg (temp_writable_reg $F64))
1947
- (_ Unit (emit (MInst.FpuRRRR size op dst src1 src2 src3))))
1948
- dst))
1949
-
1950
- ;; Helper for emitting `MInst.FpuCmp` instructions.
1951
- (decl fpu_cmp (ScalarSize Reg Reg) ProducesFlags)
1952
- (rule (fpu_cmp size rn rm)
1953
- (ProducesFlags.ProducesFlagsSideEffect
1954
- (MInst.FpuCmp size rn rm)))
1955
-
1956
- ;; Helper for emitting `MInst.VecLanes` instructions.
1957
- (decl vec_lanes (VecLanesOp Reg VectorSize) Reg)
1958
- (rule (vec_lanes op src size)
1959
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1960
- (_ Unit (emit (MInst.VecLanes op dst src size))))
1961
- dst))
1962
-
1963
- ;; Helper for emitting `MInst.VecShiftImm` instructions.
1964
- (decl vec_shift_imm (VecShiftImmOp u8 Reg VectorSize) Reg)
1965
- (rule (vec_shift_imm op imm src size)
1966
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1967
- (_ Unit (emit (MInst.VecShiftImm op dst src size imm))))
1968
- dst))
1969
-
1970
- ;; Helper for emitting `MInst.VecDup` instructions.
1971
- (decl vec_dup (Reg VectorSize) Reg)
1972
- (rule (vec_dup src size)
1973
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1974
- (_ Unit (emit (MInst.VecDup dst src size))))
1975
- dst))
1976
-
1977
- ;; Helper for emitting `MInst.VecDupFromFpu` instructions.
1978
- (decl vec_dup_from_fpu (Reg VectorSize u8) Reg)
1979
- (rule (vec_dup_from_fpu src size lane)
1980
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1981
- (_ Unit (emit (MInst.VecDupFromFpu dst src size lane))))
1982
- dst))
1983
-
1984
- ;; Helper for emitting `MInst.VecDupImm` instructions.
1985
- (decl vec_dup_imm (ASIMDMovModImm bool VectorSize) Reg)
1986
- (rule (vec_dup_imm imm invert size)
1987
- (let ((dst WritableReg (temp_writable_reg $I8X16))
1988
- (_ Unit (emit (MInst.VecDupImm dst imm invert size))))
1989
- dst))
1990
-
1991
- ;; Helper for emitting `MInst.AluRRImm12` instructions.
1992
- (decl alu_rr_imm12 (ALUOp Type Reg Imm12) Reg)
1993
- (rule (alu_rr_imm12 op ty src imm)
1994
- (let ((dst WritableReg (temp_writable_reg $I64))
1995
- (_ Unit (emit (MInst.AluRRImm12 op (operand_size ty) dst src imm))))
1996
- dst))
1997
-
1998
- ;; Helper for emitting `MInst.AluRRRShift` instructions.
1999
- (decl alu_rrr_shift (ALUOp Type Reg Reg ShiftOpAndAmt) Reg)
2000
- (rule (alu_rrr_shift op ty src1 src2 shift)
2001
- (let ((dst WritableReg (temp_writable_reg $I64))
2002
- (_ Unit (emit (MInst.AluRRRShift op (operand_size ty) dst src1 src2 shift))))
2003
- dst))
2004
-
2005
- ;; Helper for emitting `cmp` instructions, setting flags, with a right-shifted
2006
- ;; second operand register.
2007
- (decl cmp_rr_shift (OperandSize Reg Reg u64) ProducesFlags)
2008
- (rule (cmp_rr_shift size src1 src2 shift_amount)
2009
- (if-let shift (lshr_from_u64 $I64 shift_amount))
2010
- (ProducesFlags.ProducesFlagsSideEffect
2011
- (MInst.AluRRRShift (ALUOp.SubS) size (writable_zero_reg)
2012
- src1 src2 shift)))
2013
-
2014
- ;; Helper for emitting `cmp` instructions, setting flags, with an arithmetic right-shifted
2015
- ;; second operand register.
2016
- (decl cmp_rr_shift_asr (OperandSize Reg Reg u64) ProducesFlags)
2017
- (rule (cmp_rr_shift_asr size src1 src2 shift_amount)
2018
- (if-let shift (ashr_from_u64 $I64 shift_amount))
2019
- (ProducesFlags.ProducesFlagsSideEffect
2020
- (MInst.AluRRRShift (ALUOp.SubS) size (writable_zero_reg)
2021
- src1 src2 shift)))
2022
-
2023
- ;; Helper for emitting `MInst.AluRRRExtend` instructions.
2024
- (decl alu_rrr_extend (ALUOp Type Reg Reg ExtendOp) Reg)
2025
- (rule (alu_rrr_extend op ty src1 src2 extend)
2026
- (let ((dst WritableReg (temp_writable_reg $I64))
2027
- (_ Unit (emit (MInst.AluRRRExtend op (operand_size ty) dst src1 src2 extend))))
2028
- dst))
2029
-
2030
- ;; Same as `alu_rrr_extend`, but takes an `ExtendedValue` packed "pair" instead
2031
- ;; of a `Reg` and an `ExtendOp`.
2032
- (decl alu_rr_extend_reg (ALUOp Type Reg ExtendedValue) Reg)
2033
- (rule (alu_rr_extend_reg op ty src1 extended_reg)
2034
- (let ((src2 Reg (put_extended_in_reg extended_reg))
2035
- (extend ExtendOp (get_extended_op extended_reg)))
2036
- (alu_rrr_extend op ty src1 src2 extend)))
2037
-
2038
- ;; Helper for emitting `MInst.AluRRRR` instructions.
2039
- (decl alu_rrrr (ALUOp3 Type Reg Reg Reg) Reg)
2040
- (rule (alu_rrrr op ty src1 src2 src3)
2041
- (let ((dst WritableReg (temp_writable_reg $I64))
2042
- (_ Unit (emit (MInst.AluRRRR op (operand_size ty) dst src1 src2 src3))))
2043
- dst))
2044
-
2045
- ;; Helper for emitting paired `MInst.AluRRR` instructions
2046
- (decl alu_rrr_with_flags_paired (Type Reg Reg ALUOp) ProducesFlags)
2047
- (rule (alu_rrr_with_flags_paired ty src1 src2 alu_op)
2048
- (let ((dst WritableReg (temp_writable_reg $I64)))
2049
- (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
2050
- (MInst.AluRRR alu_op (operand_size ty) dst src1 src2)
2051
- dst)))
2052
-
2053
- ;; Should only be used for AdcS and SbcS
2054
- (decl alu_rrr_with_flags_chained (Type Reg Reg ALUOp) ConsumesAndProducesFlags)
2055
- (rule (alu_rrr_with_flags_chained ty src1 src2 alu_op)
2056
- (let ((dst WritableReg (temp_writable_reg $I64)))
2057
- (ConsumesAndProducesFlags.ReturnsReg
2058
- (MInst.AluRRR alu_op (operand_size ty) dst src1 src2)
2059
- dst)))
2060
-
2061
- ;; Helper for emitting `MInst.BitRR` instructions.
2062
- (decl bit_rr (BitOp Type Reg) Reg)
2063
- (rule (bit_rr op ty src)
2064
- (let ((dst WritableReg (temp_writable_reg $I64))
2065
- (_ Unit (emit (MInst.BitRR op (operand_size ty) dst src))))
2066
- dst))
2067
-
2068
- ;; Helper for emitting `adds` instructions.
2069
- (decl add_with_flags_paired (Type Reg Reg) ProducesFlags)
2070
- (rule (add_with_flags_paired ty src1 src2)
2071
- (let ((dst WritableReg (temp_writable_reg $I64)))
2072
- (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
2073
- (MInst.AluRRR (ALUOp.AddS) (operand_size ty) dst src1 src2)
2074
- dst)))
2075
-
2076
- ;; Helper for emitting `adc` instructions.
2077
- (decl adc_paired (Type Reg Reg) ConsumesFlags)
2078
- (rule (adc_paired ty src1 src2)
2079
- (let ((dst WritableReg (temp_writable_reg $I64)))
2080
- (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer
2081
- (MInst.AluRRR (ALUOp.Adc) (operand_size ty) dst src1 src2)
2082
- dst)))
2083
-
2084
- ;; Helper for emitting `subs` instructions.
2085
- (decl sub_with_flags_paired (Type Reg Reg) ProducesFlags)
2086
- (rule (sub_with_flags_paired ty src1 src2)
2087
- (let ((dst WritableReg (temp_writable_reg $I64)))
2088
- (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
2089
- (MInst.AluRRR (ALUOp.SubS) (operand_size ty) dst src1 src2)
2090
- dst)))
2091
-
2092
- ;; Helper for materializing a boolean value into a register from
2093
- ;; flags.
2094
- (decl materialize_bool_result (Cond) ConsumesFlags)
2095
- (rule (materialize_bool_result cond)
2096
- (let ((dst WritableReg (temp_writable_reg $I64)))
2097
- (ConsumesFlags.ConsumesFlagsReturnsReg
2098
- (MInst.CSet dst cond)
2099
- dst)))
2100
-
2101
- (decl cmn_imm (OperandSize Reg Imm12) ProducesFlags)
2102
- (rule (cmn_imm size src1 src2)
2103
- (ProducesFlags.ProducesFlagsSideEffect
2104
- (MInst.AluRRImm12 (ALUOp.AddS) size (writable_zero_reg)
2105
- src1 src2)))
2106
-
2107
- (decl cmp (OperandSize Reg Reg) ProducesFlags)
2108
- (rule (cmp size src1 src2)
2109
- (ProducesFlags.ProducesFlagsSideEffect
2110
- (MInst.AluRRR (ALUOp.SubS) size (writable_zero_reg)
2111
- src1 src2)))
2112
-
2113
- (decl cmp_imm (OperandSize Reg Imm12) ProducesFlags)
2114
- (rule (cmp_imm size src1 src2)
2115
- (ProducesFlags.ProducesFlagsSideEffect
2116
- (MInst.AluRRImm12 (ALUOp.SubS) size (writable_zero_reg)
2117
- src1 src2)))
2118
-
2119
- (decl cmp64_imm (Reg Imm12) ProducesFlags)
2120
- (rule (cmp64_imm src1 src2)
2121
- (cmp_imm (OperandSize.Size64) src1 src2))
2122
-
2123
- (decl cmp_extend (OperandSize Reg Reg ExtendOp) ProducesFlags)
2124
- (rule (cmp_extend size src1 src2 extend)
2125
- (ProducesFlags.ProducesFlagsSideEffect
2126
- (MInst.AluRRRExtend (ALUOp.SubS) size (writable_zero_reg)
2127
- src1 src2 extend)))
2128
-
2129
- ;; Helper for emitting `sbc` instructions.
2130
- (decl sbc_paired (Type Reg Reg) ConsumesFlags)
2131
- (rule (sbc_paired ty src1 src2)
2132
- (let ((dst WritableReg (temp_writable_reg $I64)))
2133
- (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer
2134
- (MInst.AluRRR (ALUOp.Sbc) (operand_size ty) dst src1 src2)
2135
- dst)))
2136
-
2137
- ;; Helper for emitting `MInst.VecMisc` instructions.
2138
- (decl vec_misc (VecMisc2 Reg VectorSize) Reg)
2139
- (rule (vec_misc op src size)
2140
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2141
- (_ Unit (emit (MInst.VecMisc op dst src size))))
2142
- dst))
2143
-
2144
- ;; Helper for emitting `MInst.VecTbl` instructions.
2145
- (decl vec_tbl (Reg Reg) Reg)
2146
- (rule (vec_tbl rn rm)
2147
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2148
- (_ Unit (emit (MInst.VecTbl dst rn rm))))
2149
- dst))
2150
-
2151
- (decl vec_tbl_ext (Reg Reg Reg) Reg)
2152
- (rule (vec_tbl_ext ri rn rm)
2153
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2154
- (_ Unit (emit (MInst.VecTblExt dst ri rn rm))))
2155
- dst))
2156
-
2157
- ;; Helper for emitting `MInst.VecTbl2` instructions.
2158
- (decl vec_tbl2 (Reg Reg Reg Type) Reg)
2159
- (rule (vec_tbl2 rn rn2 rm ty)
2160
- (let (
2161
- (dst WritableReg (temp_writable_reg $I8X16))
2162
- (_ Unit (emit (MInst.VecTbl2 dst rn rn2 rm)))
2163
- )
2164
- dst))
2165
-
2166
- ;; Helper for emitting `MInst.VecTbl2Ext` instructions.
2167
- (decl vec_tbl2_ext (Reg Reg Reg Reg Type) Reg)
2168
- (rule (vec_tbl2_ext ri rn rn2 rm ty)
2169
- (let (
2170
- (dst WritableReg (temp_writable_reg $I8X16))
2171
- (_ Unit (emit (MInst.VecTbl2Ext dst ri rn rn2 rm)))
2172
- )
2173
- dst))
2174
-
2175
- ;; Helper for emitting `MInst.VecRRRLong` instructions.
2176
- (decl vec_rrr_long (VecRRRLongOp Reg Reg bool) Reg)
2177
- (rule (vec_rrr_long op src1 src2 high_half)
2178
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2179
- (_ Unit (emit (MInst.VecRRRLong op dst src1 src2 high_half))))
2180
- dst))
2181
-
2182
- ;; Helper for emitting `MInst.VecRRPairLong` instructions.
2183
- (decl vec_rr_pair_long (VecRRPairLongOp Reg) Reg)
2184
- (rule (vec_rr_pair_long op src)
2185
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2186
- (_ Unit (emit (MInst.VecRRPairLong op dst src))))
2187
- dst))
2188
-
2189
- ;; Helper for emitting `MInst.VecRRRLongMod` instructions.
2190
- (decl vec_rrrr_long (VecRRRLongModOp Reg Reg Reg bool) Reg)
2191
- (rule (vec_rrrr_long op src1 src2 src3 high_half)
2192
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2193
- (_ Unit (emit (MInst.VecRRRLongMod op dst src1 src2 src3 high_half))))
2194
- dst))
2195
-
2196
- ;; Helper for emitting `MInst.VecRRNarrow` instructions.
2197
- (decl vec_rr_narrow_low (VecRRNarrowOp Reg ScalarSize) Reg)
2198
- (rule (vec_rr_narrow_low op src size)
2199
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2200
- (_ Unit (emit (MInst.VecRRNarrowLow op dst src size))))
2201
- dst))
2202
-
2203
- ;; Helper for emitting `MInst.VecRRNarrow` instructions which update the
2204
- ;; high half of the destination register.
2205
- (decl vec_rr_narrow_high (VecRRNarrowOp Reg Reg ScalarSize) Reg)
2206
- (rule (vec_rr_narrow_high op mod src size)
2207
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2208
- (_ Unit (emit (MInst.VecRRNarrowHigh op dst mod src size))))
2209
- dst))
2210
-
2211
- ;; Helper for emitting `MInst.VecRRLong` instructions.
2212
- (decl vec_rr_long (VecRRLongOp Reg bool) Reg)
2213
- (rule (vec_rr_long op src high_half)
2214
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2215
- (_ Unit (emit (MInst.VecRRLong op dst src high_half))))
2216
- dst))
2217
-
2218
- ;; Helper for emitting `MInst.FpuCSel32` / `MInst.FpuCSel64`
2219
- ;; instructions.
2220
- (decl fpu_csel (Type Cond Reg Reg) ConsumesFlags)
2221
- (rule (fpu_csel $F32 cond if_true if_false)
2222
- (let ((dst WritableReg (temp_writable_reg $F32)))
2223
- (ConsumesFlags.ConsumesFlagsReturnsReg
2224
- (MInst.FpuCSel32 dst if_true if_false cond)
2225
- dst)))
2226
-
2227
- (rule (fpu_csel $F64 cond if_true if_false)
2228
- (let ((dst WritableReg (temp_writable_reg $F64)))
2229
- (ConsumesFlags.ConsumesFlagsReturnsReg
2230
- (MInst.FpuCSel64 dst if_true if_false cond)
2231
- dst)))
2232
-
2233
- ;; Helper for emitting `MInst.VecCSel` instructions.
2234
- (decl vec_csel (Cond Reg Reg) ConsumesFlags)
2235
- (rule (vec_csel cond if_true if_false)
2236
- (let ((dst WritableReg (temp_writable_reg $I8X16)))
2237
- (ConsumesFlags.ConsumesFlagsReturnsReg
2238
- (MInst.VecCSel dst if_true if_false cond)
2239
- dst)))
2240
-
2241
- ;; Helper for emitting `MInst.FpuRound` instructions.
2242
- (decl fpu_round (FpuRoundMode Reg) Reg)
2243
- (rule (fpu_round op rn)
2244
- (let ((dst WritableReg (temp_writable_reg $F64))
2245
- (_ Unit (emit (MInst.FpuRound op dst rn))))
2246
- dst))
2247
-
2248
- ;; Helper for emitting `MInst.FpuMove64` and `MInst.FpuMove128` instructions.
2249
- (decl fpu_move (Type Reg) Reg)
2250
- (rule (fpu_move _ src)
2251
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2252
- (_ Unit (emit (MInst.FpuMove128 dst src))))
2253
- dst))
2254
- (rule 1 (fpu_move (fits_in_64 _) src)
2255
- (let ((dst WritableReg (temp_writable_reg $F64))
2256
- (_ Unit (emit (MInst.FpuMove64 dst src))))
2257
- dst))
2258
-
2259
- ;; Helper for emitting `MInst.MovToFpu` instructions.
2260
- (decl mov_to_fpu (Reg ScalarSize) Reg)
2261
- (rule (mov_to_fpu x size)
2262
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2263
- (_ Unit (emit (MInst.MovToFpu dst x size))))
2264
- dst))
2265
-
2266
- ;; Helper for emitting `MInst.FpuMoveFPImm` instructions.
2267
- (decl fpu_move_fp_imm (ASIMDFPModImm ScalarSize) Reg)
2268
- (rule (fpu_move_fp_imm imm size)
2269
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2270
- (_ Unit (emit (MInst.FpuMoveFPImm dst imm size))))
2271
- dst))
2272
-
2273
- ;; Helper for emitting `MInst.MovToVec` instructions.
2274
- (decl mov_to_vec (Reg Reg u8 VectorSize) Reg)
2275
- (rule (mov_to_vec src1 src2 lane size)
2276
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2277
- (_ Unit (emit (MInst.MovToVec dst src1 src2 lane size))))
2278
- dst))
2279
-
2280
- ;; Helper for emitting `MInst.VecMovElement` instructions.
2281
- (decl mov_vec_elem (Reg Reg u8 u8 VectorSize) Reg)
2282
- (rule (mov_vec_elem src1 src2 dst_idx src_idx size)
2283
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2284
- (_ Unit (emit (MInst.VecMovElement dst src1 src2 dst_idx src_idx size))))
2285
- dst))
2286
-
2287
- ;; Helper for emitting `MInst.MovFromVec` instructions.
2288
- (decl mov_from_vec (Reg u8 ScalarSize) Reg)
2289
- (rule (mov_from_vec rn idx size)
2290
- (let ((dst WritableReg (temp_writable_reg $I64))
2291
- (_ Unit (emit (MInst.MovFromVec dst rn idx size))))
2292
- dst))
2293
-
2294
- ;; Helper for emitting `MInst.MovFromVecSigned` instructions.
2295
- (decl mov_from_vec_signed (Reg u8 VectorSize OperandSize) Reg)
2296
- (rule (mov_from_vec_signed rn idx size scalar_size)
2297
- (let ((dst WritableReg (temp_writable_reg $I64))
2298
- (_ Unit (emit (MInst.MovFromVecSigned dst rn idx size scalar_size))))
2299
- dst))
2300
-
2301
- (decl fpu_move_from_vec (Reg u8 VectorSize) Reg)
2302
- (rule (fpu_move_from_vec rn idx size)
2303
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2304
- (_ Unit (emit (MInst.FpuMoveFromVec dst rn idx size))))
2305
- dst))
2306
-
2307
- ;; Helper for emitting `MInst.Extend` instructions.
2308
- (decl extend (Reg bool u8 u8) Reg)
2309
- (rule (extend rn signed from_bits to_bits)
2310
- (let ((dst WritableReg (temp_writable_reg $I64))
2311
- (_ Unit (emit (MInst.Extend dst rn signed from_bits to_bits))))
2312
- dst))
2313
-
2314
- ;; Helper for emitting `MInst.FpuExtend` instructions.
2315
- (decl fpu_extend (Reg ScalarSize) Reg)
2316
- (rule (fpu_extend src size)
2317
- (let ((dst WritableReg (temp_writable_reg $F32X4))
2318
- (_ Unit (emit (MInst.FpuExtend dst src size))))
2319
- dst))
2320
-
2321
- ;; Helper for emitting `MInst.VecExtend` instructions.
2322
- (decl vec_extend (VecExtendOp Reg bool ScalarSize) Reg)
2323
- (rule (vec_extend op src high_half size)
2324
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2325
- (_ Unit (emit (MInst.VecExtend op dst src high_half size))))
2326
- dst))
2327
-
2328
- ;; Helper for emitting `MInst.VecExtract` instructions.
2329
- (decl vec_extract (Reg Reg u8) Reg)
2330
- (rule (vec_extract src1 src2 idx)
2331
- (let ((dst WritableReg (temp_writable_reg $I8X16))
2332
- (_ Unit (emit (MInst.VecExtract dst src1 src2 idx))))
2333
- dst))
2334
-
2335
- ;; Helper for emitting `MInst.LoadAcquire` instructions.
2336
- (decl load_acquire (Type MemFlags Reg) Reg)
2337
- (rule (load_acquire ty flags addr)
2338
- (let ((dst WritableReg (temp_writable_reg $I64))
2339
- (_ Unit (emit (MInst.LoadAcquire ty dst addr flags))))
2340
- dst))
2341
-
2342
- ;; Helper for emitting `MInst.StoreRelease` instructions.
2343
- (decl store_release (Type MemFlags Reg Reg) SideEffectNoResult)
2344
- (rule (store_release ty flags src addr)
2345
- (SideEffectNoResult.Inst (MInst.StoreRelease ty src addr flags)))
2346
-
2347
- ;; Helper for generating a `tst` instruction.
2348
- ;;
2349
- ;; Produces a `ProducesFlags` rather than a register or emitted instruction
2350
- ;; which must be paired with `with_flags*` helpers.
2351
- (decl tst_imm (Type Reg ImmLogic) ProducesFlags)
2352
- (rule (tst_imm ty reg imm)
2353
- (ProducesFlags.ProducesFlagsSideEffect
2354
- (MInst.AluRRImmLogic (ALUOp.AndS)
2355
- (operand_size ty)
2356
- (writable_zero_reg)
2357
- reg
2358
- imm)))
2359
-
2360
- ;; Helper for generating a `CSel` instruction.
2361
- ;;
2362
- ;; Note that this doesn't actually emit anything, instead it produces a
2363
- ;; `ConsumesFlags` instruction which must be consumed with `with_flags*`
2364
- ;; helpers.
2365
- (decl csel (Cond Reg Reg) ConsumesFlags)
2366
- (rule (csel cond if_true if_false)
2367
- (let ((dst WritableReg (temp_writable_reg $I64)))
2368
- (ConsumesFlags.ConsumesFlagsReturnsReg
2369
- (MInst.CSel dst cond if_true if_false)
2370
- dst)))
2371
-
2372
- ;; Helper for constructing `cset` instructions.
2373
- (decl cset (Cond) ConsumesFlags)
2374
- (rule (cset cond)
2375
- (let ((dst WritableReg (temp_writable_reg $I64)))
2376
- (ConsumesFlags.ConsumesFlagsReturnsReg (MInst.CSet dst cond) dst)))
2377
-
2378
- ;; Helper for constructing `cset` instructions, when the flags producer will
2379
- ;; also return a value.
2380
- (decl cset_paired (Cond) ConsumesFlags)
2381
- (rule (cset_paired cond)
2382
- (let ((dst WritableReg (temp_writable_reg $I64)))
2383
- (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer (MInst.CSet dst cond) dst)))
2384
-
2385
- ;; Helper for constructing `csetm` instructions.
2386
- (decl csetm (Cond) ConsumesFlags)
2387
- (rule (csetm cond)
2388
- (let ((dst WritableReg (temp_writable_reg $I64)))
2389
- (ConsumesFlags.ConsumesFlagsReturnsReg (MInst.CSetm dst cond) dst)))
2390
-
2391
- ;; Helper for generating a `CSNeg` instruction.
2392
- ;;
2393
- ;; Note that this doesn't actually emit anything, instead it produces a
2394
- ;; `ConsumesFlags` instruction which must be consumed with `with_flags*`
2395
- ;; helpers.
2396
- (decl csneg (Cond Reg Reg) ConsumesFlags)
2397
- (rule (csneg cond if_true if_false)
2398
- (let ((dst WritableReg (temp_writable_reg $I64)))
2399
- (ConsumesFlags.ConsumesFlagsReturnsReg
2400
- (MInst.CSNeg dst cond if_true if_false)
2401
- dst)))
2402
-
2403
- ;; Helper for generating `MInst.CCmp` instructions.
2404
- ;; Creates a new `ProducesFlags` from the supplied `ProducesFlags` followed
2405
- ;; immediately by the `MInst.CCmp` instruction.
2406
- (decl ccmp (OperandSize Reg Reg NZCV Cond ProducesFlags) ProducesFlags)
2407
- (rule (ccmp size rn rm nzcv cond inst_input)
2408
- (produces_flags_concat inst_input (ProducesFlags.ProducesFlagsSideEffect (MInst.CCmp size rn rm nzcv cond))))
2409
-
2410
- ;; Helper for generating `MInst.CCmpImm` instructions.
2411
- (decl ccmp_imm (OperandSize Reg UImm5 NZCV Cond) ConsumesFlags)
2412
- (rule 1 (ccmp_imm size rn imm nzcv cond)
2413
- (let ((dst WritableReg (temp_writable_reg $I64)))
2414
- (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
2415
- (MInst.CCmpImm size rn imm nzcv cond)
2416
- (MInst.CSet dst cond)
2417
- (value_reg dst))))
2418
-
2419
- ;; Helpers for generating `add` instructions.
2420
-
2421
- (decl add (Type Reg Reg) Reg)
2422
- (rule (add ty x y) (alu_rrr (ALUOp.Add) ty x y))
2423
-
2424
- (decl add_imm (Type Reg Imm12) Reg)
2425
- (rule (add_imm ty x y) (alu_rr_imm12 (ALUOp.Add) ty x y))
2426
-
2427
- (decl add_extend (Type Reg ExtendedValue) Reg)
2428
- (rule (add_extend ty x y) (alu_rr_extend_reg (ALUOp.Add) ty x y))
2429
-
2430
- (decl add_extend_op (Type Reg Reg ExtendOp) Reg)
2431
- (rule (add_extend_op ty x y extend) (alu_rrr_extend (ALUOp.Add) ty x y extend))
2432
-
2433
- (decl add_shift (Type Reg Reg ShiftOpAndAmt) Reg)
2434
- (rule (add_shift ty x y z) (alu_rrr_shift (ALUOp.Add) ty x y z))
2435
-
2436
- (decl add_vec (Reg Reg VectorSize) Reg)
2437
- (rule (add_vec x y size) (vec_rrr (VecALUOp.Add) x y size))
2438
-
2439
- ;; Helpers for generating `sub` instructions.
2440
-
2441
- (decl sub (Type Reg Reg) Reg)
2442
- (rule (sub ty x y) (alu_rrr (ALUOp.Sub) ty x y))
2443
-
2444
- (decl sub_imm (Type Reg Imm12) Reg)
2445
- (rule (sub_imm ty x y) (alu_rr_imm12 (ALUOp.Sub) ty x y))
2446
-
2447
- (decl sub_extend (Type Reg ExtendedValue) Reg)
2448
- (rule (sub_extend ty x y) (alu_rr_extend_reg (ALUOp.Sub) ty x y))
2449
-
2450
- (decl sub_shift (Type Reg Reg ShiftOpAndAmt) Reg)
2451
- (rule (sub_shift ty x y z) (alu_rrr_shift (ALUOp.Sub) ty x y z))
2452
-
2453
- (decl sub_vec (Reg Reg VectorSize) Reg)
2454
- (rule (sub_vec x y size) (vec_rrr (VecALUOp.Sub) x y size))
2455
-
2456
- (decl sub_i128 (ValueRegs ValueRegs) ValueRegs)
2457
- (rule (sub_i128 x y)
2458
- (let
2459
- ;; Get the high/low registers for `x`.
2460
- ((x_regs ValueRegs x)
2461
- (x_lo Reg (value_regs_get x_regs 0))
2462
- (x_hi Reg (value_regs_get x_regs 1))
2463
-
2464
- ;; Get the high/low registers for `y`.
2465
- (y_regs ValueRegs y)
2466
- (y_lo Reg (value_regs_get y_regs 0))
2467
- (y_hi Reg (value_regs_get y_regs 1)))
2468
- ;; the actual subtraction is `subs` followed by `sbc` which comprises
2469
- ;; the low/high bits of the result
2470
- (with_flags
2471
- (sub_with_flags_paired $I64 x_lo y_lo)
2472
- (sbc_paired $I64 x_hi y_hi))))
2473
-
2474
- ;; Helpers for generating `madd` instructions.
2475
-
2476
- (decl madd (Type Reg Reg Reg) Reg)
2477
- (rule (madd ty x y z) (alu_rrrr (ALUOp3.MAdd) ty x y z))
2478
-
2479
- ;; Helpers for generating `msub` instructions.
2480
-
2481
- (decl msub (Type Reg Reg Reg) Reg)
2482
- (rule (msub ty x y z) (alu_rrrr (ALUOp3.MSub) ty x y z))
2483
-
2484
- ;; Helpers for generating `umaddl` instructions
2485
- (decl umaddl (Reg Reg Reg) Reg)
2486
- (rule (umaddl x y z) (alu_rrrr (ALUOp3.UMAddL) $I32 x y z))
2487
-
2488
- ;; Helpers for generating `smaddl` instructions
2489
- (decl smaddl (Reg Reg Reg) Reg)
2490
- (rule (smaddl x y z) (alu_rrrr (ALUOp3.SMAddL) $I32 x y z))
2491
-
2492
- ;; Helper for generating `uqadd` instructions.
2493
- (decl uqadd (Reg Reg VectorSize) Reg)
2494
- (rule (uqadd x y size) (vec_rrr (VecALUOp.Uqadd) x y size))
2495
-
2496
- ;; Helper for generating `sqadd` instructions.
2497
- (decl sqadd (Reg Reg VectorSize) Reg)
2498
- (rule (sqadd x y size) (vec_rrr (VecALUOp.Sqadd) x y size))
2499
-
2500
- ;; Helper for generating `uqsub` instructions.
2501
- (decl uqsub (Reg Reg VectorSize) Reg)
2502
- (rule (uqsub x y size) (vec_rrr (VecALUOp.Uqsub) x y size))
2503
-
2504
- ;; Helper for generating `sqsub` instructions.
2505
- (decl sqsub (Reg Reg VectorSize) Reg)
2506
- (rule (sqsub x y size) (vec_rrr (VecALUOp.Sqsub) x y size))
2507
-
2508
- ;; Helper for generating `umulh` instructions.
2509
- (decl umulh (Type Reg Reg) Reg)
2510
- (rule (umulh ty x y) (alu_rrr (ALUOp.UMulH) ty x y))
2511
-
2512
- ;; Helper for generating `smulh` instructions.
2513
- (decl smulh (Type Reg Reg) Reg)
2514
- (rule (smulh ty x y) (alu_rrr (ALUOp.SMulH) ty x y))
2515
-
2516
- ;; Helper for generating `mul` instructions.
2517
- (decl mul (Reg Reg VectorSize) Reg)
2518
- (rule (mul x y size) (vec_rrr (VecALUOp.Mul) x y size))
2519
-
2520
- ;; Helper for generating `neg` instructions.
2521
- (decl neg (Reg VectorSize) Reg)
2522
- (rule (neg x size) (vec_misc (VecMisc2.Neg) x size))
2523
-
2524
- ;; Helper for generating `rev16` instructions.
2525
- (decl rev16 (Reg VectorSize) Reg)
2526
- (rule (rev16 x size) (vec_misc (VecMisc2.Rev16) x size))
2527
-
2528
- ;; Helper for generating `rev32` instructions.
2529
- (decl rev32 (Reg VectorSize) Reg)
2530
- (rule (rev32 x size) (vec_misc (VecMisc2.Rev32) x size))
2531
-
2532
- ;; Helper for generating `rev64` instructions.
2533
- (decl rev64 (Reg VectorSize) Reg)
2534
- (rule (rev64 x size) (vec_misc (VecMisc2.Rev64) x size))
2535
-
2536
- ;; Helper for generating `xtn` instructions.
2537
- (decl xtn (Reg ScalarSize) Reg)
2538
- (rule (xtn x size) (vec_rr_narrow_low (VecRRNarrowOp.Xtn) x size))
2539
-
2540
- ;; Helper for generating `fcvtn` instructions.
2541
- (decl fcvtn (Reg ScalarSize) Reg)
2542
- (rule (fcvtn x size) (vec_rr_narrow_low (VecRRNarrowOp.Fcvtn) x size))
2543
-
2544
- ;; Helper for generating `sqxtn` instructions.
2545
- (decl sqxtn (Reg ScalarSize) Reg)
2546
- (rule (sqxtn x size) (vec_rr_narrow_low (VecRRNarrowOp.Sqxtn) x size))
2547
-
2548
- ;; Helper for generating `sqxtn2` instructions.
2549
- (decl sqxtn2 (Reg Reg ScalarSize) Reg)
2550
- (rule (sqxtn2 x y size) (vec_rr_narrow_high (VecRRNarrowOp.Sqxtn) x y size))
2551
-
2552
- ;; Helper for generating `sqxtun` instructions.
2553
- (decl sqxtun (Reg ScalarSize) Reg)
2554
- (rule (sqxtun x size) (vec_rr_narrow_low (VecRRNarrowOp.Sqxtun) x size))
2555
-
2556
- ;; Helper for generating `sqxtun2` instructions.
2557
- (decl sqxtun2 (Reg Reg ScalarSize) Reg)
2558
- (rule (sqxtun2 x y size) (vec_rr_narrow_high (VecRRNarrowOp.Sqxtun) x y size))
2559
-
2560
- ;; Helper for generating `uqxtn` instructions.
2561
- (decl uqxtn (Reg ScalarSize) Reg)
2562
- (rule (uqxtn x size) (vec_rr_narrow_low (VecRRNarrowOp.Uqxtn) x size))
2563
-
2564
- ;; Helper for generating `uqxtn2` instructions.
2565
- (decl uqxtn2 (Reg Reg ScalarSize) Reg)
2566
- (rule (uqxtn2 x y size) (vec_rr_narrow_high (VecRRNarrowOp.Uqxtn) x y size))
2567
-
2568
- ;; Helper for generating `fence` instructions.
2569
- (decl aarch64_fence () SideEffectNoResult)
2570
- (rule (aarch64_fence)
2571
- (SideEffectNoResult.Inst (MInst.Fence)))
2572
-
2573
- ;; Helper for generating `csdb` instructions.
2574
- (decl csdb () SideEffectNoResult)
2575
- (rule (csdb)
2576
- (SideEffectNoResult.Inst (MInst.Csdb)))
2577
-
2578
- ;; Helper for generating `brk` instructions.
2579
- (decl brk () SideEffectNoResult)
2580
- (rule (brk)
2581
- (SideEffectNoResult.Inst (MInst.Brk)))
2582
-
2583
- ;; Helper for generating `addp` instructions.
2584
- (decl addp (Reg Reg VectorSize) Reg)
2585
- (rule (addp x y size) (vec_rrr (VecALUOp.Addp) x y size))
2586
-
2587
- ;; Helper for generating `zip1` instructions.
2588
- (decl zip1 (Reg Reg VectorSize) Reg)
2589
- (rule (zip1 x y size) (vec_rrr (VecALUOp.Zip1) x y size))
2590
-
2591
- ;; Helper for generating vector `abs` instructions.
2592
- (decl vec_abs (Reg VectorSize) Reg)
2593
- (rule (vec_abs x size) (vec_misc (VecMisc2.Abs) x size))
2594
-
2595
- ;; Helper for generating instruction sequences to calculate a scalar absolute
2596
- ;; value.
2597
- (decl abs (OperandSize Reg) Reg)
2598
- (rule (abs size x)
2599
- (value_regs_get (with_flags (cmp_imm size x (u8_into_imm12 0))
2600
- (csneg (Cond.Gt) x x)) 0))
2601
-
2602
- ;; Helper for generating `addv` instructions.
2603
- (decl addv (Reg VectorSize) Reg)
2604
- (rule (addv x size) (vec_lanes (VecLanesOp.Addv) x size))
2605
-
2606
- ;; Helper for generating `shll32` instructions.
2607
- (decl shll32 (Reg bool) Reg)
2608
- (rule (shll32 x high_half) (vec_rr_long (VecRRLongOp.Shll32) x high_half))
2609
-
2610
- ;; Helpers for generating `addlp` instructions.
2611
-
2612
- (decl saddlp8 (Reg) Reg)
2613
- (rule (saddlp8 x) (vec_rr_pair_long (VecRRPairLongOp.Saddlp8) x))
2614
-
2615
- (decl saddlp16 (Reg) Reg)
2616
- (rule (saddlp16 x) (vec_rr_pair_long (VecRRPairLongOp.Saddlp16) x))
2617
-
2618
- (decl uaddlp8 (Reg) Reg)
2619
- (rule (uaddlp8 x) (vec_rr_pair_long (VecRRPairLongOp.Uaddlp8) x))
2620
-
2621
- (decl uaddlp16 (Reg) Reg)
2622
- (rule (uaddlp16 x) (vec_rr_pair_long (VecRRPairLongOp.Uaddlp16) x))
2623
-
2624
- ;; Helper for generating `umlal32` instructions.
2625
- (decl umlal32 (Reg Reg Reg bool) Reg)
2626
- (rule (umlal32 x y z high_half) (vec_rrrr_long (VecRRRLongModOp.Umlal32) x y z high_half))
2627
-
2628
- ;; Helper for generating `smull8` instructions.
2629
- (decl smull8 (Reg Reg bool) Reg)
2630
- (rule (smull8 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull8) x y high_half))
2631
-
2632
- ;; Helper for generating `umull8` instructions.
2633
- (decl umull8 (Reg Reg bool) Reg)
2634
- (rule (umull8 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull8) x y high_half))
2635
-
2636
- ;; Helper for generating `smull16` instructions.
2637
- (decl smull16 (Reg Reg bool) Reg)
2638
- (rule (smull16 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull16) x y high_half))
2639
-
2640
- ;; Helper for generating `umull16` instructions.
2641
- (decl umull16 (Reg Reg bool) Reg)
2642
- (rule (umull16 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull16) x y high_half))
2643
-
2644
- ;; Helper for generating `smull32` instructions.
2645
- (decl smull32 (Reg Reg bool) Reg)
2646
- (rule (smull32 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull32) x y high_half))
2647
-
2648
- ;; Helper for generating `umull32` instructions.
2649
- (decl umull32 (Reg Reg bool) Reg)
2650
- (rule (umull32 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull32) x y high_half))
2651
-
2652
- ;; Helper for generating `asr` instructions.
2653
- (decl asr (Type Reg Reg) Reg)
2654
- (rule (asr ty x y) (alu_rrr (ALUOp.Asr) ty x y))
2655
-
2656
- (decl asr_imm (Type Reg ImmShift) Reg)
2657
- (rule (asr_imm ty x imm) (alu_rr_imm_shift (ALUOp.Asr) ty x imm))
2658
-
2659
- ;; Helper for generating `lsr` instructions.
2660
- (decl lsr (Type Reg Reg) Reg)
2661
- (rule (lsr ty x y) (alu_rrr (ALUOp.Lsr) ty x y))
2662
-
2663
- (decl lsr_imm (Type Reg ImmShift) Reg)
2664
- (rule (lsr_imm ty x imm) (alu_rr_imm_shift (ALUOp.Lsr) ty x imm))
2665
-
2666
- ;; Helper for generating `lsl` instructions.
2667
- (decl lsl (Type Reg Reg) Reg)
2668
- (rule (lsl ty x y) (alu_rrr (ALUOp.Lsl) ty x y))
2669
-
2670
- (decl lsl_imm (Type Reg ImmShift) Reg)
2671
- (rule (lsl_imm ty x imm) (alu_rr_imm_shift (ALUOp.Lsl) ty x imm))
2672
-
2673
- ;; Helper for generating `udiv` instructions.
2674
- (decl a64_udiv (Type Reg Reg) Reg)
2675
- (rule (a64_udiv ty x y) (alu_rrr (ALUOp.UDiv) ty x y))
2676
-
2677
- ;; Helper for generating `sdiv` instructions.
2678
- (decl a64_sdiv (Type Reg Reg) Reg)
2679
- (rule (a64_sdiv ty x y) (alu_rrr (ALUOp.SDiv) ty x y))
2680
-
2681
- ;; Helper for generating `not` instructions.
2682
- (decl not (Reg VectorSize) Reg)
2683
- (rule (not x size) (vec_misc (VecMisc2.Not) x size))
2684
-
2685
- ;; Helpers for generating `orr_not` instructions.
2686
-
2687
- (decl orr_not (Type Reg Reg) Reg)
2688
- (rule (orr_not ty x y) (alu_rrr (ALUOp.OrrNot) ty x y))
2689
-
2690
- (decl orr_not_shift (Type Reg Reg ShiftOpAndAmt) Reg)
2691
- (rule (orr_not_shift ty x y shift) (alu_rrr_shift (ALUOp.OrrNot) ty x y shift))
2692
-
2693
- ;; Helpers for generating `orr` instructions.
2694
-
2695
- (decl orr (Type Reg Reg) Reg)
2696
- (rule (orr ty x y) (alu_rrr (ALUOp.Orr) ty x y))
2697
-
2698
- (decl orr_imm (Type Reg ImmLogic) Reg)
2699
- (rule (orr_imm ty x y) (alu_rr_imm_logic (ALUOp.Orr) ty x y))
2700
-
2701
- (decl orr_shift (Type Reg Reg ShiftOpAndAmt) Reg)
2702
- (rule (orr_shift ty x y shift) (alu_rrr_shift (ALUOp.Orr) ty x y shift))
2703
-
2704
- (decl orr_vec (Reg Reg VectorSize) Reg)
2705
- (rule (orr_vec x y size) (vec_rrr (VecALUOp.Orr) x y size))
2706
-
2707
- ;; Helpers for generating `and` instructions.
2708
-
2709
- (decl and_reg (Type Reg Reg) Reg)
2710
- (rule (and_reg ty x y) (alu_rrr (ALUOp.And) ty x y))
2711
-
2712
- (decl and_imm (Type Reg ImmLogic) Reg)
2713
- (rule (and_imm ty x y) (alu_rr_imm_logic (ALUOp.And) ty x y))
2714
-
2715
- (decl and_vec (Reg Reg VectorSize) Reg)
2716
- (rule (and_vec x y size) (vec_rrr (VecALUOp.And) x y size))
2717
-
2718
- ;; Helpers for generating `eor` instructions.
2719
- (decl eor (Type Reg Reg) Reg)
2720
- (rule (eor ty x y) (alu_rrr (ALUOp.Eor) ty x y))
2721
-
2722
- (decl eor_vec (Reg Reg VectorSize) Reg)
2723
- (rule (eor_vec x y size) (vec_rrr (VecALUOp.Eor) x y size))
2724
-
2725
- ;; Helpers for generating `bic` instructions.
2726
-
2727
- (decl bic (Type Reg Reg) Reg)
2728
- (rule (bic ty x y) (alu_rrr (ALUOp.AndNot) ty x y))
2729
-
2730
- (decl bic_vec (Reg Reg VectorSize) Reg)
2731
- (rule (bic_vec x y size) (vec_rrr (VecALUOp.Bic) x y size))
2732
-
2733
- ;; Helpers for generating `sshl` instructions.
2734
- (decl sshl (Reg Reg VectorSize) Reg)
2735
- (rule (sshl x y size) (vec_rrr (VecALUOp.Sshl) x y size))
2736
-
2737
- ;; Helpers for generating `ushl` instructions.
2738
- (decl ushl (Reg Reg VectorSize) Reg)
2739
- (rule (ushl x y size) (vec_rrr (VecALUOp.Ushl) x y size))
2740
-
2741
- ;; Helpers for generating `ushl` instructions.
2742
- (decl ushl_vec_imm (Reg u8 VectorSize) Reg)
2743
- (rule (ushl_vec_imm x amt size) (vec_shift_imm (VecShiftImmOp.Shl) amt x size))
2744
-
2745
- ;; Helpers for generating `ushr` instructions.
2746
- (decl ushr_vec_imm (Reg u8 VectorSize) Reg)
2747
- (rule (ushr_vec_imm x amt size) (vec_shift_imm (VecShiftImmOp.Ushr) amt x size))
2748
-
2749
- ;; Helpers for generating `sshr` instructions.
2750
- (decl sshr_vec_imm (Reg u8 VectorSize) Reg)
2751
- (rule (sshr_vec_imm x amt size) (vec_shift_imm (VecShiftImmOp.Sshr) amt x size))
2752
-
2753
- ;; Helpers for generating `rotr` instructions.
2754
-
2755
- (decl a64_rotr (Type Reg Reg) Reg)
2756
- (rule (a64_rotr ty x y) (alu_rrr (ALUOp.RotR) ty x y))
2757
-
2758
- (decl a64_rotr_imm (Type Reg ImmShift) Reg)
2759
- (rule (a64_rotr_imm ty x y) (alu_rr_imm_shift (ALUOp.RotR) ty x y))
2760
-
2761
- ;; Helpers for generating `rbit` instructions.
2762
-
2763
- (decl rbit (Type Reg) Reg)
2764
- (rule (rbit ty x) (bit_rr (BitOp.RBit) ty x))
2765
-
2766
- ;; Helpers for generating `clz` instructions.
2767
-
2768
- (decl a64_clz (Type Reg) Reg)
2769
- (rule (a64_clz ty x) (bit_rr (BitOp.Clz) ty x))
2770
-
2771
- ;; Helpers for generating `cls` instructions.
2772
-
2773
- (decl a64_cls (Type Reg) Reg)
2774
- (rule (a64_cls ty x) (bit_rr (BitOp.Cls) ty x))
2775
-
2776
- ;; Helpers for generating `rev` instructions
2777
-
2778
- (decl a64_rev16 (Type Reg) Reg)
2779
- (rule (a64_rev16 ty x) (bit_rr (BitOp.Rev16) ty x))
2780
-
2781
- (decl a64_rev32 (Type Reg) Reg)
2782
- (rule (a64_rev32 ty x) (bit_rr (BitOp.Rev32) ty x))
2783
-
2784
- (decl a64_rev64 (Type Reg) Reg)
2785
- (rule (a64_rev64 ty x) (bit_rr (BitOp.Rev64) ty x))
2786
-
2787
- ;; Helpers for generating `eon` instructions.
2788
-
2789
- (decl eon (Type Reg Reg) Reg)
2790
- (rule (eon ty x y) (alu_rrr (ALUOp.EorNot) ty x y))
2791
-
2792
- ;; Helpers for generating `cnt` instructions.
2793
-
2794
- (decl vec_cnt (Reg VectorSize) Reg)
2795
- (rule (vec_cnt x size) (vec_misc (VecMisc2.Cnt) x size))
2796
-
2797
- ;; Helpers for generating a `bsl` instruction.
2798
-
2799
- (decl bsl (Type Reg Reg Reg) Reg)
2800
- (rule (bsl ty c x y)
2801
- (vec_rrr_mod (VecALUModOp.Bsl) c x y (vector_size ty)))
2802
-
2803
- ;; Helper for generating a `udf` instruction.
2804
-
2805
- (decl udf (TrapCode) SideEffectNoResult)
2806
- (rule (udf trap_code)
2807
- (SideEffectNoResult.Inst (MInst.Udf trap_code)))
2808
-
2809
- ;; Helpers for generating various load instructions, with varying
2810
- ;; widths and sign/zero-extending properties.
2811
- (decl aarch64_uload8 (AMode MemFlags) Reg)
2812
- (rule (aarch64_uload8 amode flags)
2813
- (let ((dst WritableReg (temp_writable_reg $I64))
2814
- (_ Unit (emit (MInst.ULoad8 dst amode flags))))
2815
- dst))
2816
- (decl aarch64_sload8 (AMode MemFlags) Reg)
2817
- (rule (aarch64_sload8 amode flags)
2818
- (let ((dst WritableReg (temp_writable_reg $I64))
2819
- (_ Unit (emit (MInst.SLoad8 dst amode flags))))
2820
- dst))
2821
- (decl aarch64_uload16 (AMode MemFlags) Reg)
2822
- (rule (aarch64_uload16 amode flags)
2823
- (let ((dst WritableReg (temp_writable_reg $I64))
2824
- (_ Unit (emit (MInst.ULoad16 dst amode flags))))
2825
- dst))
2826
- (decl aarch64_sload16 (AMode MemFlags) Reg)
2827
- (rule (aarch64_sload16 amode flags)
2828
- (let ((dst WritableReg (temp_writable_reg $I64))
2829
- (_ Unit (emit (MInst.SLoad16 dst amode flags))))
2830
- dst))
2831
- (decl aarch64_uload32 (AMode MemFlags) Reg)
2832
- (rule (aarch64_uload32 amode flags)
2833
- (let ((dst WritableReg (temp_writable_reg $I64))
2834
- (_ Unit (emit (MInst.ULoad32 dst amode flags))))
2835
- dst))
2836
- (decl aarch64_sload32 (AMode MemFlags) Reg)
2837
- (rule (aarch64_sload32 amode flags)
2838
- (let ((dst WritableReg (temp_writable_reg $I64))
2839
- (_ Unit (emit (MInst.SLoad32 dst amode flags))))
2840
- dst))
2841
- (decl aarch64_uload64 (AMode MemFlags) Reg)
2842
- (rule (aarch64_uload64 amode flags)
2843
- (let ((dst WritableReg (temp_writable_reg $I64))
2844
- (_ Unit (emit (MInst.ULoad64 dst amode flags))))
2845
- dst))
2846
- (decl aarch64_fpuload32 (AMode MemFlags) Reg)
2847
- (rule (aarch64_fpuload32 amode flags)
2848
- (let ((dst WritableReg (temp_writable_reg $F64))
2849
- (_ Unit (emit (MInst.FpuLoad32 dst amode flags))))
2850
- dst))
2851
- (decl aarch64_fpuload64 (AMode MemFlags) Reg)
2852
- (rule (aarch64_fpuload64 amode flags)
2853
- (let ((dst WritableReg (temp_writable_reg $F64))
2854
- (_ Unit (emit (MInst.FpuLoad64 dst amode flags))))
2855
- dst))
2856
- (decl aarch64_fpuload128 (AMode MemFlags) Reg)
2857
- (rule (aarch64_fpuload128 amode flags)
2858
- (let ((dst WritableReg (temp_writable_reg $F64X2))
2859
- (_ Unit (emit (MInst.FpuLoad128 dst amode flags))))
2860
- dst))
2861
- (decl aarch64_loadp64 (PairAMode MemFlags) ValueRegs)
2862
- (rule (aarch64_loadp64 amode flags)
2863
- (let ((dst1 WritableReg (temp_writable_reg $I64))
2864
- (dst2 WritableReg (temp_writable_reg $I64))
2865
- (_ Unit (emit (MInst.LoadP64 dst1 dst2 amode flags))))
2866
- (value_regs dst1 dst2)))
2867
-
2868
- ;; Helpers for generating various store instructions with varying
2869
- ;; widths.
2870
- (decl aarch64_store8 (AMode MemFlags Reg) SideEffectNoResult)
2871
- (rule (aarch64_store8 amode flags val)
2872
- (SideEffectNoResult.Inst (MInst.Store8 val amode flags)))
2873
- (decl aarch64_store16 (AMode MemFlags Reg) SideEffectNoResult)
2874
- (rule (aarch64_store16 amode flags val)
2875
- (SideEffectNoResult.Inst (MInst.Store16 val amode flags)))
2876
- (decl aarch64_store32 (AMode MemFlags Reg) SideEffectNoResult)
2877
- (rule (aarch64_store32 amode flags val)
2878
- (SideEffectNoResult.Inst (MInst.Store32 val amode flags)))
2879
- (decl aarch64_store64 (AMode MemFlags Reg) SideEffectNoResult)
2880
- (rule (aarch64_store64 amode flags val)
2881
- (SideEffectNoResult.Inst (MInst.Store64 val amode flags)))
2882
- (decl aarch64_fpustore32 (AMode MemFlags Reg) SideEffectNoResult)
2883
- (rule (aarch64_fpustore32 amode flags val)
2884
- (SideEffectNoResult.Inst (MInst.FpuStore32 val amode flags)))
2885
- (decl aarch64_fpustore64 (AMode MemFlags Reg) SideEffectNoResult)
2886
- (rule (aarch64_fpustore64 amode flags val)
2887
- (SideEffectNoResult.Inst (MInst.FpuStore64 val amode flags)))
2888
- (decl aarch64_fpustore128 (AMode MemFlags Reg) SideEffectNoResult)
2889
- (rule (aarch64_fpustore128 amode flags val)
2890
- (SideEffectNoResult.Inst (MInst.FpuStore128 val amode flags)))
2891
- (decl aarch64_storep64 (PairAMode MemFlags Reg Reg) SideEffectNoResult)
2892
- (rule (aarch64_storep64 amode flags val1 val2)
2893
- (SideEffectNoResult.Inst (MInst.StoreP64 val1 val2 amode flags)))
2894
-
2895
- ;; Helper for generating a `trapif` instruction.
2896
-
2897
- (decl trap_if (ProducesFlags TrapCode Cond) InstOutput)
2898
- (rule (trap_if flags trap_code cond)
2899
- (side_effect
2900
- (with_flags_side_effect flags
2901
- (ConsumesFlags.ConsumesFlagsSideEffect
2902
- (MInst.TrapIf (cond_br_cond cond) trap_code)))))
2903
-
2904
- ;; Immediate value helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2905
-
2906
- ;; Type of extension performed by an immediate helper
2907
- (type ImmExtend
2908
- (enum
2909
- (Sign)
2910
- (Zero)))
2911
-
2912
- ;; Arguments:
2913
- ;; * Immediate type
2914
- ;; * Way to extend the immediate value to the full width of the destination
2915
- ;; register
2916
- ;; * Immediate value - only the bits that fit within the type are used and
2917
- ;; extended, while the rest are ignored
2918
- ;;
2919
- ;; Note that, unlike the convention in the AArch64 backend, this helper leaves
2920
- ;; all bits in the destination register in a defined state, i.e. smaller types
2921
- ;; such as `I8` are either sign- or zero-extended.
2922
- (decl imm (Type ImmExtend u64) Reg)
2923
-
2924
- ;; Move wide immediate instructions; to simplify, we only match when we
2925
- ;; are zero-extending the value.
2926
- (rule 3 (imm (integral_ty ty) (ImmExtend.Zero) k)
2927
- (if-let n (move_wide_const_from_u64 ty k))
2928
- (add_range_fact
2929
- (movz n (operand_size ty))
2930
- 64 k k))
2931
- (rule 2 (imm (integral_ty (ty_32_or_64 ty)) (ImmExtend.Zero) k)
2932
- (if-let n (move_wide_const_from_inverted_u64 ty k))
2933
- (add_range_fact
2934
- (movn n (operand_size ty))
2935
- 64 k k))
2936
-
2937
- ;; Weird logical-instruction immediate in ORI using zero register; to simplify,
2938
- ;; we only match when we are zero-extending the value.
2939
- (rule 1 (imm (integral_ty ty) (ImmExtend.Zero) k)
2940
- (if-let n (imm_logic_from_u64 ty k))
2941
- (add_range_fact
2942
- (orr_imm ty (zero_reg) n)
2943
- 64 k k))
2944
-
2945
- (decl load_constant64_full (Type ImmExtend u64) Reg)
2946
- (extern constructor load_constant64_full load_constant64_full)
2947
-
2948
- ;; Fallback for integral 64-bit constants
2949
- (rule (imm (integral_ty ty) extend n)
2950
- (load_constant64_full ty extend n))
2951
-
2952
- ;; Sign extension helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2953
-
2954
- ;; Place a `Value` into a register, sign extending it to 32-bits
2955
- (decl put_in_reg_sext32 (Value) Reg)
2956
- (rule -1 (put_in_reg_sext32 val @ (value_type (fits_in_32 ty)))
2957
- (extend val $true (ty_bits ty) 32))
2958
-
2959
- ;; 32/64-bit passthrough.
2960
- (rule (put_in_reg_sext32 val @ (value_type $I32)) val)
2961
- (rule (put_in_reg_sext32 val @ (value_type $I64)) val)
2962
-
2963
- ;; Place a `Value` into a register, zero extending it to 32-bits
2964
- (decl put_in_reg_zext32 (Value) Reg)
2965
- (rule -1 (put_in_reg_zext32 val @ (value_type (fits_in_32 ty)))
2966
- (extend val $false (ty_bits ty) 32))
2967
-
2968
- ;; 32/64-bit passthrough.
2969
- (rule (put_in_reg_zext32 val @ (value_type $I32)) val)
2970
- (rule (put_in_reg_zext32 val @ (value_type $I64)) val)
2971
-
2972
- ;; Place a `Value` into a register, sign extending it to 64-bits
2973
- (decl put_in_reg_sext64 (Value) Reg)
2974
- (rule 1 (put_in_reg_sext64 val @ (value_type (fits_in_32 ty)))
2975
- (extend val $true (ty_bits ty) 64))
2976
-
2977
- ;; 64-bit passthrough.
2978
- (rule (put_in_reg_sext64 val @ (value_type $I64)) val)
2979
-
2980
- ;; Place a `Value` into a register, zero extending it to 64-bits
2981
- (decl put_in_reg_zext64 (Value) Reg)
2982
- (rule 1 (put_in_reg_zext64 val @ (value_type (fits_in_32 ty)))
2983
- (extend val $false (ty_bits ty) 64))
2984
-
2985
- ;; 64-bit passthrough.
2986
- (rule (put_in_reg_zext64 val @ (value_type $I64)) val)
2987
-
2988
- ;; Misc instruction helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2989
-
2990
- (decl trap_if_zero_divisor (Reg) Reg)
2991
- (rule (trap_if_zero_divisor reg)
2992
- (let ((_ Unit (emit (MInst.TrapIf (cond_br_zero reg) (trap_code_division_by_zero)))))
2993
- reg))
2994
-
2995
- (decl size_from_ty (Type) OperandSize)
2996
- (rule 1 (size_from_ty (fits_in_32 _ty)) (OperandSize.Size32))
2997
- (rule (size_from_ty $I64) (OperandSize.Size64))
2998
-
2999
- ;; Check for signed overflow. The only case is min_value / -1.
3000
- ;; The following checks must be done in 32-bit or 64-bit, depending
3001
- ;; on the input type.
3002
- (decl trap_if_div_overflow (Type Reg Reg) Reg)
3003
- (rule (trap_if_div_overflow ty x y)
3004
- (let (
3005
- ;; Check RHS is -1.
3006
- (_ Unit (emit (MInst.AluRRImm12 (ALUOp.AddS) (operand_size ty) (writable_zero_reg) y (u8_into_imm12 1))))
3007
-
3008
- ;; Check LHS is min_value, by subtracting 1 and branching if
3009
- ;; there is overflow.
3010
- (_ Unit (emit (MInst.CCmpImm (size_from_ty ty)
3011
- x
3012
- (u8_into_uimm5 1)
3013
- (nzcv $false $false $false $false)
3014
- (Cond.Eq))))
3015
- (_ Unit (emit (MInst.TrapIf (cond_br_cond (Cond.Vs))
3016
- (trap_code_integer_overflow))))
3017
- )
3018
- x))
3019
-
3020
- ;; Check for unsigned overflow.
3021
- (decl trap_if_overflow (ProducesFlags TrapCode) Reg)
3022
- (rule (trap_if_overflow producer tc)
3023
- (with_flags_reg
3024
- producer
3025
- (ConsumesFlags.ConsumesFlagsSideEffect
3026
- (MInst.TrapIf (cond_br_cond (Cond.Hs)) tc))))
3027
-
3028
- (decl sink_atomic_load (Inst) Reg)
3029
- (rule (sink_atomic_load x @ (atomic_load _ addr))
3030
- (let ((_ Unit (sink_inst x)))
3031
- (put_in_reg addr)))
3032
-
3033
- ;; Helper for generating either an `AluRRR`, `AluRRRShift`, or `AluRRImmLogic`
3034
- ;; instruction depending on the input. Note that this requires that the `ALUOp`
3035
- ;; specified is commutative.
3036
- (decl alu_rs_imm_logic_commutative (ALUOp Type Value Value) Reg)
3037
-
3038
- ;; Base case of operating on registers.
3039
- (rule -1 (alu_rs_imm_logic_commutative op ty x y)
3040
- (alu_rrr op ty x y))
3041
-
3042
- ;; Special cases for when one operand is a constant.
3043
- (rule (alu_rs_imm_logic_commutative op ty x (iconst k))
3044
- (if-let imm (imm_logic_from_imm64 ty k))
3045
- (alu_rr_imm_logic op ty x imm))
3046
- (rule 1 (alu_rs_imm_logic_commutative op ty (iconst k) x)
3047
- (if-let imm (imm_logic_from_imm64 ty k))
3048
- (alu_rr_imm_logic op ty x imm))
3049
-
3050
- ;; Special cases for when one operand is shifted left by a constant.
3051
- (rule (alu_rs_imm_logic_commutative op ty x (ishl y (iconst k)))
3052
- (if-let amt (lshl_from_imm64 ty k))
3053
- (alu_rrr_shift op ty x y amt))
3054
- (rule 1 (alu_rs_imm_logic_commutative op ty (ishl x (iconst k)) y)
3055
- (if-let amt (lshl_from_imm64 ty k))
3056
- (alu_rrr_shift op ty y x amt))
3057
-
3058
- ;; Same as `alu_rs_imm_logic_commutative` above, except that it doesn't require
3059
- ;; that the operation is commutative.
3060
- (decl alu_rs_imm_logic (ALUOp Type Value Value) Reg)
3061
- (rule -1 (alu_rs_imm_logic op ty x y)
3062
- (alu_rrr op ty x y))
3063
- (rule (alu_rs_imm_logic op ty x (iconst k))
3064
- (if-let imm (imm_logic_from_imm64 ty k))
3065
- (alu_rr_imm_logic op ty x imm))
3066
- (rule (alu_rs_imm_logic op ty x (ishl y (iconst k)))
3067
- (if-let amt (lshl_from_imm64 ty k))
3068
- (alu_rrr_shift op ty x y amt))
3069
-
3070
- ;; Helper for generating i128 bitops which simply do the same operation to the
3071
- ;; hi/lo registers.
3072
- ;;
3073
- ;; TODO: Support immlogic here
3074
- (decl i128_alu_bitop (ALUOp Type Value Value) ValueRegs)
3075
- (rule (i128_alu_bitop op ty x y)
3076
- (let (
3077
- (x_regs ValueRegs (put_in_regs x))
3078
- (x_lo Reg (value_regs_get x_regs 0))
3079
- (x_hi Reg (value_regs_get x_regs 1))
3080
- (y_regs ValueRegs (put_in_regs y))
3081
- (y_lo Reg (value_regs_get y_regs 0))
3082
- (y_hi Reg (value_regs_get y_regs 1))
3083
- )
3084
- (value_regs
3085
- (alu_rrr op ty x_lo y_lo)
3086
- (alu_rrr op ty x_hi y_hi))))
3087
-
3088
- ;; Helper for emitting `MInst.VecLoadReplicate` instructions.
3089
- (decl ld1r (Reg VectorSize MemFlags) Reg)
3090
- (rule (ld1r src size flags)
3091
- (let ((dst WritableReg (temp_writable_reg $I8X16))
3092
- (_ Unit (emit (MInst.VecLoadReplicate dst src size flags))))
3093
- dst))
3094
-
3095
- ;; Helper for emitting `MInst.LoadExtName` instructions.
3096
- (decl load_ext_name (BoxExternalName i64) Reg)
3097
- (rule (load_ext_name extname offset)
3098
- (let ((dst WritableReg (temp_writable_reg $I64))
3099
- (_ Unit (emit (MInst.LoadExtName dst extname offset))))
3100
- dst))
3101
-
3102
- ;; Lower the address of a load or a store.
3103
- ;;
3104
- ;; This will create an `AMode` representing the address of the `Value` provided
3105
- ;; at runtime plus the immediate offset `i32` provided. The `Type` here is used
3106
- ;; to represent the size of the value being loaded or stored for offset scaling
3107
- ;; if necessary.
3108
- ;;
3109
- ;; Note that this is broken up into two phases. In the first phase this attempts
3110
- ;; to find constants within the `val` provided and fold them in to the `offset`
3111
- ;; provided. Afterwards though the `amode_no_more_iconst` helper is used at
3112
- ;; which pointer constants are no longer pattern-matched and instead only
3113
- ;; various modes are generated. This in theory would not be necessary with
3114
- ;; mid-end optimizations that fold constants into load/store immediate offsets
3115
- ;; instead, but for now each backend needs to do this.
3116
- (decl amode (Type Value i32) AMode)
3117
- (rule 0 (amode ty val offset)
3118
- (amode_no_more_iconst ty val offset))
3119
- (rule 1 (amode ty (iadd x (iconst (simm32 y))) offset)
3120
- (if-let new_offset (s32_add_fallible y offset))
3121
- (amode_no_more_iconst ty x new_offset))
3122
- (rule 2 (amode ty (iadd (iconst (simm32 x)) y) offset)
3123
- (if-let new_offset (s32_add_fallible x offset))
3124
- (amode_no_more_iconst ty y new_offset))
3125
-
3126
- (decl amode_no_more_iconst (Type Value i32) AMode)
3127
- ;; Base case: move the `offset` into a register and add it to `val` via the
3128
- ;; amode
3129
- (rule 0 (amode_no_more_iconst ty val offset)
3130
- (AMode.RegReg val (imm $I64 (ImmExtend.Zero) (i64_as_u64 offset))))
3131
-
3132
- ;; Optimize cases where the `offset` provided fits into a immediates of
3133
- ;; various kinds of addressing modes.
3134
- (rule 1 (amode_no_more_iconst ty val offset)
3135
- (if-let simm9 (simm9_from_i64 offset))
3136
- (AMode.Unscaled val simm9))
3137
- (rule 2 (amode_no_more_iconst ty val offset)
3138
- (if-let uimm12 (uimm12_scaled_from_i64 offset ty))
3139
- (AMode.UnsignedOffset val uimm12))
3140
-
3141
- ;; Optimizations where addition can fold some operations into the `amode`.
3142
- ;;
3143
- ;; Note that here these take higher priority than constants because an
3144
- ;; add-of-extend can be folded into an amode, representing 2 otherwise emitted
3145
- ;; instructions. Constants on the other hand added to the amode represent only
3146
- ;; a single instruction folded in, so fewer instructions should be generated
3147
- ;; with these higher priority than the rules above.
3148
- (rule 3 (amode_no_more_iconst ty (iadd x y) offset)
3149
- (AMode.RegReg (amode_add x offset) y))
3150
- (rule 4 (amode_no_more_iconst ty (iadd x (uextend y @ (value_type $I32))) offset)
3151
- (AMode.RegExtended (amode_add x offset) y (ExtendOp.UXTW)))
3152
- (rule 4 (amode_no_more_iconst ty (iadd x (sextend y @ (value_type $I32))) offset)
3153
- (AMode.RegExtended (amode_add x offset) y (ExtendOp.SXTW)))
3154
- (rule 5 (amode_no_more_iconst ty (iadd (uextend x @ (value_type $I32)) y) offset)
3155
- (AMode.RegExtended (amode_add y offset) x (ExtendOp.UXTW)))
3156
- (rule 5 (amode_no_more_iconst ty (iadd (sextend x @ (value_type $I32)) y) offset)
3157
- (AMode.RegExtended (amode_add y offset) x (ExtendOp.SXTW)))
3158
-
3159
- ;; `RegScaled*` rules where this matches an addition of an "index register" to a
3160
- ;; base register. The index register is shifted by the size of the type loaded
3161
- ;; in bytes to enable this mode matching.
3162
- ;;
3163
- ;; Note that this can additionally bundle an extending operation but the
3164
- ;; extension must happen before the shift. This will pattern-match the shift
3165
- ;; first and then if that succeeds afterwards try to find an extend.
3166
- (rule 6 (amode_no_more_iconst ty (iadd x (ishl y (iconst (u64_from_imm64 n)))) offset)
3167
- (if-let $true (u64_eq (ty_bytes ty) (u64_shl 1 n)))
3168
- (amode_reg_scaled (amode_add x offset) y ty))
3169
- (rule 7 (amode_no_more_iconst ty (iadd (ishl y (iconst (u64_from_imm64 n))) x) offset)
3170
- (if-let $true (u64_eq (ty_bytes ty) (u64_shl 1 n)))
3171
- (amode_reg_scaled (amode_add x offset) y ty))
3172
-
3173
- (decl amode_reg_scaled (Reg Value Type) AMode)
3174
- (rule 0 (amode_reg_scaled base index ty)
3175
- (AMode.RegScaled base index ty))
3176
- (rule 1 (amode_reg_scaled base (uextend index @ (value_type $I32)) ty)
3177
- (AMode.RegScaledExtended base index ty (ExtendOp.UXTW)))
3178
- (rule 2 (amode_reg_scaled base (sextend index @ (value_type $I32)) ty)
3179
- (AMode.RegScaledExtended base index ty (ExtendOp.SXTW)))
3180
-
3181
- ;; Helper to add a 32-bit signed immediate to the register provided. This will
3182
- ;; select an appropriate `add` instruction to use.
3183
- (decl amode_add (Reg i32) Reg)
3184
- (rule 0 (amode_add x y)
3185
- (add $I64 x (imm $I64 (ImmExtend.Zero) (i64_as_u64 y))))
3186
- (rule 1 (amode_add x y)
3187
- (if-let (imm12_from_u64 imm12) (i64_as_u64 y))
3188
- (add_imm $I64 x imm12))
3189
- (rule 2 (amode_add x 0) x)
3190
-
3191
- ;; Creates a `PairAMode` for the `Value` provided plus the `i32` constant
3192
- ;; offset provided.
3193
- (decl pair_amode (Value i32) PairAMode)
3194
-
3195
- ;; Base case where `val` and `offset` are combined with an `add`
3196
- (rule 0 (pair_amode val offset)
3197
- (if-let simm7 (simm7_scaled_from_i64 0 $I64))
3198
- (PairAMode.SignedOffset (amode_add val offset) simm7))
3199
-
3200
- ;; Optimization when `offset` can fit into a `SImm7Scaled`.
3201
- (rule 1 (pair_amode val offset)
3202
- (if-let simm7 (simm7_scaled_from_i64 offset $I64))
3203
- (PairAMode.SignedOffset val simm7))
3204
-
3205
- (decl pure partial simm7_scaled_from_i64 (i64 Type) SImm7Scaled)
3206
- (extern constructor simm7_scaled_from_i64 simm7_scaled_from_i64)
3207
-
3208
- (decl pure partial uimm12_scaled_from_i64 (i64 Type) UImm12Scaled)
3209
- (extern constructor uimm12_scaled_from_i64 uimm12_scaled_from_i64)
3210
-
3211
- (decl pure partial simm9_from_i64 (i64) SImm9)
3212
- (extern constructor simm9_from_i64 simm9_from_i64)
3213
-
3214
-
3215
- (decl sink_load_into_addr (Type Inst) Reg)
3216
- (rule (sink_load_into_addr ty x @ (load _ addr (offset32 offset)))
3217
- (let ((_ Unit (sink_inst x)))
3218
- (add_imm_to_addr addr (i64_as_u64 offset))))
3219
-
3220
- (decl add_imm_to_addr (Reg u64) Reg)
3221
- (rule 2 (add_imm_to_addr val 0) val)
3222
- (rule 1 (add_imm_to_addr val (imm12_from_u64 imm)) (add_imm $I64 val imm))
3223
- (rule 0 (add_imm_to_addr val offset) (add $I64 val (imm $I64 (ImmExtend.Zero) offset)))
3224
-
3225
- ;; Lower a constant f32.
3226
- ;;
3227
- ;; Note that we must make sure that all bits outside the lowest 32 are set to 0
3228
- ;; because this function is also used to load wider constants (that have zeros
3229
- ;; in their most significant bits).
3230
- (decl constant_f32 (u32) Reg)
3231
- (rule 2 (constant_f32 0)
3232
- (vec_dup_imm (asimd_mov_mod_imm_zero (ScalarSize.Size32))
3233
- $false
3234
- (VectorSize.Size32x2)))
3235
- (rule 1 (constant_f32 n)
3236
- (if-let imm (asimd_fp_mod_imm_from_u64 n (ScalarSize.Size32)))
3237
- (fpu_move_fp_imm imm (ScalarSize.Size32)))
3238
- (rule (constant_f32 n)
3239
- (mov_to_fpu (imm $I32 (ImmExtend.Zero) n) (ScalarSize.Size32)))
3240
-
3241
- ;; Lower a constant f64.
3242
- ;;
3243
- ;; Note that we must make sure that all bits outside the lowest 64 are set to 0
3244
- ;; because this function is also used to load wider constants (that have zeros
3245
- ;; in their most significant bits).
3246
- ;; TODO: Treat as half of a 128 bit vector and consider replicated patterns.
3247
- ;; Scalar MOVI might also be an option.
3248
- (decl constant_f64 (u64) Reg)
3249
- (rule 4 (constant_f64 0)
3250
- (vec_dup_imm (asimd_mov_mod_imm_zero (ScalarSize.Size32))
3251
- $false
3252
- (VectorSize.Size32x2)))
3253
- (rule 3 (constant_f64 n)
3254
- (if-let imm (asimd_fp_mod_imm_from_u64 n (ScalarSize.Size64)))
3255
- (fpu_move_fp_imm imm (ScalarSize.Size64)))
3256
- (rule 2 (constant_f64 (u64_as_u32 n))
3257
- (constant_f32 n))
3258
- (rule 1 (constant_f64 (u64_low32_bits_unset n))
3259
- (mov_to_fpu (imm $I64 (ImmExtend.Zero) n) (ScalarSize.Size64)))
3260
- (rule (constant_f64 n)
3261
- (fpu_load64 (AMode.Const (emit_u64_le_const n)) (mem_flags_trusted)))
3262
-
3263
- ;; Tests whether the low 32 bits in the input are all zero.
3264
- (decl u64_low32_bits_unset (u64) u64)
3265
- (extern extractor u64_low32_bits_unset u64_low32_bits_unset)
3266
-
3267
- ;; Lower a constant f128.
3268
- (decl constant_f128 (u128) Reg)
3269
- (rule 3 (constant_f128 0)
3270
- (vec_dup_imm (asimd_mov_mod_imm_zero (ScalarSize.Size8))
3271
- $false
3272
- (VectorSize.Size8x16)))
3273
-
3274
- ;; If the upper 64-bits are all zero then defer to `constant_f64`.
3275
- (rule 2 (constant_f128 (u128_as_u64 n)) (constant_f64 n))
3276
-
3277
- ;; If the low half of the u128 equals the high half then delegate to the splat
3278
- ;; logic as a splat of a 64-bit value.
3279
- (rule 1 (constant_f128 (u128_replicated_u64 n))
3280
- (splat_const n (VectorSize.Size64x2)))
3281
-
3282
- ;; Base case is to load the constant from memory.
3283
- (rule (constant_f128 n)
3284
- (fpu_load128 (AMode.Const (emit_u128_le_const n)) (mem_flags_trusted)))
3285
-
3286
- ;; Lower a vector splat with a constant parameter.
3287
- ;;
3288
- ;; The 64-bit input here only uses the low bits for the lane size in
3289
- ;; `VectorSize` and all other bits are ignored.
3290
- (decl splat_const (u64 VectorSize) Reg)
3291
-
3292
- ;; If the splat'd constant can itself be reduced in size then attempt to do so
3293
- ;; as it will make it easier to create the immediates in the instructions below.
3294
- (rule 5 (splat_const (u64_replicated_u32 n) (VectorSize.Size64x2))
3295
- (splat_const n (VectorSize.Size32x4)))
3296
- (rule 5 (splat_const (u32_replicated_u16 n) (VectorSize.Size32x4))
3297
- (splat_const n (VectorSize.Size16x8)))
3298
- (rule 5 (splat_const (u32_replicated_u16 n) (VectorSize.Size32x2))
3299
- (splat_const n (VectorSize.Size16x4)))
3300
- (rule 5 (splat_const (u16_replicated_u8 n) (VectorSize.Size16x8))
3301
- (splat_const n (VectorSize.Size8x16)))
3302
- (rule 5 (splat_const (u16_replicated_u8 n) (VectorSize.Size16x4))
3303
- (splat_const n (VectorSize.Size8x8)))
3304
-
3305
- ;; Special cases for `vec_dup_imm` instructions where the input is either
3306
- ;; negated or not.
3307
- (rule 4 (splat_const n size)
3308
- (if-let imm (asimd_mov_mod_imm_from_u64 n (vector_lane_size size)))
3309
- (vec_dup_imm imm $false size))
3310
- (rule 3 (splat_const n size)
3311
- (if-let imm (asimd_mov_mod_imm_from_u64 (u64_not n) (vector_lane_size size)))
3312
- (vec_dup_imm imm $true size))
3313
-
3314
- ;; Special case a 32-bit splat where an immediate can be created by
3315
- ;; concatenating the 32-bit constant into a 64-bit value
3316
- (rule 2 (splat_const n (VectorSize.Size32x4))
3317
- (if-let imm (asimd_mov_mod_imm_from_u64 (u64_or n (u64_shl n 32)) (ScalarSize.Size64)))
3318
- (vec_dup_imm imm $false (VectorSize.Size64x2)))
3319
- (rule 2 (splat_const n (VectorSize.Size32x2))
3320
- (if-let imm (asimd_mov_mod_imm_from_u64 (u64_or n (u64_shl n 32)) (ScalarSize.Size64)))
3321
- (fpu_extend (vec_dup_imm imm $false (VectorSize.Size64x2)) (ScalarSize.Size64)))
3322
-
3323
- (rule 1 (splat_const n size)
3324
- (if-let imm (asimd_fp_mod_imm_from_u64 n (vector_lane_size size)))
3325
- (vec_dup_fp_imm imm size))
3326
-
3327
- ;; The base case for splat is to use `vec_dup` with the immediate loaded into a
3328
- ;; register.
3329
- (rule (splat_const n size)
3330
- (vec_dup (imm $I64 (ImmExtend.Zero) n) size))
3331
-
3332
- ;; Lower a FloatCC to a Cond.
3333
- (decl fp_cond_code (FloatCC) Cond)
3334
- ;; TODO: Port lower_fp_condcode() to ISLE.
3335
- (extern constructor fp_cond_code fp_cond_code)
3336
-
3337
- ;; Lower an integer cond code.
3338
- (decl cond_code (IntCC) Cond)
3339
- ;; TODO: Port lower_condcode() to ISLE.
3340
- (extern constructor cond_code cond_code)
3341
-
3342
- ;; Invert a condition code.
3343
- (decl invert_cond (Cond) Cond)
3344
- ;; TODO: Port cond.invert() to ISLE.
3345
- (extern constructor invert_cond invert_cond)
3346
-
3347
- ;; Generate comparison to zero operator from input condition code
3348
- (decl float_cc_cmp_zero_to_vec_misc_op (FloatCC) VecMisc2)
3349
- (extern constructor float_cc_cmp_zero_to_vec_misc_op float_cc_cmp_zero_to_vec_misc_op)
3350
-
3351
- (decl float_cc_cmp_zero_to_vec_misc_op_swap (FloatCC) VecMisc2)
3352
- (extern constructor float_cc_cmp_zero_to_vec_misc_op_swap float_cc_cmp_zero_to_vec_misc_op_swap)
3353
-
3354
- ;; Match valid generic compare to zero cases
3355
- (decl fcmp_zero_cond (FloatCC) FloatCC)
3356
- (extern extractor fcmp_zero_cond fcmp_zero_cond)
3357
-
3358
- ;; Match not equal compare to zero separately as it requires two output instructions
3359
- (decl fcmp_zero_cond_not_eq (FloatCC) FloatCC)
3360
- (extern extractor fcmp_zero_cond_not_eq fcmp_zero_cond_not_eq)
3361
-
3362
- ;; Helper for generating float compare to zero instructions where 2nd argument is zero
3363
- (decl float_cmp_zero (FloatCC Reg VectorSize) Reg)
3364
- (rule (float_cmp_zero cond rn size)
3365
- (vec_misc (float_cc_cmp_zero_to_vec_misc_op cond) rn size))
3366
-
3367
- ;; Helper for generating float compare to zero instructions in case where 1st argument is zero
3368
- (decl float_cmp_zero_swap (FloatCC Reg VectorSize) Reg)
3369
- (rule (float_cmp_zero_swap cond rn size)
3370
- (vec_misc (float_cc_cmp_zero_to_vec_misc_op_swap cond) rn size))
3371
-
3372
- ;; Helper for generating float compare equal to zero instruction
3373
- (decl fcmeq0 (Reg VectorSize) Reg)
3374
- (rule (fcmeq0 rn size)
3375
- (vec_misc (VecMisc2.Fcmeq0) rn size))
3376
-
3377
- ;; Generate comparison to zero operator from input condition code
3378
- (decl int_cc_cmp_zero_to_vec_misc_op (IntCC) VecMisc2)
3379
- (extern constructor int_cc_cmp_zero_to_vec_misc_op int_cc_cmp_zero_to_vec_misc_op)
3380
-
3381
- (decl int_cc_cmp_zero_to_vec_misc_op_swap (IntCC) VecMisc2)
3382
- (extern constructor int_cc_cmp_zero_to_vec_misc_op_swap int_cc_cmp_zero_to_vec_misc_op_swap)
3383
-
3384
- ;; Match valid generic compare to zero cases
3385
- (decl icmp_zero_cond (IntCC) IntCC)
3386
- (extern extractor icmp_zero_cond icmp_zero_cond)
3387
-
3388
- ;; Match not equal compare to zero separately as it requires two output instructions
3389
- (decl icmp_zero_cond_not_eq (IntCC) IntCC)
3390
- (extern extractor icmp_zero_cond_not_eq icmp_zero_cond_not_eq)
3391
-
3392
- ;; Helper for generating int compare to zero instructions where 2nd argument is zero
3393
- (decl int_cmp_zero (IntCC Reg VectorSize) Reg)
3394
- (rule (int_cmp_zero cond rn size)
3395
- (vec_misc (int_cc_cmp_zero_to_vec_misc_op cond) rn size))
3396
-
3397
- ;; Helper for generating int compare to zero instructions in case where 1st argument is zero
3398
- (decl int_cmp_zero_swap (IntCC Reg VectorSize) Reg)
3399
- (rule (int_cmp_zero_swap cond rn size)
3400
- (vec_misc (int_cc_cmp_zero_to_vec_misc_op_swap cond) rn size))
3401
-
3402
- ;; Helper for generating int compare equal to zero instruction
3403
- (decl cmeq0 (Reg VectorSize) Reg)
3404
- (rule (cmeq0 rn size)
3405
- (vec_misc (VecMisc2.Cmeq0) rn size))
3406
-
3407
- ;; Helper for emitting `MInst.AtomicRMW` instructions.
3408
- (decl lse_atomic_rmw (AtomicRMWOp Value Reg Type MemFlags) Reg)
3409
- (rule (lse_atomic_rmw op p r_arg2 ty flags)
3410
- (let (
3411
- (r_addr Reg p)
3412
- (dst WritableReg (temp_writable_reg ty))
3413
- (_ Unit (emit (MInst.AtomicRMW op r_arg2 dst r_addr ty flags)))
3414
- )
3415
- dst))
3416
-
3417
- ;; Helper for emitting `MInst.AtomicCAS` instructions.
3418
- (decl lse_atomic_cas (Reg Reg Reg Type MemFlags) Reg)
3419
- (rule (lse_atomic_cas addr expect replace ty flags)
3420
- (let (
3421
- (dst WritableReg (temp_writable_reg ty))
3422
- (_ Unit (emit (MInst.AtomicCAS dst expect replace addr ty flags)))
3423
- )
3424
- dst))
3425
-
3426
- ;; Helper for emitting `MInst.AtomicRMWLoop` instructions.
3427
- ;; - Make sure that both args are in virtual regs, since in effect
3428
- ;; we have to do a parallel copy to get them safely to the AtomicRMW input
3429
- ;; regs, and that's not guaranteed safe if either is in a real reg.
3430
- ;; - Move the args to the preordained AtomicRMW input regs
3431
- ;; - And finally, copy the preordained AtomicRMW output reg to its destination.
3432
- (decl atomic_rmw_loop (AtomicRMWLoopOp Reg Reg Type MemFlags) Reg)
3433
- (rule (atomic_rmw_loop op addr operand ty flags)
3434
- (let ((dst WritableReg (temp_writable_reg $I64))
3435
- (scratch1 WritableReg (temp_writable_reg $I64))
3436
- (scratch2 WritableReg (temp_writable_reg $I64))
3437
- (_ Unit (emit (MInst.AtomicRMWLoop ty op flags addr operand dst scratch1 scratch2))))
3438
- dst))
3439
-
3440
- ;; Helper for emitting `MInst.AtomicCASLoop` instructions.
3441
- ;; This is very similar to, but not identical to, the AtomicRmw case. Note
3442
- ;; that the AtomicCASLoop sequence does its own masking, so we don't need to worry
3443
- ;; about zero-extending narrow (I8/I16/I32) values here.
3444
- ;; Make sure that all three args are in virtual regs. See corresponding comment
3445
- ;; for `atomic_rmw_loop` above.
3446
- (decl atomic_cas_loop (Reg Reg Reg Type MemFlags) Reg)
3447
- (rule (atomic_cas_loop addr expect replace ty flags)
3448
- (let ((dst WritableReg (temp_writable_reg $I64))
3449
- (scratch WritableReg (temp_writable_reg $I64))
3450
- (_ Unit (emit (MInst.AtomicCASLoop ty flags addr expect replace dst scratch))))
3451
- dst))
3452
-
3453
- ;; Helper for emitting `MInst.MovPReg` instructions.
3454
- (decl mov_from_preg (PReg) Reg)
3455
- (rule (mov_from_preg src)
3456
- (let ((dst WritableReg (temp_writable_reg $I64))
3457
- (_ Unit (emit (MInst.MovFromPReg dst src))))
3458
- dst))
3459
-
3460
- (decl mov_to_preg (PReg Reg) SideEffectNoResult)
3461
- (rule (mov_to_preg dst src)
3462
- (SideEffectNoResult.Inst (MInst.MovToPReg dst src)))
3463
-
3464
- (decl preg_sp () PReg)
3465
- (extern constructor preg_sp preg_sp)
3466
-
3467
- (decl preg_fp () PReg)
3468
- (extern constructor preg_fp preg_fp)
3469
-
3470
- (decl preg_link () PReg)
3471
- (extern constructor preg_link preg_link)
3472
-
3473
- (decl preg_pinned () PReg)
3474
- (extern constructor preg_pinned preg_pinned)
3475
-
3476
- (decl aarch64_sp () Reg)
3477
- (rule (aarch64_sp)
3478
- (mov_from_preg (preg_sp)))
3479
-
3480
- (decl aarch64_fp () Reg)
3481
- (rule (aarch64_fp)
3482
- (mov_from_preg (preg_fp)))
3483
-
3484
- (decl aarch64_link () Reg)
3485
- (rule 1 (aarch64_link)
3486
- (if (preserve_frame_pointers))
3487
- (if (sign_return_address_disabled))
3488
- (let ((dst WritableReg (temp_writable_reg $I64))
3489
- ;; Even though LR is not an allocatable register, whether it
3490
- ;; contains the return address for the current function is
3491
- ;; unknown at this point. For example, this operation may come
3492
- ;; immediately after a call, in which case LR would not have a
3493
- ;; valid value. That's why we must obtain the return address from
3494
- ;; the frame record that corresponds to the current subroutine on
3495
- ;; the stack; the presence of the record is guaranteed by the
3496
- ;; `preserve_frame_pointers` setting.
3497
- (addr AMode (AMode.FPOffset 8 $I64))
3498
- (_ Unit (emit (MInst.ULoad64 dst addr (mem_flags_trusted)))))
3499
- dst))
3500
-
3501
- (rule (aarch64_link)
3502
- (if (preserve_frame_pointers))
3503
- ;; Similarly to the rule above, we must load the return address from the
3504
- ;; the frame record. Furthermore, we can use LR as a scratch register
3505
- ;; because the function will set it to the return address immediately
3506
- ;; before returning.
3507
- (let ((addr AMode (AMode.FPOffset 8 $I64))
3508
- (lr WritableReg (writable_link_reg))
3509
- (_ Unit (emit (MInst.ULoad64 lr addr (mem_flags_trusted))))
3510
- (_ Unit (emit (MInst.Xpaclri))))
3511
- (mov_from_preg (preg_link))))
3512
-
3513
- ;; Helper for getting the maximum shift amount for a type.
3514
-
3515
- (decl max_shift (Type) u8)
3516
- (rule (max_shift $F64) 63)
3517
- (rule (max_shift $F32) 31)
3518
-
3519
- ;; Helper for generating `fcopysign` instruction sequences.
3520
-
3521
- (decl fcopy_sign (Reg Reg Type) Reg)
3522
- (rule 1 (fcopy_sign x y (ty_scalar_float ty))
3523
- (let ((dst WritableReg (temp_writable_reg $F64))
3524
- (tmp Reg (fpu_rri (fpu_op_ri_ushr (ty_bits ty) (max_shift ty)) y))
3525
- (_ Unit (emit (MInst.FpuRRIMod (fpu_op_ri_sli (ty_bits ty) (max_shift ty)) dst x tmp))))
3526
- dst))
3527
- (rule (fcopy_sign x y ty @ (multi_lane _ _))
3528
- (let ((dst WritableReg (temp_writable_reg $I8X16))
3529
- (tmp Reg (ushr_vec_imm y (max_shift (lane_type ty)) (vector_size ty)))
3530
- (_ Unit (emit (MInst.VecShiftImmMod (VecShiftImmModOp.Sli) dst x tmp (vector_size ty) (max_shift (lane_type ty))))))
3531
- dst))
3532
-
3533
- ;; Helpers for generating `MInst.FpuToInt` instructions.
3534
-
3535
- (decl fpu_to_int_nan_check (ScalarSize Reg) Reg)
3536
- (rule (fpu_to_int_nan_check size src)
3537
- (let ((r ValueRegs
3538
- (with_flags (fpu_cmp size src src)
3539
- (ConsumesFlags.ConsumesFlagsReturnsReg
3540
- (MInst.TrapIf (cond_br_cond (Cond.Vs))
3541
- (trap_code_bad_conversion_to_integer))
3542
- src))))
3543
- (value_regs_get r 0)))
3544
-
3545
- ;; Checks that the value is not less than the minimum bound,
3546
- ;; accepting a boolean (whether the type is signed), input type,
3547
- ;; output type, and registers containing the source and minimum bound.
3548
- (decl fpu_to_int_underflow_check (bool Type Type Reg Reg) Reg)
3549
- (rule (fpu_to_int_underflow_check $true $F32 (fits_in_16 out_ty) src min)
3550
- (let ((r ValueRegs
3551
- (with_flags (fpu_cmp (ScalarSize.Size32) src min)
3552
- (ConsumesFlags.ConsumesFlagsReturnsReg
3553
- (MInst.TrapIf (cond_br_cond (Cond.Le))
3554
- (trap_code_integer_overflow))
3555
- src))))
3556
- (value_regs_get r 0)))
3557
- (rule (fpu_to_int_underflow_check $true $F64 (fits_in_32 out_ty) src min)
3558
- (let ((r ValueRegs
3559
- (with_flags (fpu_cmp (ScalarSize.Size64) src min)
3560
- (ConsumesFlags.ConsumesFlagsReturnsReg
3561
- (MInst.TrapIf (cond_br_cond (Cond.Le))
3562
- (trap_code_integer_overflow))
3563
- src))))
3564
- (value_regs_get r 0)))
3565
- (rule -1 (fpu_to_int_underflow_check $true in_ty _out_ty src min)
3566
- (let ((r ValueRegs
3567
- (with_flags (fpu_cmp (scalar_size in_ty) src min)
3568
- (ConsumesFlags.ConsumesFlagsReturnsReg
3569
- (MInst.TrapIf (cond_br_cond (Cond.Lt))
3570
- (trap_code_integer_overflow))
3571
- src))))
3572
- (value_regs_get r 0)))
3573
- (rule (fpu_to_int_underflow_check $false in_ty _out_ty src min)
3574
- (let ((r ValueRegs
3575
- (with_flags (fpu_cmp (scalar_size in_ty) src min)
3576
- (ConsumesFlags.ConsumesFlagsReturnsReg
3577
- (MInst.TrapIf (cond_br_cond (Cond.Le))
3578
- (trap_code_integer_overflow))
3579
- src))))
3580
- (value_regs_get r 0)))
3581
-
3582
- (decl fpu_to_int_overflow_check (ScalarSize Reg Reg) Reg)
3583
- (rule (fpu_to_int_overflow_check size src max)
3584
- (let ((r ValueRegs
3585
- (with_flags (fpu_cmp size src max)
3586
- (ConsumesFlags.ConsumesFlagsReturnsReg
3587
- (MInst.TrapIf (cond_br_cond (Cond.Ge))
3588
- (trap_code_integer_overflow))
3589
- src))))
3590
- (value_regs_get r 0)))
3591
-
3592
- ;; Emits the appropriate instruction sequence to convert a
3593
- ;; floating-point value to an integer, trapping if the value
3594
- ;; is a NaN or does not fit in the target type.
3595
- ;; Accepts the specific conversion op, the source register,
3596
- ;; whether the input is signed, and finally the input and output
3597
- ;; types.
3598
- (decl fpu_to_int_cvt (FpuToIntOp Reg bool Type Type) Reg)
3599
- (rule (fpu_to_int_cvt op src signed in_ty out_ty)
3600
- (let ((size ScalarSize (scalar_size in_ty))
3601
- (in_bits u8 (ty_bits in_ty))
3602
- (out_bits u8 (ty_bits out_ty))
3603
- (src Reg (fpu_to_int_nan_check size src))
3604
- (min Reg (min_fp_value signed in_bits out_bits))
3605
- (src Reg (fpu_to_int_underflow_check signed in_ty out_ty src min))
3606
- (max Reg (max_fp_value signed in_bits out_bits))
3607
- (src Reg (fpu_to_int_overflow_check size src max)))
3608
- (fpu_to_int op src)))
3609
-
3610
- ;; Emits the appropriate instruction sequence to convert a
3611
- ;; floating-point value to an integer, saturating if the value
3612
- ;; does not fit in the target type.
3613
- ;; Accepts the specific conversion op, the source register,
3614
- ;; whether the input is signed, and finally the output type.
3615
- (decl fpu_to_int_cvt_sat (FpuToIntOp Reg bool Type) Reg)
3616
- (rule 1 (fpu_to_int_cvt_sat op src _ $I64)
3617
- (fpu_to_int op src))
3618
- (rule 1 (fpu_to_int_cvt_sat op src _ $I32)
3619
- (fpu_to_int op src))
3620
- (rule (fpu_to_int_cvt_sat op src $false (fits_in_16 out_ty))
3621
- (let ((result Reg (fpu_to_int op src))
3622
- (max Reg (imm out_ty (ImmExtend.Zero) (ty_mask out_ty))))
3623
- (with_flags_reg
3624
- (cmp (OperandSize.Size32) result max)
3625
- (csel (Cond.Hi) max result))))
3626
- (rule (fpu_to_int_cvt_sat op src $true (fits_in_16 out_ty))
3627
- (let ((result Reg (fpu_to_int op src))
3628
- (max Reg (signed_max out_ty))
3629
- (min Reg (signed_min out_ty))
3630
- (result Reg (with_flags_reg
3631
- (cmp (operand_size out_ty) result max)
3632
- (csel (Cond.Gt) max result)))
3633
- (result Reg (with_flags_reg
3634
- (cmp (operand_size out_ty) result min)
3635
- (csel (Cond.Lt) min result))))
3636
- result))
3637
-
3638
- (decl signed_min (Type) Reg)
3639
- (rule (signed_min $I8) (imm $I8 (ImmExtend.Sign) 0x80))
3640
- (rule (signed_min $I16) (imm $I16 (ImmExtend.Sign) 0x8000))
3641
-
3642
- (decl signed_max (Type) Reg)
3643
- (rule (signed_max $I8) (imm $I8 (ImmExtend.Sign) 0x7F))
3644
- (rule (signed_max $I16) (imm $I16 (ImmExtend.Sign) 0x7FFF))
3645
-
3646
- (decl fpu_to_int (FpuToIntOp Reg) Reg)
3647
- (rule (fpu_to_int op src)
3648
- (let ((dst WritableReg (temp_writable_reg $I64))
3649
- (_ Unit (emit (MInst.FpuToInt op dst src))))
3650
- dst))
3651
-
3652
- ;; Helper for generating `MInst.IntToFpu` instructions.
3653
-
3654
- (decl int_to_fpu (IntToFpuOp Reg) Reg)
3655
- (rule (int_to_fpu op src)
3656
- (let ((dst WritableReg (temp_writable_reg $I8X16))
3657
- (_ Unit (emit (MInst.IntToFpu op dst src))))
3658
- dst))
3659
-
3660
- ;;;; Helpers for Emitting Calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3661
-
3662
- (decl gen_call (SigRef ExternalName RelocDistance ValueSlice) InstOutput)
3663
- (extern constructor gen_call gen_call)
3664
-
3665
- (decl gen_call_indirect (SigRef Value ValueSlice) InstOutput)
3666
- (extern constructor gen_call_indirect gen_call_indirect)
3667
-
3668
- ;; Helpers for pinned register manipulation.
3669
-
3670
- (decl write_pinned_reg (Reg) SideEffectNoResult)
3671
- (rule (write_pinned_reg val)
3672
- (mov_to_preg (preg_pinned) val))
3673
-
3674
- ;; Helpers for stackslot effective address generation.
3675
-
3676
- (decl compute_stack_addr (StackSlot Offset32) Reg)
3677
- (rule (compute_stack_addr stack_slot offset)
3678
- (let ((dst WritableReg (temp_writable_reg $I64))
3679
- (_ Unit (emit (abi_stackslot_addr dst stack_slot offset))))
3680
- dst))
3681
-
3682
- ;; Helper for emitting instruction sequences to perform a vector comparison.
3683
-
3684
- (decl vec_cmp_vc (Reg Reg VectorSize) Reg)
3685
- (rule (vec_cmp_vc rn rm size)
3686
- (let ((dst Reg (vec_rrr (VecALUOp.Fcmeq) rn rn size))
3687
- (tmp Reg (vec_rrr (VecALUOp.Fcmeq) rm rm size))
3688
- (dst Reg (vec_rrr (VecALUOp.And) dst tmp size)))
3689
- dst))
3690
-
3691
- (decl vec_cmp (Reg Reg Type Cond) Reg)
3692
-
3693
- ;; Floating point Vs / Vc
3694
- (rule (vec_cmp rn rm ty (Cond.Vc))
3695
- (if (ty_vector_float ty))
3696
- (vec_cmp_vc rn rm (vector_size ty)))
3697
- (rule (vec_cmp rn rm ty (Cond.Vs))
3698
- (if (ty_vector_float ty))
3699
- (let ((tmp Reg (vec_cmp_vc rn rm (vector_size ty))))
3700
- (vec_misc (VecMisc2.Not) tmp (vector_size ty))))
3701
-
3702
- ;; 'Less than' operations are implemented by swapping the order of
3703
- ;; operands and using the 'greater than' instructions.
3704
- ;; 'Not equal' is implemented with 'equal' and inverting the result.
3705
-
3706
- ;; Floating-point
3707
- (rule (vec_cmp rn rm ty (Cond.Eq))
3708
- (if (ty_vector_float ty))
3709
- (vec_rrr (VecALUOp.Fcmeq) rn rm (vector_size ty)))
3710
- (rule (vec_cmp rn rm ty (Cond.Ne))
3711
- (if (ty_vector_float ty))
3712
- (let ((tmp Reg (vec_rrr (VecALUOp.Fcmeq) rn rm (vector_size ty))))
3713
- (vec_misc (VecMisc2.Not) tmp (vector_size ty))))
3714
- (rule (vec_cmp rn rm ty (Cond.Ge))
3715
- (if (ty_vector_float ty))
3716
- (vec_rrr (VecALUOp.Fcmge) rn rm (vector_size ty)))
3717
- (rule (vec_cmp rn rm ty (Cond.Gt))
3718
- (if (ty_vector_float ty))
3719
- (vec_rrr (VecALUOp.Fcmgt) rn rm (vector_size ty)))
3720
- ;; Floating-point swapped-operands
3721
- (rule (vec_cmp rn rm ty (Cond.Mi))
3722
- (if (ty_vector_float ty))
3723
- (vec_rrr (VecALUOp.Fcmgt) rm rn (vector_size ty)))
3724
- (rule (vec_cmp rn rm ty (Cond.Ls))
3725
- (if (ty_vector_float ty))
3726
- (vec_rrr (VecALUOp.Fcmge) rm rn (vector_size ty)))
3727
-
3728
- ;; Integer
3729
- (rule 1 (vec_cmp rn rm ty (Cond.Eq))
3730
- (if (ty_vector_not_float ty))
3731
- (vec_rrr (VecALUOp.Cmeq) rn rm (vector_size ty)))
3732
- (rule 1 (vec_cmp rn rm ty (Cond.Ne))
3733
- (if (ty_vector_not_float ty))
3734
- (let ((tmp Reg (vec_rrr (VecALUOp.Cmeq) rn rm (vector_size ty))))
3735
- (vec_misc (VecMisc2.Not) tmp (vector_size ty))))
3736
- (rule 1 (vec_cmp rn rm ty (Cond.Ge))
3737
- (if (ty_vector_not_float ty))
3738
- (vec_rrr (VecALUOp.Cmge) rn rm (vector_size ty)))
3739
- (rule 1 (vec_cmp rn rm ty (Cond.Gt))
3740
- (if (ty_vector_not_float ty))
3741
- (vec_rrr (VecALUOp.Cmgt) rn rm (vector_size ty)))
3742
- (rule (vec_cmp rn rm ty (Cond.Hs))
3743
- (if (ty_vector_not_float ty))
3744
- (vec_rrr (VecALUOp.Cmhs) rn rm (vector_size ty)))
3745
- (rule (vec_cmp rn rm ty (Cond.Hi))
3746
- (if (ty_vector_not_float ty))
3747
- (vec_rrr (VecALUOp.Cmhi) rn rm (vector_size ty)))
3748
- ;; Integer swapped-operands
3749
- (rule (vec_cmp rn rm ty (Cond.Le))
3750
- (if (ty_vector_not_float ty))
3751
- (vec_rrr (VecALUOp.Cmge) rm rn (vector_size ty)))
3752
- (rule (vec_cmp rn rm ty (Cond.Lt))
3753
- (if (ty_vector_not_float ty))
3754
- (vec_rrr (VecALUOp.Cmgt) rm rn (vector_size ty)))
3755
- (rule 1 (vec_cmp rn rm ty (Cond.Ls))
3756
- (if (ty_vector_not_float ty))
3757
- (vec_rrr (VecALUOp.Cmhs) rm rn (vector_size ty)))
3758
- (rule (vec_cmp rn rm ty (Cond.Lo))
3759
- (if (ty_vector_not_float ty))
3760
- (vec_rrr (VecALUOp.Cmhi) rm rn (vector_size ty)))
3761
-
3762
- ;; Helper for determining if any value in a vector is true.
3763
- ;; This operation is implemented by using umaxp to create a scalar value, which
3764
- ;; is then compared against zero.
3765
- ;;
3766
- ;; umaxp vn.4s, vm.4s, vm.4s
3767
- ;; mov xm, vn.d[0]
3768
- ;; cmp xm, #0
3769
- (decl vanytrue (Reg Type) ProducesFlags)
3770
- (rule 1 (vanytrue src (ty_vec128 ty))
3771
- (let ((src Reg (vec_rrr (VecALUOp.Umaxp) src src (VectorSize.Size32x4)))
3772
- (src Reg (mov_from_vec src 0 (ScalarSize.Size64))))
3773
- (cmp_imm (OperandSize.Size64) src (u8_into_imm12 0))))
3774
- (rule (vanytrue src ty)
3775
- (if (ty_vec64 ty))
3776
- (let ((src Reg (mov_from_vec src 0 (ScalarSize.Size64))))
3777
- (cmp_imm (OperandSize.Size64) src (u8_into_imm12 0))))
3778
-
3779
- ;;;; TLS Values ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3780
-
3781
- ;; Helper for emitting ElfTlsGetAddr.
3782
- (decl elf_tls_get_addr (ExternalName) Reg)
3783
- (rule (elf_tls_get_addr name)
3784
- (let ((dst WritableReg (temp_writable_reg $I64))
3785
- (tmp WritableReg (temp_writable_reg $I64))
3786
- (_ Unit (emit (MInst.ElfTlsGetAddr (box_external_name name) dst tmp))))
3787
- dst))
3788
-
3789
- (decl macho_tls_get_addr (ExternalName) Reg)
3790
- (rule (macho_tls_get_addr name)
3791
- (let ((dst WritableReg (temp_writable_reg $I64))
3792
- (_ Unit (emit (MInst.MachOTlsGetAddr name dst))))
3793
- dst))
3794
-
3795
- ;; A tuple of `ProducesFlags` and `IntCC`.
3796
- (type FlagsAndCC (enum (FlagsAndCC (flags ProducesFlags)
3797
- (cc IntCC))))
3798
-
3799
- ;; Helper constructor for `FlagsAndCC`.
3800
- (decl flags_and_cc (ProducesFlags IntCC) FlagsAndCC)
3801
- (rule (flags_and_cc flags cc) (FlagsAndCC.FlagsAndCC flags cc))
3802
-
3803
- ;; Materialize a `FlagsAndCC` into a boolean `ValueRegs`.
3804
- (decl flags_and_cc_to_bool (FlagsAndCC) ValueRegs)
3805
- (rule (flags_and_cc_to_bool (FlagsAndCC.FlagsAndCC flags cc))
3806
- (with_flags flags (materialize_bool_result (cond_code cc))))
3807
-
3808
- ;; Get the `ProducesFlags` out of a `FlagsAndCC`.
3809
- (decl flags_and_cc_flags (FlagsAndCC) ProducesFlags)
3810
- (rule (flags_and_cc_flags (FlagsAndCC.FlagsAndCC flags _cc)) flags)
3811
-
3812
- ;; Get the `IntCC` out of a `FlagsAndCC`.
3813
- (decl flags_and_cc_cc (FlagsAndCC) IntCC)
3814
- (rule (flags_and_cc_cc (FlagsAndCC.FlagsAndCC _flags cc)) cc)
3815
-
3816
- ;; Helpers for lowering `icmp` sequences.
3817
- ;; `lower_icmp` contains shared functionality for lowering `icmp`
3818
- ;; sequences, which `lower_icmp_into_{reg,flags}` extend from.
3819
- (decl lower_icmp (IntCC Value Value Type) FlagsAndCC)
3820
- (decl lower_icmp_into_reg (IntCC Value Value Type Type) ValueRegs)
3821
- (decl lower_icmp_into_flags (IntCC Value Value Type) FlagsAndCC)
3822
- (decl lower_icmp_const (IntCC Value u64 Type) FlagsAndCC)
3823
- ;; For most cases, `lower_icmp_into_flags` is the same as `lower_icmp`,
3824
- ;; except for some I128 cases (see below).
3825
- (rule -1 (lower_icmp_into_flags cond x y ty) (lower_icmp cond x y ty))
3826
-
3827
- ;; Vectors.
3828
- ;; `icmp` into flags for vectors is invalid.
3829
- (rule 1 (lower_icmp_into_reg cond x y in_ty @ (multi_lane _ _) _out_ty)
3830
- (let ((cond Cond (cond_code cond))
3831
- (rn Reg (put_in_reg x))
3832
- (rm Reg (put_in_reg y)))
3833
- (vec_cmp rn rm in_ty cond)))
3834
-
3835
- ;; Determines the appropriate extend op given the value type and the given ArgumentExtension.
3836
- (decl lower_extend_op (Type ArgumentExtension) ExtendOp)
3837
- (rule (lower_extend_op $I8 (ArgumentExtension.Sext)) (ExtendOp.SXTB))
3838
- (rule (lower_extend_op $I16 (ArgumentExtension.Sext)) (ExtendOp.SXTH))
3839
- (rule (lower_extend_op $I8 (ArgumentExtension.Uext)) (ExtendOp.UXTB))
3840
- (rule (lower_extend_op $I16 (ArgumentExtension.Uext)) (ExtendOp.UXTH))
3841
-
3842
- ;; Integers <= 64-bits.
3843
- (rule -2 (lower_icmp_into_reg cond rn rm in_ty out_ty)
3844
- (if (ty_int_ref_scalar_64 in_ty))
3845
- (let ((cc Cond (cond_code cond)))
3846
- (flags_and_cc_to_bool (lower_icmp cond rn rm in_ty))))
3847
-
3848
- (rule 1 (lower_icmp cond rn rm (fits_in_16 ty))
3849
- (if (signed_cond_code cond))
3850
- (let ((rn Reg (put_in_reg_sext32 rn)))
3851
- (flags_and_cc (cmp_extend (operand_size ty) rn rm (lower_extend_op ty (ArgumentExtension.Sext))) cond)))
3852
- (rule -1 (lower_icmp cond rn (imm12_from_value rm) (fits_in_16 ty))
3853
- (let ((rn Reg (put_in_reg_zext32 rn)))
3854
- (flags_and_cc (cmp_imm (operand_size ty) rn rm) cond)))
3855
- (rule -2 (lower_icmp cond rn rm (fits_in_16 ty))
3856
- (let ((rn Reg (put_in_reg_zext32 rn)))
3857
- (flags_and_cc (cmp_extend (operand_size ty) rn rm (lower_extend_op ty (ArgumentExtension.Uext))) cond)))
3858
- (rule -3 (lower_icmp cond rn (u64_from_iconst c) ty)
3859
- (if (ty_int_ref_scalar_64 ty))
3860
- (lower_icmp_const cond rn c ty))
3861
- (rule -4 (lower_icmp cond rn rm ty)
3862
- (if (ty_int_ref_scalar_64 ty))
3863
- (flags_and_cc (cmp (operand_size ty) rn rm) cond))
3864
-
3865
- ;; We get better encodings when testing against an immediate that's even instead
3866
- ;; of odd, so rewrite comparisons to use even immediates:
3867
- ;;
3868
- ;; A >= B + 1
3869
- ;; ==> A - 1 >= B
3870
- ;; ==> A > B
3871
- (rule (lower_icmp_const (IntCC.UnsignedGreaterThanOrEqual) a b ty)
3872
- (if (ty_int_ref_scalar_64 ty))
3873
- (if-let $true (u64_is_odd b))
3874
- (if-let (imm12_from_u64 imm) (u64_sub b 1))
3875
- (flags_and_cc (cmp_imm (operand_size ty) a imm) (IntCC.UnsignedGreaterThan)))
3876
- (rule (lower_icmp_const (IntCC.SignedGreaterThanOrEqual) a b ty)
3877
- (if (ty_int_ref_scalar_64 ty))
3878
- (if-let $true (u64_is_odd b))
3879
- (if-let (imm12_from_u64 imm) (u64_sub b 1))
3880
- (flags_and_cc (cmp_imm (operand_size ty) a imm) (IntCC.SignedGreaterThan)))
3881
-
3882
- (rule -1 (lower_icmp_const cond rn (imm12_from_u64 c) ty)
3883
- (if (ty_int_ref_scalar_64 ty))
3884
- (flags_and_cc (cmp_imm (operand_size ty) rn c) cond))
3885
- (rule -2 (lower_icmp_const cond rn c ty)
3886
- (if (ty_int_ref_scalar_64 ty))
3887
- (flags_and_cc (cmp (operand_size ty) rn (imm ty (ImmExtend.Zero) c)) cond))
3888
-
3889
-
3890
- ;; 128-bit integers.
3891
- (rule (lower_icmp_into_reg cond @ (IntCC.Equal) rn rm $I128 $I8)
3892
- (let ((cc Cond (cond_code cond)))
3893
- (flags_and_cc_to_bool
3894
- (lower_icmp cond rn rm $I128))))
3895
- (rule (lower_icmp_into_reg cond @ (IntCC.NotEqual) rn rm $I128 $I8)
3896
- (let ((cc Cond (cond_code cond)))
3897
- (flags_and_cc_to_bool
3898
- (lower_icmp cond rn rm $I128))))
3899
-
3900
- ;; cmp lhs_lo, rhs_lo
3901
- ;; ccmp lhs_hi, rhs_hi, #0, eq
3902
- (decl lower_icmp_i128_eq_ne (Value Value) ProducesFlags)
3903
- (rule (lower_icmp_i128_eq_ne lhs rhs)
3904
- (let ((lhs ValueRegs (put_in_regs lhs))
3905
- (rhs ValueRegs (put_in_regs rhs))
3906
- (lhs_lo Reg (value_regs_get lhs 0))
3907
- (lhs_hi Reg (value_regs_get lhs 1))
3908
- (rhs_lo Reg (value_regs_get rhs 0))
3909
- (rhs_hi Reg (value_regs_get rhs 1))
3910
- (cmp_inst ProducesFlags (cmp (OperandSize.Size64) lhs_lo rhs_lo)))
3911
- (ccmp (OperandSize.Size64) lhs_hi rhs_hi
3912
- (nzcv $false $false $false $false) (Cond.Eq) cmp_inst)))
3913
-
3914
- (rule (lower_icmp (IntCC.Equal) lhs rhs $I128)
3915
- (flags_and_cc (lower_icmp_i128_eq_ne lhs rhs) (IntCC.Equal)))
3916
- (rule (lower_icmp (IntCC.NotEqual) lhs rhs $I128)
3917
- (flags_and_cc (lower_icmp_i128_eq_ne lhs rhs) (IntCC.NotEqual)))
3918
-
3919
- ;; cmp lhs_lo, rhs_lo
3920
- ;; cset tmp1, unsigned_cond
3921
- ;; cmp lhs_hi, rhs_hi
3922
- ;; cset tmp2, cond
3923
- ;; csel dst, tmp1, tmp2, eq
3924
- (rule -1 (lower_icmp_into_reg cond lhs rhs $I128 $I8)
3925
- (let ((unsigned_cond Cond (cond_code (intcc_unsigned cond)))
3926
- (cond Cond (cond_code cond))
3927
- (lhs ValueRegs (put_in_regs lhs))
3928
- (rhs ValueRegs (put_in_regs rhs))
3929
- (lhs_lo Reg (value_regs_get lhs 0))
3930
- (lhs_hi Reg (value_regs_get lhs 1))
3931
- (rhs_lo Reg (value_regs_get rhs 0))
3932
- (rhs_hi Reg (value_regs_get rhs 1))
3933
- (tmp1 Reg (with_flags_reg (cmp (OperandSize.Size64) lhs_lo rhs_lo)
3934
- (materialize_bool_result unsigned_cond))))
3935
- (with_flags (cmp (OperandSize.Size64) lhs_hi rhs_hi)
3936
- (lower_icmp_i128_consumer cond tmp1))))
3937
-
3938
- (decl lower_icmp_i128_consumer (Cond Reg) ConsumesFlags)
3939
- (rule (lower_icmp_i128_consumer cond tmp1)
3940
- (let ((tmp2 WritableReg (temp_writable_reg $I64))
3941
- (dst WritableReg (temp_writable_reg $I64)))
3942
- (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
3943
- (MInst.CSet tmp2 cond)
3944
- (MInst.CSel dst (Cond.Eq) tmp1 tmp2)
3945
- (value_reg dst))))
3946
-
3947
- (decl lower_bmask (Type Type ValueRegs) ValueRegs)
3948
-
3949
-
3950
- ;; For conversions that exactly fit a register, we can use csetm.
3951
- ;;
3952
- ;; cmp val, #0
3953
- ;; csetm res, ne
3954
- (rule 0
3955
- (lower_bmask (fits_in_64 _) (ty_32_or_64 in_ty) val)
3956
- (with_flags_reg
3957
- (cmp_imm (operand_size in_ty) (value_regs_get val 0) (u8_into_imm12 0))
3958
- (csetm (Cond.Ne))))
3959
-
3960
- ;; For conversions from a 128-bit value into a 64-bit or smaller one, we or the
3961
- ;; two registers of the 128-bit value together, and then recurse with the
3962
- ;; combined value as a 64-bit test.
3963
- ;;
3964
- ;; orr val, lo, hi
3965
- ;; cmp val, #0
3966
- ;; csetm res, ne
3967
- (rule 1
3968
- (lower_bmask (fits_in_64 ty) $I128 val)
3969
- (let ((lo Reg (value_regs_get val 0))
3970
- (hi Reg (value_regs_get val 1))
3971
- (combined Reg (orr $I64 lo hi)))
3972
- (lower_bmask ty $I64 (value_reg combined))))
3973
-
3974
- ;; For converting from any type into i128, duplicate the result of
3975
- ;; converting to i64.
3976
- (rule 2
3977
- (lower_bmask $I128 in_ty val)
3978
- (let ((res ValueRegs (lower_bmask $I64 in_ty val))
3979
- (res Reg (value_regs_get res 0)))
3980
- (value_regs res res)))
3981
-
3982
- ;; For conversions smaller than a register, we need to mask off the high bits, and then
3983
- ;; we can recurse into the general case.
3984
- ;;
3985
- ;; and tmp, val, #ty_mask
3986
- ;; cmp tmp, #0
3987
- ;; csetm res, ne
3988
- (rule 3
3989
- (lower_bmask out_ty (fits_in_16 in_ty) val)
3990
- ; This if-let can't fail due to ty_mask always producing 8/16 consecutive 1s.
3991
- (if-let mask_bits (imm_logic_from_u64 $I32 (ty_mask in_ty)))
3992
- (let ((masked Reg (and_imm $I32 (value_regs_get val 0) mask_bits)))
3993
- (lower_bmask out_ty $I32 masked)))
3994
-
3995
- ;; Exceptional `lower_icmp_into_flags` rules.
3996
- ;; We need to guarantee that the flags for `cond` are correct, so we
3997
- ;; compare `dst` with 1.
3998
- (rule (lower_icmp_into_flags cond @ (IntCC.SignedGreaterThanOrEqual) lhs rhs $I128)
3999
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4000
- (dst Reg (value_regs_get dst 0))
4001
- (tmp Reg (imm $I64 (ImmExtend.Sign) 1))) ;; mov tmp, #1
4002
- (flags_and_cc (cmp (OperandSize.Size64) dst tmp) cond)))
4003
- (rule (lower_icmp_into_flags cond @ (IntCC.UnsignedGreaterThanOrEqual) lhs rhs $I128)
4004
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4005
- (dst Reg (value_regs_get dst 0))
4006
- (tmp Reg (imm $I64 (ImmExtend.Zero) 1)))
4007
- (flags_and_cc (cmp (OperandSize.Size64) dst tmp) cond)))
4008
- (rule (lower_icmp_into_flags cond @ (IntCC.SignedLessThanOrEqual) lhs rhs $I128)
4009
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4010
- (dst Reg (value_regs_get dst 0))
4011
- (tmp Reg (imm $I64 (ImmExtend.Sign) 1)))
4012
- (flags_and_cc (cmp (OperandSize.Size64) tmp dst) cond)))
4013
- (rule (lower_icmp_into_flags cond @ (IntCC.UnsignedLessThanOrEqual) lhs rhs $I128)
4014
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4015
- (dst Reg (value_regs_get dst 0))
4016
- (tmp Reg (imm $I64 (ImmExtend.Zero) 1)))
4017
- (flags_and_cc (cmp (OperandSize.Size64) tmp dst) cond)))
4018
- ;; For strict comparisons, we compare with 0.
4019
- (rule (lower_icmp_into_flags cond @ (IntCC.SignedGreaterThan) lhs rhs $I128)
4020
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4021
- (dst Reg (value_regs_get dst 0)))
4022
- (flags_and_cc (cmp (OperandSize.Size64) dst (zero_reg)) cond)))
4023
- (rule (lower_icmp_into_flags cond @ (IntCC.UnsignedGreaterThan) lhs rhs $I128)
4024
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4025
- (dst Reg (value_regs_get dst 0)))
4026
- (flags_and_cc (cmp (OperandSize.Size64) dst (zero_reg)) cond)))
4027
- (rule (lower_icmp_into_flags cond @ (IntCC.SignedLessThan) lhs rhs $I128)
4028
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4029
- (dst Reg (value_regs_get dst 0)))
4030
- (flags_and_cc (cmp (OperandSize.Size64) (zero_reg) dst) cond)))
4031
- (rule (lower_icmp_into_flags cond @ (IntCC.UnsignedLessThan) lhs rhs $I128)
4032
- (let ((dst ValueRegs (lower_icmp_into_reg cond lhs rhs $I128 $I8))
4033
- (dst Reg (value_regs_get dst 0)))
4034
- (flags_and_cc (cmp (OperandSize.Size64) (zero_reg) dst) cond)))
4035
-
4036
- ;; Helpers for generating select instruction sequences.
4037
- (decl lower_select (ProducesFlags Cond Type Value Value) ValueRegs)
4038
- (rule 2 (lower_select flags cond (ty_scalar_float ty) rn rm)
4039
- (with_flags flags (fpu_csel ty cond rn rm)))
4040
- (rule 3 (lower_select flags cond (ty_vec128 ty) rn rm)
4041
- (with_flags flags (vec_csel cond rn rm)))
4042
- (rule (lower_select flags cond ty rn rm)
4043
- (if (ty_vec64 ty))
4044
- (with_flags flags (fpu_csel $F64 cond rn rm)))
4045
- (rule 4 (lower_select flags cond $I128 rn rm)
4046
- (let ((dst_lo WritableReg (temp_writable_reg $I64))
4047
- (dst_hi WritableReg (temp_writable_reg $I64))
4048
- (rn ValueRegs (put_in_regs rn))
4049
- (rm ValueRegs (put_in_regs rm))
4050
- (rn_lo Reg (value_regs_get rn 0))
4051
- (rn_hi Reg (value_regs_get rn 1))
4052
- (rm_lo Reg (value_regs_get rm 0))
4053
- (rm_hi Reg (value_regs_get rm 1)))
4054
- (with_flags flags
4055
- (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
4056
- (MInst.CSel dst_lo cond rn_lo rm_lo)
4057
- (MInst.CSel dst_hi cond rn_hi rm_hi)
4058
- (value_regs dst_lo dst_hi)))))
4059
- (rule 1 (lower_select flags cond ty rn rm)
4060
- (if (ty_int_ref_scalar_64 ty))
4061
- (with_flags flags (csel cond rn rm)))
4062
-
4063
- ;; Helper for emitting `MInst.Jump` instructions.
4064
- (decl aarch64_jump (BranchTarget) SideEffectNoResult)
4065
- (rule (aarch64_jump target)
4066
- (SideEffectNoResult.Inst (MInst.Jump target)))
4067
-
4068
- ;; Helper for emitting `MInst.JTSequence` instructions.
4069
- ;; Emit the compound instruction that does:
4070
- ;;
4071
- ;; b.hs default
4072
- ;; csel rB, xzr, rIndex, hs
4073
- ;; csdb
4074
- ;; adr rA, jt
4075
- ;; ldrsw rB, [rA, rB, uxtw #2]
4076
- ;; add rA, rA, rB
4077
- ;; br rA
4078
- ;; [jt entries]
4079
- ;;
4080
- ;; This must be *one* instruction in the vcode because
4081
- ;; we cannot allow regalloc to insert any spills/fills
4082
- ;; in the middle of the sequence; otherwise, the ADR's
4083
- ;; PC-rel offset to the jumptable would be incorrect.
4084
- ;; (The alternative is to introduce a relocation pass
4085
- ;; for inlined jumptables, which is much worse, IMHO.)
4086
- (decl jt_sequence (Reg MachLabel BoxVecMachLabel) ConsumesFlags)
4087
- (rule (jt_sequence ridx default targets)
4088
- (let ((rtmp1 WritableReg (temp_writable_reg $I64))
4089
- (rtmp2 WritableReg (temp_writable_reg $I64)))
4090
- (ConsumesFlags.ConsumesFlagsSideEffect
4091
- (MInst.JTSequence default targets ridx rtmp1 rtmp2))))
4092
-
4093
- ;; Helper for emitting `MInst.CondBr` instructions.
4094
- (decl cond_br (BranchTarget BranchTarget CondBrKind) ConsumesFlags)
4095
- (rule (cond_br taken not_taken kind)
4096
- (ConsumesFlags.ConsumesFlagsSideEffect
4097
- (MInst.CondBr taken not_taken kind)))
4098
-
4099
- ;; Helper for emitting `MInst.TestBitAndBranch` instructions.
4100
- (decl test_branch (TestBitAndBranchKind BranchTarget BranchTarget Reg u8) SideEffectNoResult)
4101
- (rule (test_branch kind taken not_taken rn bit)
4102
- (SideEffectNoResult.Inst (MInst.TestBitAndBranch kind taken not_taken rn bit)))
4103
-
4104
- ;; Helper for emitting `tbnz` instructions.
4105
- (decl tbnz (BranchTarget BranchTarget Reg u8) SideEffectNoResult)
4106
- (rule (tbnz taken not_taken rn bit)
4107
- (test_branch (TestBitAndBranchKind.NZ) taken not_taken rn bit))
4108
-
4109
- ;; Helper for emitting `tbz` instructions.
4110
- (decl tbz (BranchTarget BranchTarget Reg u8) SideEffectNoResult)
4111
- (rule (tbz taken not_taken rn bit)
4112
- (test_branch (TestBitAndBranchKind.Z) taken not_taken rn bit))
4113
-
4114
- ;; Helper for emitting `MInst.MovToNZCV` instructions.
4115
- (decl mov_to_nzcv (Reg) ProducesFlags)
4116
- (rule (mov_to_nzcv rn)
4117
- (ProducesFlags.ProducesFlagsSideEffect
4118
- (MInst.MovToNZCV rn)))
4119
-
4120
- ;; Helper for emitting `MInst.EmitIsland` instructions.
4121
- (decl emit_island (CodeOffset) SideEffectNoResult)
4122
- (rule (emit_island needed_space)
4123
- (SideEffectNoResult.Inst
4124
- (MInst.EmitIsland needed_space)))
4125
-
4126
- ;; Helper for emitting `br_table` sequences.
4127
- (decl br_table_impl (u64 Reg MachLabel BoxVecMachLabel) Unit)
4128
- (rule (br_table_impl (imm12_from_u64 jt_size) ridx default targets)
4129
- (emit_side_effect (with_flags_side_effect
4130
- (cmp_imm (OperandSize.Size32) ridx jt_size)
4131
- (jt_sequence ridx default targets))))
4132
- (rule -1 (br_table_impl jt_size ridx default targets)
4133
- (let ((jt_size Reg (imm $I64 (ImmExtend.Zero) jt_size)))
4134
- (emit_side_effect (with_flags_side_effect
4135
- (cmp (OperandSize.Size32) ridx jt_size)
4136
- (jt_sequence ridx default targets)))))
4137
-
4138
- ;; Helper for emitting the `uzp1` instruction
4139
- (decl vec_uzp1 (Reg Reg VectorSize) Reg)
4140
- (rule (vec_uzp1 rn rm size) (vec_rrr (VecALUOp.Uzp1) rn rm size))
4141
-
4142
- ;; Helper for emitting the `uzp2` instruction
4143
- (decl vec_uzp2 (Reg Reg VectorSize) Reg)
4144
- (rule (vec_uzp2 rn rm size) (vec_rrr (VecALUOp.Uzp2) rn rm size))
4145
-
4146
- ;; Helper for emitting the `zip1` instruction
4147
- (decl vec_zip1 (Reg Reg VectorSize) Reg)
4148
- (rule (vec_zip1 rn rm size) (vec_rrr (VecALUOp.Zip1) rn rm size))
4149
-
4150
- ;; Helper for emitting the `zip2` instruction
4151
- (decl vec_zip2 (Reg Reg VectorSize) Reg)
4152
- (rule (vec_zip2 rn rm size) (vec_rrr (VecALUOp.Zip2) rn rm size))
4153
-
4154
- ;; Helper for emitting the `trn1` instruction
4155
- (decl vec_trn1 (Reg Reg VectorSize) Reg)
4156
- (rule (vec_trn1 rn rm size) (vec_rrr (VecALUOp.Trn1) rn rm size))
4157
-
4158
- ;; Helper for emitting the `trn2` instruction
4159
- (decl vec_trn2 (Reg Reg VectorSize) Reg)
4160
- (rule (vec_trn2 rn rm size) (vec_rrr (VecALUOp.Trn2) rn rm size))
4161
-
4162
- ;; Helper for creating a zero value `ASIMDMovModImm` immediate.
4163
- (decl asimd_mov_mod_imm_zero (ScalarSize) ASIMDMovModImm)
4164
- (extern constructor asimd_mov_mod_imm_zero asimd_mov_mod_imm_zero)
4165
-
4166
- ;; Helper for fallibly creating an `ASIMDMovModImm` immediate from its parts.
4167
- (decl pure partial asimd_mov_mod_imm_from_u64 (u64 ScalarSize) ASIMDMovModImm)
4168
- (extern constructor asimd_mov_mod_imm_from_u64 asimd_mov_mod_imm_from_u64)
4169
-
4170
- ;; Helper for fallibly creating an `ASIMDFPModImm` immediate from its parts.
4171
- (decl pure partial asimd_fp_mod_imm_from_u64 (u64 ScalarSize) ASIMDFPModImm)
4172
- (extern constructor asimd_fp_mod_imm_from_u64 asimd_fp_mod_imm_from_u64)
4173
-
4174
- ;; Helper for creating a `VecDupFPImm` instruction
4175
- (decl vec_dup_fp_imm (ASIMDFPModImm VectorSize) Reg)
4176
- (rule (vec_dup_fp_imm imm size)
4177
- (let ((dst WritableReg (temp_writable_reg $I8X16))
4178
- (_ Unit (emit (MInst.VecDupFPImm dst imm size))))
4179
- dst))
4180
-
4181
- ;; Helper for creating a `FpuLoad64` instruction
4182
- (decl fpu_load64 (AMode MemFlags) Reg)
4183
- (rule (fpu_load64 amode flags)
4184
- (let ((dst WritableReg (temp_writable_reg $I8X16))
4185
- (_ Unit (emit (MInst.FpuLoad64 dst amode flags))))
4186
- dst))
4187
-
4188
- ;; Helper for creating a `FpuLoad128` instruction
4189
- (decl fpu_load128 (AMode MemFlags) Reg)
4190
- (rule (fpu_load128 amode flags)
4191
- (let ((dst WritableReg (temp_writable_reg $I8X16))
4192
- (_ Unit (emit (MInst.FpuLoad128 dst amode flags))))
4193
- dst))