vertigo_vhdl 0.8.6 → 0.8.11

data/tests/parser_tests/test_microwatt_decode1_pp.vhd

@@ -1,138 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.common.all;
-use work.decode_types.all;
- 
-entity decode1 is
-  port(
-    clk : in std_ulogic;
-    rst : in std_ulogic;
-    stall_in : in std_ulogic;
-    flush_in : in std_ulogic;
-    f_in : in fetch2todecode1type;
-    d_out : out decode1todecode2type);
-end entity decode1;
- 
-architecture behaviour of decode1 is
-  signal r : decode1todecode2type;
-  signal rin : decode1todecode2type;
-   
-  subtype major_opcode_t is unsigned(5 downto 0);
-   
-  type major_rom_array_t is array(range 0 to 63) of decode_rom_t;
-   
-  type minor_valid_array_t is array(range 0 to 1023) of std_ulogic;
-   
-  type op_19_subop_array_t is array(range 0 to 7) of decode_rom_t;
-   
-  type op_30_subop_array_t is array(range 0 to 15) of decode_rom_t;
-   
-  type op_31_subop_array_t is array(range 0 to 1023) of decode_rom_t;
-   
-  type minor_rom_array_2_t is array(range 0 to 3) of decode_rom_t;
-  constant illegal_inst : decode_rom_t := (alu,op_illegal,none,none,none,none,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','1');
-  constant major_decode_rom_array : major_rom_array_t := (12 => (alu,op_add,ra,const_si,none,rt,'0','0','0','0',zero,'1',none,'0','0','0','0','0','0',none,'0','0'),13 => (alu,op_add,ra,const_si,none,rt,'0','0','0','0',zero,'1',none,'0','0','0','0','0','0',one,'0','0'),14 => (alu,op_add,ra_or_zero,const_si,none,rt,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','0'),15 => (alu,op_add,ra_or_zero,const_si_hi,none,rt,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','0'),28 => (alu,op_and,none,const_ui,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',one,'0','0'),29 => (alu,op_and,none,const_ui_hi,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',one,'0','0'),18 => (alu,op_b,none,const_li,none,none,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'1','0'),16 => (alu,op_bc,spr,const_bd,none,spr,'1','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'1','0'),11 => (alu,op_cmp,ra,const_si,none,none,'0','1','1','0',one,'0',none,'0','0','0','0','0','1',none,'0','0'),10 => (alu,op_cmp,ra,const_ui,none,none,'0','1','1','0',one,'0',none,'0','0','0','0','0','0',none,'0','0'),34 => (ldst,op_load,ra_or_zero,const_si,none,rt,'0','0','0','0',zero,'0',is1b,'0','0','0','0','0','0',none,'0','0'),35 => (ldst,op_load,ra_or_zero,const_si,none,rt,'0','0','0','0',zero,'0',is1b,'0','0','1','0','0','0',none,'0','0'),42 => (ldst,op_load,ra_or_zero,const_si,none,rt,'0','0','0','0',zero,'0',is2b,'0','1','0','0','0','0',none,'0','0'),43 => (ldst,op_load,ra_or_zero,const_si,none,rt,'0','0','0','0',zero,'0',is2b,'0','1','1','0','0','0',none,'0','0'),40 => (ldst,op_load,ra_or_zero,const_si,none,rt,'0','0','0','0',zero,'0',is2b,'0','0','0','0','0','0',none,'0','0'),41 => (ldst,op_load,ra_or_zero,const_si,none,rt,'0','0','0','0',zero,'0',is2b,'0','0','1','0','0','0',none,'0','0'),32 => (ldst,op_load,ra_or_zero,const_si,none,rt,'0','0','0','0',zero,'0',is4b,'0','0','0','0','0','0',none,'0','0'),33 => (ldst,op_load,ra_or_zero,const_si,none,rt,'0','0','0','0',zero,'0',is4b,'0','0','1','0','0','0',none,'0','0'),7 => (alu,op_mul_l64,ra,const_si,none,rt,'0','1','0','0',zero,'0',none,'0','0','0','0','0','1',none,'0','0'),24 => (alu,op_or,none,const_ui,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','0'),25 => (alu,op_or,none,const_ui_hi,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','0'),20 => (alu,op_rlc,ra,const_sh32,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','1','0',rc,'0','0'),21 => (alu,op_rlc,none,const_sh32,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','1','0',rc,'0','0'),23 => (alu,op_rlc,none,rb,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','1','0',rc,'0','0'),38 => (ldst,op_store,ra_or_zero,const_si,rs,none,'0','0','0','0',zero,'0',is1b,'0','0','0','0','0','0',none,'0','0'),39 => (ldst,op_store,ra_or_zero,const_si,rs,none,'0','0','0','0',zero,'0',is1b,'0','0','1','0','0','0',none,'0','0'),44 => (ldst,op_store,ra_or_zero,const_si,rs,none,'0','0','0','0',zero,'0',is2b,'0','0','0','0','0','0',none,'0','0'),45 => (ldst,op_store,ra_or_zero,const_si,rs,none,'0','0','0','0',zero,'0',is2b,'0','0','1','0','0','0',none,'0','0'),36 => (ldst,op_store,ra_or_zero,const_si,rs,none,'0','0','0','0',zero,'0',is4b,'0','0','0','0','0','0',none,'0','0'),37 => (ldst,op_store,ra_or_zero,const_si,rs,none,'0','0','0','0',zero,'0',is4b,'0','0','1','0','0','0',none,'0','0'),8 => (alu,op_add,ra,const_si,none,rt,'0','0','1','0',one,'1',none,'0','0','0','0','0','0',none,'0','0'),2 => (alu,op_tdi,ra,const_si,none,none,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','1'),26 => (alu,op_xor,none,const_ui,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','0'),27 => (alu,op_xor,none,const_ui_hi,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','0'),others => illegal_inst);
-  constant decode_op_19_valid : minor_valid_array_t := (2#0000000010# => '1',2#0000100010# => '1',2#0001000010# => '1',2#0001100010# => '1',2#0010000010# => '1',2#0010100010# => '1',2#0011000010# => '1',2#0011100010# => '1',2#0100000010# => '1',2#0100100010# => '1',2#0101000010# => '1',2#0101100010# => '1',2#0110000010# => '1',2#0110100010# => '1',2#0111000010# => '1',2#0111100010# => '1',2#1000000010# => '1',2#1000100010# => '1',2#1001000010# => '1',2#1001100010# => '1',2#1010000010# => '1',2#1010100010# => '1',2#1011000010# => '1',2#1011100010# => '1',2#1100000010# => '1',2#1100100010# => '1',2#1101000010# => '1',2#1101100010# => '1',2#1110000010# => '1',2#1110100010# => '1',2#1111000010# => '1',2#1111100010# => '1',2#1000010000# => '1',2#0000010000# => '1',2#1000110000# => '0',2#0100000001# => '1',2#0010000001# => '1',2#0100100001# => '1',2#0011100001# => '1',2#0000100001# => '1',2#0111000001# => '1',2#0110100001# => '1',2#0011000001# => '1',2#0010010110# => '1',2#0000000000# => '1',2#0000010010# => '1',others => '0');
-  constant decode_op_19_array : op_19_subop_array_t := (2#000# => (alu,op_mcrf,none,none,none,none,'1','1','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','0'),2#001# => (alu,op_illegal,none,none,none,none,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','1'),2#100# => (alu,op_bcreg,spr,spr,none,spr,'1','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'1','0'),2#111# => (alu,op_isync,none,none,none,none,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','1'),2#101# => (alu,op_rfid,spr,spr,none,none,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','0'),others => illegal_inst);
-  constant decode_op_30_array : op_30_subop_array_t := (2#0100# => (alu,op_rlc,none,const_sh,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0101# => (alu,op_rlc,none,const_sh,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0000# => (alu,op_rlcl,none,const_sh,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0001# => (alu,op_rlcl,none,const_sh,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0010# => (alu,op_rlcr,none,const_sh,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0011# => (alu,op_rlcr,none,const_sh,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0110# => (alu,op_rlc,ra,const_sh,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0111# => (alu,op_rlc,ra,const_sh,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#1000# => (alu,op_rlcl,none,rb,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#1001# => (alu,op_rlcr,none,rb,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),others => illegal_inst);
-  constant decode_op_31_array : op_31_subop_array_t := (2#0100001010# => (alu,op_add,ra,rb,none,rt,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#1100001010# => (alu,op_add,ra,rb,none,rt,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0000001010# => (alu,op_add,ra,rb,none,rt,'0','0','0','0',zero,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#1000001010# => (alu,op_add,ra,rb,none,rt,'0','0','0','0',zero,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#0010001010# => (alu,op_add,ra,rb,none,rt,'0','0','0','0',ca,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#1010001010# => (alu,op_add,ra,rb,none,rt,'0','0','0','0',ca,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#0011101010# => (alu,op_add,ra,const_m1,none,rt,'0','0','0','0',ca,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#1011101010# => (alu,op_add,ra,const_m1,none,rt,'0','0','0','0',ca,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#0011001010# => (alu,op_add,ra,none,none,rt,'0','0','0','0',ca,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#1011001010# => (alu,op_add,ra,none,none,rt,'0','0','0','0',ca,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#0000011100# => (alu,op_and,none,rb,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0000111100# => (alu,op_and,none,rb,rs,ra,'0','0','1','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0000000000# => (alu,op_cmp,ra,rb,none,none,'0','1','1','0',one,'0',none,'0','0','0','0','0','1',none,'0','0'),2#0111111100# => (alu,op_cmpb,none,rb,rs,ra,'0','1','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','0'),2#0000100000# => (alu,op_cmp,ra,rb,none,none,'0','1','1','0',one,'0',none,'0','0','0','0','0','0',none,'0','0'),2#0000111010# => (alu,op_cntz,none,none,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0000011010# => (alu,op_cntz,none,none,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','1','0',rc,'0','0'),2#1000111010# => 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(ldst,op_load,ra_or_zero,rb,none,rt,'0','0','0','0',zero,'0',is8b,'0','0','0','0','0','0',none,'0','0'),2#0000110101# => (ldst,op_load,ra_or_zero,rb,none,rt,'0','0','0','0',zero,'0',is8b,'0','0','1','0','0','0',none,'0','0'),2#0000010101# => (ldst,op_load,ra_or_zero,rb,none,rt,'0','0','0','0',zero,'0',is8b,'0','0','0','0','0','0',none,'0','0'),2#0001110100# => (ldst,op_load,ra_or_zero,rb,none,rt,'0','0','0','0',zero,'0',is2b,'0','0','0','1','0','0',none,'0','0'),2#0101110111# => (ldst,op_load,ra_or_zero,rb,none,rt,'0','0','0','0',zero,'0',is2b,'0','1','1','0','0','0',none,'0','0'),2#0101010111# => (ldst,op_load,ra_or_zero,rb,none,rt,'0','0','0','0',zero,'0',is2b,'0','1','0','0','0','0',none,'0','0'),2#1100010110# => (ldst,op_load,ra_or_zero,rb,none,rt,'0','0','0','0',zero,'0',is2b,'1','0','0','0','0','0',none,'0','0'),2#1100110101# => (ldst,op_load,ra_or_zero,rb,none,rt,'0','0','0','0',zero,'0',is2b,'0','0','0','0','0','0',none,'0','0'),2#0100110111# => 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(alu,op_mul_h64,ra,rb,none,rt,'0','1','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#1001001011# => (alu,op_mul_h32,ra,rb,none,rt,'0','1','0','0',zero,'0',none,'0','0','0','0','1','1',rc,'0','0'),2#1000001011# => (alu,op_mul_h32,ra,rb,none,rt,'0','1','0','0',zero,'0',none,'0','0','0','0','1','0',rc,'0','0'),2#0011101001# => (alu,op_mul_l64,ra,rb,none,rt,'0','1','0','0',zero,'0',none,'0','0','0','0','0','1',rc,'0','0'),2#1011101001# => (alu,op_mul_l64,ra,rb,none,rt,'0','1','0','0',zero,'0',none,'0','0','0','0','0','1',rc,'0','0'),2#0011101011# => (alu,op_mul_l64,ra,rb,none,rt,'0','1','0','0',zero,'0',none,'0','0','0','0','1','1',rc,'0','0'),2#1011101011# => (alu,op_mul_l64,ra,rb,none,rt,'0','1','0','0',zero,'0',none,'0','0','0','0','1','1',rc,'0','0'),2#0111011100# => (alu,op_and,none,rb,rs,ra,'0','0','0','1',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0001101000# => (alu,op_add,ra,none,none,rt,'0','0','1','0',one,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#1001101000# => (alu,op_add,ra,none,none,rt,'0','0','1','0',one,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0001111100# => (alu,op_or,none,rb,rs,ra,'0','0','0','1',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0110111100# => (alu,op_or,none,rb,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0110011100# => (alu,op_or,none,rb,rs,ra,'0','0','1','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0001111010# => (alu,op_popcnt,none,none,rs,ra,'0','0','0','0',zero,'0',is1b,'0','0','0','0','0','0',none,'0','0'),2#0111111010# => (alu,op_popcnt,none,none,rs,ra,'0','0','0','0',zero,'0',is8b,'0','0','0','0','0','0',none,'0','0'),2#0101111010# => (alu,op_popcnt,none,none,rs,ra,'0','0','0','0',zero,'0',is4b,'0','0','0','0','0','0',none,'0','0'),2#0010111010# => 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(alu,op_shr,none,const_sh32,rs,ra,'0','0','0','0',zero,'1',none,'0','0','0','0','1','1',rc,'0','0'),2#1000011011# => (alu,op_shr,none,rb,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#1000011000# => (alu,op_shr,none,rb,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','1','0',rc,'0','0'),2#1111010101# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is1b,'0','0','0','0','0','0',none,'0','0'),2#1010110110# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is1b,'0','0','0','1','0','0',one,'0','0'),2#0011110111# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is1b,'0','0','1','0','0','0',none,'0','0'),2#0011010111# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is1b,'0','0','0','0','0','0',none,'0','0'),2#1010010100# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is8b,'1','0','0','0','0','0',none,'0','0'),2#1111110101# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is8b,'0','0','0','0','0','0',none,'0','0'),2#0011010110# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is8b,'0','0','0','1','0','0',one,'0','0'),2#0010110101# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is8b,'0','0','1','0','0','0',none,'0','0'),2#0010010101# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is8b,'0','0','0','0','0','0',none,'0','0'),2#1110010110# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is2b,'1','0','0','0','0','0',none,'0','0'),2#1110110101# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is2b,'0','0','0','0','0','0',none,'0','0'),2#1011010110# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is2b,'0','0','0','1','0','0',one,'0','0'),2#0110110111# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is2b,'0','0','1','0','0','0',none,'0','0'),2#0110010111# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is2b,'0','0','0','0','0','0',none,'0','0'),2#1010010110# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is4b,'1','0','0','0','0','0',none,'0','0'),2#1110010101# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is4b,'0','0','0','0','0','0',none,'0','0'),2#0010010110# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is4b,'0','0','0','1','0','0',one,'0','0'),2#0010110111# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is4b,'0','0','1','0','0','0',none,'0','0'),2#0010010111# => (ldst,op_store,ra_or_zero,rb,rs,none,'0','0','0','0',zero,'0',is4b,'0','0','0','0','0','0',none,'0','0'),2#0000101000# => (alu,op_add,ra,rb,none,rt,'0','0','1','0',one,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#1000101000# => (alu,op_add,ra,rb,none,rt,'0','0','1','0',one,'0',none,'0','0','0','0','0','0',rc,'0','0'),2#0000001000# => (alu,op_add,ra,rb,none,rt,'0','0','1','0',one,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#1000001000# => (alu,op_add,ra,rb,none,rt,'0','0','1','0',one,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#0010001000# => (alu,op_add,ra,rb,none,rt,'0','0','1','0',ca,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#1010001000# => (alu,op_add,ra,rb,none,rt,'0','0','1','0',ca,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#0011101000# => (alu,op_add,ra,const_m1,none,rt,'0','0','1','0',ca,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#1011101000# => (alu,op_add,ra,const_m1,none,rt,'0','0','1','0',ca,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#0011001000# => (alu,op_add,ra,none,none,rt,'0','0','1','0',ca,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#1011001000# => (alu,op_add,ra,none,none,rt,'0','0','1','0',ca,'1',none,'0','0','0','0','0','0',rc,'0','0'),2#1001010110# => (alu,op_nop,none,none,none,none,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','1'),2#0000000100# => (alu,op_tw,ra,rb,none,none,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','1'),2#0100111100# => (alu,op_xor,none,rb,rs,ra,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',rc,'0','0'),others => illegal_inst);
-  constant decode_op_58_array : minor_rom_array_2_t := (0 => (ldst,op_load,ra_or_zero,const_ds,none,rt,'0','0','0','0',zero,'0',is8b,'0','0','0','0','0','0',none,'0','1'),1 => (ldst,op_load,ra_or_zero,const_ds,none,rt,'0','0','0','0',zero,'0',is8b,'0','0','1','0','0','0',none,'0','1'),2 => (ldst,op_load,ra_or_zero,const_ds,none,rt,'0','0','0','0',zero,'0',is4b,'0','1','0','0','0','0',none,'0','1'),others => decode_rom_init);
-  constant decode_op_62_array : minor_rom_array_2_t := (0 => (ldst,op_store,ra_or_zero,const_ds,rs,none,'0','0','0','0',zero,'0',is8b,'0','0','0','0','0','0',none,'0','1'),1 => (ldst,op_store,ra_or_zero,const_ds,rs,none,'0','0','0','0',zero,'0',is8b,'0','0','1','0','0','0',none,'0','1'),others => decode_rom_init);
-  constant attn_instr : decode_rom_t := (alu,op_attn,none,none,none,none,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','1');
-  constant nop_instr : decode_rom_t := (alu,op_nop,none,none,none,none,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','0');
-  constant sc_instr : decode_rom_t := (alu,op_sc,none,none,none,none,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','0');
-  constant sim_cfg_instr : decode_rom_t := (alu,op_sim_config,none,none,none,rt,'0','0','0','0',zero,'0',none,'0','0','0','0','0','0',none,'0','1');
-begin
- 
-   
-  decode1_0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      if rst = '1' or flush_in = '1' or stall_in = '0' then
-        r <= rin;
-      end if;
-    end if;
-  end process;
-   
-  decode1_1 : process(all)
-    variable v : decode1todecode2type;
-    variable majorop : major_opcode_t;
-    variable op_19_bits : std_ulogic_vector(2 downto 0);
-  begin
-    v := r;
-    v.valid := f_in.valid;
-    v.nia := f_in.nia;
-    v.insn := f_in.insn;
-    v.stop_mark := f_in.stop_mark;
-    v.ispr1 := (others => '0');
-    v.ispr2 := (others => '0');
-    if f_in.valid = '1' then
-      report "decode insn " & to_hstring(f_in.insn) & " at " & to_hstring(f_in.nia);
-    end if;
-    majorop := unsigned(f_in.insn(31 downto 26));
-    if majorop = "011111" then
-      v.decode := decode_op_31_array(to_integer(unsigned(f_in.insn(10 downto 1))));
-    elsif majorop = "010011" then
-      if decode_op_19_valid(to_integer(unsigned(f_in.insn(10 downto 1)))) = '0' then
-        report "op 19 illegal subcode";
-        v.decode := illegal_inst;
-      else
-        op_19_bits := f_in.insn(5) & f_in.insn(3) & f_in.insn(2);
-        v.decode := decode_op_19_array(to_integer(unsigned(op_19_bits)));
-        report "op 19 sub " & to_hstring(op_19_bits);
-      end if;
-    elsif majorop = "011110" then
-      v.decode := decode_op_30_array(to_integer(unsigned(f_in.insn(4 downto 1))));
-    elsif majorop = "111010" then
-      v.decode := decode_op_58_array(to_integer(unsigned(f_in.insn(1 downto 0))));
-    elsif majorop = "111110" then
-      v.decode := decode_op_62_array(to_integer(unsigned(f_in.insn(1 downto 0))));
-    elsif std_match(f_in.insn,"01100000000000000000000000000000") then
-      report "ppc_nop";
-      v.decode := nop_instr;
-    elsif std_match(f_in.insn,"010001--------------0000000---1-") then
-      report "ppc_sc";
-      v.decode := sc_instr;
-    elsif std_match(f_in.insn,"000001---------------0000000011-") then
-      report "ppc_sim_config";
-      v.decode := sim_cfg_instr;
-    elsif std_match(f_in.insn,"000000---------------0100000000-") then
-      report "ppc_attn";
-      v.decode := attn_instr;
-    else
-      v.decode := major_decode_rom_array(to_integer(majorop));
-    end if;
-    if v.decode.insn_type = op_bc or v.decode.insn_type = op_bcreg then
-      if f_in.insn(23) = '0' then
-        v.ispr1 := fast_spr_num(spr_ctr);
-      end if;
-      if v.decode.insn_type = op_bcreg then
-        if f_in.insn(10) = '0' then
-          v.ispr2 := fast_spr_num(spr_lr);
-        else
-          v.ispr2 := fast_spr_num(spr_ctr);
-        end if;
-      end if;
-    elsif v.decode.insn_type = op_mfspr or v.decode.insn_type = op_mtspr then
-      v.ispr1 := fast_spr_num(decode_spr_num(f_in.insn));
-      if is_fast_spr(v.ispr1) = '0' then
-        v.decode.sgl_pipe := '1';
-      end if;
-    elsif v.decode.insn_type = op_rfid then
-      report "ppc rfid";
-      v.ispr1 := fast_spr_num(spr_srr0);
-      v.ispr2 := fast_spr_num(spr_srr1);
-    end if;
-    if flush_in = '1' then
-      v.valid := '0';
-    end if;
-    if rst = '1' then
-      v := decode1todecode2init;
-    end if;
-    rin <= v;
-    d_out <= r;
-  end process;
-end behaviour;

data/tests/parser_tests/test_microwatt_decode2_pp.vhd

@@ -1,300 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.decode_types.all;
-use work.common.all;
-use work.helpers.all;
-use work.insn_helpers.all;
- 
-entity decode2 is
-  generic(
-    ex1_bypass : booleantrue := true);
-  port(
-    clk : in std_ulogic;
-    rst : in std_ulogic;
-    complete_in : in std_ulogic;
-    stall_in : in std_ulogic;
-    stall_out : out std_ulogic;
-    stopped_out : out std_ulogic;
-    flush_in : in std_ulogic;
-    d_in : in decode1todecode2type;
-    e_out : out decode2toexecute1type;
-    r_in : in registerfiletodecode2type;
-    r_out : out decode2toregisterfiletype;
-    c_in : in crfiletodecode2type;
-    c_out : out decode2tocrfiletype);
-end entity decode2;
- 
-architecture behaviour of decode2 is
-   
-  type reg_type is record
-    e : decode2toexecute1type;
-  end record;
-  signal r : reg_type;
-  signal rin : reg_type;
-   
-  type decode_input_reg_t is record
-    reg_valid : std_ulogic;
-    reg : gspr_index_t;
-    data : std_ulogic_vector(63 downto 0);
-  end record;
-   
-  type decode_output_reg_t is record
-    reg_valid : std_ulogic;
-    reg : gspr_index_t;
-  end record;
-   
-  function decode_input_reg_a(t : input_reg_a_t;insn_in : std_ulogic_vector(31 downto 0);reg_data : std_ulogic_vector(63 downto 0);ispr : gspr_index_t) return decode_input_reg_t is
-  begin
-    if t = ra or (t = ra_or_zero and insn_ra(insn_in) /= "00000") then
-      assert is_fast_spr(ispr) = '0'
-        report "decode a says gpr but ispr says spr:" & to_hstring(ispr) severity failure;
-      return ('1',gpr_to_gspr(insn_ra(insn_in)),reg_data);
-    elsif t = spr then
-      assert is_fast_spr(ispr) = '1' or ispr = "000000"
-        report "decode a says spr but ispr is invalid:" & to_hstring(ispr) severity failure;
-      return (is_fast_spr(ispr),ispr,reg_data);
-    else
-      return ('0',(others => '0'),(others => '0'));
-    end if;
-  end function decode_input_reg_a;
-   
-  function decode_input_reg_b(t : input_reg_b_t;insn_in : std_ulogic_vector(31 downto 0);reg_data : std_ulogic_vector(63 downto 0);ispr : gspr_index_t) return decode_input_reg_t is
-    variable ret : decode_input_reg_t;
-  begin
-    case t is
-      when rb =>
-        assert is_fast_spr(ispr) = '0'
-          report "decode b says gpr but ispr says spr:" & to_hstring(ispr) severity failure;
-        ret := ('1',gpr_to_gspr(insn_rb(insn_in)),reg_data);
-      when const_ui =>
-        ret := ('0',(others => '0'),std_ulogic_vector(resize(unsigned(insn_ui(insn_in)),64)));
-      when const_si =>
-        ret := ('0',(others => '0'),std_ulogic_vector(resize(signed(insn_si(insn_in)),64)));
-      when const_si_hi =>
-        ret := ('0',(others => '0'),std_ulogic_vector(resize(signed(insn_si(insn_in)) & x"0000",64)));
-      when const_ui_hi =>
-        ret := ('0',(others => '0'),std_ulogic_vector(resize(unsigned(insn_si(insn_in)) & x"0000",64)));
-      when const_li =>
-        ret := ('0',(others => '0'),std_ulogic_vector(resize(signed(insn_li(insn_in)) & "00",64)));
-      when const_bd =>
-        ret := ('0',(others => '0'),std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00",64)));
-      when const_ds =>
-        ret := ('0',(others => '0'),std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00",64)));
-      when const_m1 =>
-        ret := ('0',(others => '0'),x"ffffffffffffffff");
-      when const_sh =>
-        ret := ('0',(others => '0'),x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11));
-      when const_sh32 =>
-        ret := ('0',(others => '0'),x"00000000000000" & "000" & insn_in(15 downto 11));
-      when spr =>
-        assert is_fast_spr(ispr) = '1' or ispr = "000000"
-          report "decode b says spr but ispr is invalid:" & to_hstring(ispr) severity failure;
-        ret := (is_fast_spr(ispr),ispr,reg_data);
-      when none =>
-        ret := ('0',(others => '0'),(others => '0'));
-    end case;
-    return ret;
-  end function decode_input_reg_b;
-   
-  function decode_input_reg_c(t : input_reg_c_t;insn_in : std_ulogic_vector(31 downto 0);reg_data : std_ulogic_vector(63 downto 0)) return decode_input_reg_t is
-  begin
-    case t is
-      when rs =>
-        return ('1',gpr_to_gspr(insn_rs(insn_in)),reg_data);
-      when none =>
-        return ('0',(others => '0'),(others => '0'));
-    end case;
-  end function decode_input_reg_c;
-   
-  function decode_output_reg(t : output_reg_a_t;insn_in : std_ulogic_vector(31 downto 0);ispr : gspr_index_t) return decode_output_reg_t is
-  begin
-    case t is
-      when rt =>
-        return ('1',gpr_to_gspr(insn_rt(insn_in)));
-      when ra =>
-        return ('1',gpr_to_gspr(insn_ra(insn_in)));
-      when spr =>
-        assert is_fast_spr(ispr) = '1' or ispr = "000000"
-          report "decode b says spr but ispr is invalid:" & to_hstring(ispr) severity failure;
-        return (is_fast_spr(ispr),ispr);
-      when none =>
-        return ('0',"000000");
-    end case;
-  end function decode_output_reg;
-   
-  function decode_rc(t : rc_t;insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
-  begin
-    case t is
-      when rc =>
-        return insn_rc(insn_in);
-      when one =>
-        return '1';
-      when none =>
-        return '0';
-    end case;
-  end function decode_rc;
-   
-  function decode_oe(t : rc_t;insn_in : std_ulogic_vector(31 downto 0)) return std_ulogic is
-  begin
-    case t is
-      when rc =>
-        return insn_oe(insn_in);
-      when others =>
-        return '0';
-    end case;
-  end function decode_oe;
-  signal control_valid_in : std_ulogic;
-  signal control_valid_out : std_ulogic;
-  signal control_sgl_pipe : std_logic;
-  signal gpr_write_valid : std_ulogic;
-  signal gpr_write : gspr_index_t;
-  signal gpr_bypassable : std_ulogic;
-  signal gpr_a_read_valid : std_ulogic;
-  signal gpr_a_read : gspr_index_t;
-  signal gpr_a_bypass : std_ulogic;
-  signal gpr_b_read_valid : std_ulogic;
-  signal gpr_b_read : gspr_index_t;
-  signal gpr_b_bypass : std_ulogic;
-  signal gpr_c_read_valid : std_ulogic;
-  signal gpr_c_read : gpr_index_t;
-  signal gpr_c_bypass : std_ulogic;
-  signal cr_write_valid : std_ulogic;
-begin
- 
-  control_0 : entity work.control
-    port map(
-      clk => clk,
-      rst => rst,
-      complete_in => complete_in,
-      valid_in => control_valid_in,
-      stall_in => stall_in,
-      flush_in => flush_in,
-      sgl_pipe_in => control_sgl_pipe,
-      stop_mark_in => d_in.stop_mark,
-      gpr_write_valid_in => gpr_write_valid,
-      gpr_write_in => gpr_write,
-      gpr_bypassable => gpr_bypassable,
-      gpr_a_read_valid_in => gpr_a_read_valid,
-      gpr_a_read_in => gpr_a_read,
-      gpr_b_read_valid_in => gpr_b_read_valid,
-      gpr_b_read_in => gpr_b_read,
-      gpr_c_read_valid_in => gpr_c_read_valid,
-      gpr_c_read_in => gpr_c_read,
-      cr_read_in => d_in.decode.input_cr,
-      cr_write_in => cr_write_valid,
-      valid_out => control_valid_out,
-      stall_out => stall_out,
-      stopped_out => stopped_out,
-      gpr_bypass_a => gpr_a_bypass,
-      gpr_bypass_b => gpr_b_bypass,
-      gpr_bypass_c => gpr_c_bypass);
-   
-   
-  decode2_0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      if rin.e.valid = '1' then
-        report "execute " & to_hstring(rin.e.nia);
-      end if;
-      r <= rin;
-    end if;
-  end process;
-  r_out.read1_reg <= gpr_or_spr_to_gspr(insn_ra(d_in.insn),d_in.ispr1);
-  r_out.read2_reg <= gpr_or_spr_to_gspr(insn_rb(d_in.insn),d_in.ispr2);
-  r_out.read3_reg <= insn_rs(d_in.insn);
-  c_out.read <= d_in.decode.input_cr;
-   
-  decode2_1 : process(all)
-    variable v : reg_type;
-    variable mul_a : std_ulogic_vector(63 downto 0);
-    variable mul_b : std_ulogic_vector(63 downto 0);
-    variable decoded_reg_a : decode_input_reg_t;
-    variable decoded_reg_b : decode_input_reg_t;
-    variable decoded_reg_c : decode_input_reg_t;
-    variable decoded_reg_o : decode_output_reg_t;
-    variable length : std_ulogic_vector(3 downto 0);
-  begin
-    v := r;
-    v.e := decode2toexecute1init;
-    mul_a := (others => '0');
-    mul_b := (others => '0');
-    decoded_reg_a := decode_input_reg_a(d_in.decode.input_reg_a,d_in.insn,r_in.read1_data,d_in.ispr1);
-    decoded_reg_b := decode_input_reg_b(d_in.decode.input_reg_b,d_in.insn,r_in.read2_data,d_in.ispr2);
-    decoded_reg_c := decode_input_reg_c(d_in.decode.input_reg_c,d_in.insn,r_in.read3_data);
-    decoded_reg_o := decode_output_reg(d_in.decode.output_reg_a,d_in.insn,d_in.ispr1);
-    r_out.read1_enable <= decoded_reg_a.reg_valid;
-    r_out.read2_enable <= decoded_reg_b.reg_valid;
-    r_out.read3_enable <= decoded_reg_c.reg_valid;
-    case d_in.decode.length is
-      when is1b =>
-        length := "0001";
-      when is2b =>
-        length := "0010";
-      when is4b =>
-        length := "0100";
-      when is8b =>
-        length := "1000";
-      when none =>
-        length := "0000";
-    end case;
-    v.e.nia := d_in.nia;
-    v.e.insn_type := d_in.decode.insn_type;
-    v.e.read_reg1 := decoded_reg_a.reg;
-    v.e.read_data1 := decoded_reg_a.data;
-    v.e.bypass_data1 := gpr_a_bypass;
-    v.e.read_reg2 := decoded_reg_b.reg;
-    v.e.read_data2 := decoded_reg_b.data;
-    v.e.bypass_data2 := gpr_b_bypass;
-    v.e.read_data3 := decoded_reg_c.data;
-    v.e.bypass_data3 := gpr_c_bypass;
-    v.e.write_reg := decoded_reg_o.reg;
-    v.e.rc := decode_rc(d_in.decode.rc,d_in.insn);
-    if (d_in.decode.insn_type = op_mul_h32 or d_in.decode.insn_type = op_mul_h64) then
-      v.e.oe := decode_oe(d_in.decode.rc,d_in.insn);
-    end if;
-    v.e.cr := c_in.read_cr_data;
-    v.e.xerc := c_in.read_xerc_data;
-    v.e.invert_a := d_in.decode.invert_a;
-    v.e.invert_out := d_in.decode.invert_out;
-    v.e.input_carry := d_in.decode.input_carry;
-    v.e.output_carry := d_in.decode.output_carry;
-    v.e.is_32bit := d_in.decode.is_32bit;
-    v.e.is_signed := d_in.decode.is_signed;
-    if d_in.decode.lr = '1' then
-      v.e.lr := insn_lk(d_in.insn);
-    end if;
-    v.e.insn := d_in.insn;
-    v.e.data_len := length;
-    v.e.byte_reverse := d_in.decode.byte_reverse;
-    v.e.sign_extend := d_in.decode.sign_extend;
-    v.e.update := d_in.decode.update;
-    v.e.reserve := d_in.decode.reserve;
-    control_valid_in <= d_in.valid;
-    control_sgl_pipe <= d_in.decode.sgl_pipe;
-    gpr_write_valid <= decoded_reg_o.reg_valid;
-    gpr_write <= decoded_reg_o.reg;
-    gpr_bypassable <= '0';
-    if ex1_bypass and d_in.decode.unit = alu then
-      gpr_bypassable <= '1';
-    end if;
-    gpr_a_read_valid <= decoded_reg_a.reg_valid;
-    gpr_a_read <= decoded_reg_a.reg;
-    gpr_b_read_valid <= decoded_reg_b.reg_valid;
-    gpr_b_read <= decoded_reg_b.reg;
-    gpr_c_read_valid <= decoded_reg_c.reg_valid;
-    gpr_c_read <= gspr_to_gpr(decoded_reg_c.reg);
-    cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc,d_in.insn);
-    v.e.valid := control_valid_out;
-    if d_in.decode.unit = none then
-      v.e.insn_type := op_illegal;
-    end if;
-    if rst = '1' then
-      v.e := decode2toexecute1init;
-    end if;
-    rin <= v;
-    e_out <= r.e;
-  end process;
-end behaviour;

data/tests/parser_tests/test_microwatt_decode_types_pp.vhd

@@ -1,67 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
- 
-package decode_types is
-   
-  type insn_type_t is (op_illegal,op_nop,op_add,op_addpcis,op_and,op_attn,op_b,op_bc,op_bcreg,op_bperm,op_cmp,op_cmpb,op_cmpeqb,op_cmprb,op_cntz,op_crand,op_crandc,op_creqv,op_crnand,op_crnor,op_cror,op_crorc,op_crxor,op_darn,op_dcbf,op_dcbst,op_dcbt,op_dcbtst,op_dcbz,op_div,op_dive,op_exts,op_extswsli,op_icbi,op_icbt,op_isel,op_isync,op_load,op_store,op_maddhd,op_maddhdu,op_maddld,op_mcrf,op_mcrxr,op_mcrxrx,op_mfcr,op_mfmsr,op_mfspr,op_mod,op_mtcrf,op_mtmsrd,op_mtspr,op_mul_l64,op_mul_h64,op_mul_h32,op_or,op_popcnt,op_prty,op_rfid,op_rlc,op_rlcl,op_rlcr,op_sc,op_setb,op_shl,op_shr,op_sync,op_td,op_tdi,op_tw,op_twi,op_xor,op_sim_config);
-   
-  type input_reg_a_t is (none,ra,ra_or_zero,spr);
-   
-  type input_reg_b_t is (none,rb,const_ui,const_si,const_si_hi,const_ui_hi,const_li,const_bd,const_ds,const_m1,const_sh,const_sh32,spr);
-   
-  type input_reg_c_t is (none,rs);
-   
-  type output_reg_a_t is (none,rt,ra,spr);
-   
-  type rc_t is (none,one,rc);
-   
-  type carry_in_t is (zero,ca,one);
-  constant sh_offset : integer := 0;
-  constant mb_offset : integer := 1;
-  constant me_offset : integer := 1;
-  constant sh32_offset : integer := 0;
-  constant mb32_offset : integer := 1;
-  constant me32_offset : integer := 2;
-  constant fxm_offset : integer := 0;
-  constant bo_offset : integer := 0;
-  constant bi_offset : integer := 1;
-  constant bh_offset : integer := 2;
-  constant bf_offset : integer := 0;
-  constant l_offset : integer := 1;
-  constant too_offset : integer := 0;
-   
-  type unit_t is (none,alu,ldst);
-   
-  type length_t is (none,is1b,is2b,is4b,is8b);
-   
-  type decode_rom_t is record
-    unit : unit_t;
-    insn_type : insn_type_t;
-    input_reg_a : input_reg_a_t;
-    input_reg_b : input_reg_b_t;
-    input_reg_c : input_reg_c_t;
-    output_reg_a : output_reg_a_t;
-    input_cr : std_ulogic;
-    output_cr : std_ulogic;
-    invert_a : std_ulogic;
-    invert_out : std_ulogic;
-    input_carry : carry_in_t;
-    output_carry : std_ulogic;
-    length : length_t;
-    byte_reverse : std_ulogic;
-    sign_extend : std_ulogic;
-    update : std_ulogic;
-    reserve : std_ulogic;
-    is_32bit : std_ulogic;
-    is_signed : std_ulogic;
-    rc : rc_t;
-    lr : std_ulogic;
-    sgl_pipe : std_ulogic;
-  end record;
-  constant decode_rom_init : decode_rom_t := (unit => none,insn_type => op_illegal,input_reg_a => none,input_reg_b => none,input_reg_c => none,output_reg_a => none,input_cr => '0',output_cr => '0',invert_a => '0',invert_out => '0',input_carry => zero,output_carry => '0',length => none,byte_reverse => '0',sign_extend => '0',update => '0',reserve => '0',is_32bit => '0',is_signed => '0',rc => none,lr => '0',sgl_pipe => '0');
- 
-end decode_types;
- 
-package body decode_types is
-end decode_types;