vertigo_vhdl 0.8.6 → 0.8.11

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 67916f8023b4daaaa9e3b2ee7405a880bbcd71ad70733b087ec4e0d1f63ccc2d
-  data.tar.gz: df9ae80fb38ea82afbfa7bc79d128448dc979342770a28493061463cae623d3e
+  metadata.gz: 5f66142ff1aa2f02093dbc99c8cd22a78a44ae177d0ecaf41e1cc3289b505e80
+  data.tar.gz: 406108f6e1fc88d54cd96b38708772e7051788b8c9ab9417a15bef96326004e1
 SHA512:
-  metadata.gz: a13be7a1c2bfdd4ed210bceab2231700f409f1e1b274073631629bf20909298fe0989a2485a14b269ecfb5058c6c3df37a31ba9f880a8e7a7fd261e3b0524475
-  data.tar.gz: ec0ae03dfae2b65a5a7f7a03aacc80e43cac31517d20ec0668b0e7542894ca4335f6273f62aacfc4fa68fef3e2c3d4983c1dd716f2857212715112b73ae93e90
+  metadata.gz: 9c3f59eea1d1a2ca3ec6c22361bcd5eb54512b95a9b76e60465d6aa2749072d730fc0d79d28cfe0b2d11048f49a29f655d55aabc34cf6f0c8fcbd0c82b3f440c
+  data.tar.gz: a12214d7979e71a31172ce35fa67ac7ca3bbf69c4a3e8730acdeae20c451cb9344b3a2c1d567389db41ffa699a896db6244f8ec3fdd4f9d15600d9caf7ef857e

data/lib/vertigo/parser.rb

@@ -801,12 +801,25 @@ module Vertigo
       expect :if
       ret.cond=parse_expression
       expect :generate
-      if showNext.is_a?(:begin) # seems optional!
+      # maybe local declarations :
+      if showNext.is_a? [:signal,:constant]
+        while showNext.is_not_a?(:begin)
+          parse_decls
+        end
+      end
+
+      #...or simply "begin"
+      if showNext.is_a?(:begin)
         acceptIt
       end
-      ret.body=parse_concurrent_stmt
+      ret.body=body=Body.new
+
+      while !showNext.is_a?(:end)
+        body << parse_concurrent_stmt
+      end
       expect :end
       expect :generate
+      maybe :ident
       expect :semicolon
       ret
     end
@@ -818,16 +831,26 @@ module Vertigo
       expect :in
       ret.range=parse_discrete_range
       expect :generate
-      while showNext.is_not_a?(:begin)
-        parse_decls
+
+      # maybe local declarations :
+      if showNext.is_a? [:signal,:constant]
+        while showNext.is_not_a?(:begin)
+          parse_decls
+        end
+      end
+
+      #...or simply "begin"
+      if showNext.is_a?(:begin)
+        acceptIt
       end
       ret.body=body=Body.new
-      expect :begin
+
       while !showNext.is_a?(:end)
         body << parse_concurrent_stmt
       end
       expect :end
       expect :generate
+      maybe :ident
       expect :semicolon
       ret
     end

data/lib/vertigo/tb_generator.rb

@@ -1,23 +1,31 @@
 module Vertigo
 
   class TestBenchGenerator
+
     attr_accessor :ast
     attr_accessor :entity,:arch
     attr_accessor :clk,:rst
+    attr_accessor :options
+
     def initialize options={}
       @options=options
       @supplemental_libs_h=options[:supplemental_libs_h]||{}
     end
 
     def generate_from ast
-      @ast=ast
-      entity_arch=find_entity_arch()
-      detecting_clk_and_reset(entity_arch)
-      vhdl_tb=gen_code()
-      @tb_name=@entity_name+"_tb"
-      tb_filename=@tb_name+".vhd"
-      File.open(tb_filename,'w'){|f| f.puts vhdl_tb}
-      puts "=> generated testbench : #{tb_filename}"
+      begin
+        @ast=ast
+        entity_arch=find_entity_arch()
+        detecting_clk_and_reset(entity_arch)
+        vhdl_tb=gen_code()
+        @tb_name=@entity_name+"_tb"
+        tb_filename=@tb_name+".vhd"
+        File.open(tb_filename,'w'){|f| f.puts vhdl_tb}
+        puts "=> generated testbench : #{tb_filename}" unless options[:mute]
+        return tb_filename
+      rescue Exception => e
+        puts e.backtrace
+      end
     end
 
     def line n=80
@@ -109,7 +117,9 @@ module Vertigo
       code << line
       code << comment("Design Under Test")
       code << line
-      code << "dut : entity work.#{@entity_name}(#{@arch_name})"
+      str="dut : entity work.#{@entity_name}"
+      str+="(#{@arch_name})" if @arch_name
+      code << str
       code.indent=2
       code << "port map ("
       code.indent=4
@@ -141,7 +151,7 @@ module Vertigo
       code << "report \"waiting for asynchronous reset\";"
       code << "wait until #{@reset_name}='1';"
       code << "wait_cycles(10);"
-      code << "wait_cycles(10);"
+      code << "wait_cycles(200);"
       code << "report \"end of simulation\";"
       code << "running <= false;"
       code << "wait;"
@@ -157,28 +167,39 @@ module Vertigo
         puts msg="ERROR : no entity found"
         raise msg
       end
-      puts "=> found entity '#{entity.name.str}'"
+      puts "=> found entity '#{entity.name.str}'" unless options[:mute]
       @arch=ast.design_units.find{|du| du.is_a? Architecture}
       if @arch.nil?
-        puts msg="ERROR : no architecture found"
-        raise msg
+        puts msg="WARNING : no architecture found"
+      else
+        puts "=> found architecture '#{arch.name.str}'" unless options[:mute]
       end
 
-      puts "=> found architecture '#{arch.name.str}'"
       @entity_name=@entity.name.str
-      @arch_name=@arch.name.str
+      @arch_name=@arch.name.str if @arch
       [@entity,@arch]
     end
 
     def detecting_clk_and_reset entity_arch
-      puts "=> detecting clock and reset"
+      puts "=> detecting clock and reset" unless options[:mute]
       entity,arch=entity_arch
       inputs=entity.ports.select{|port| port.is_a?(Input)}
       @clk = inputs.sort_by{|input| levenshtein_distance(input.name.str,"clk")}.first
       @rst = inputs.sort_by{|input| levenshtein_distance(input.name.str,"reset_n")}.first
-      puts "\t-most probable clk   : #{@clk.name.str}"
-      puts "\t-most probable reset : #{@rst.name.str}"
+      puts "\t-most probable clk   : #{@clk.name.str}" unless options[:mute]
+      puts "\t-most probable reset : #{@rst.name.str}" unless options[:mute]
+
       @max_length_str=entity.ports.map{|port| port.name.str.size}.max
+
+      print "\t-validate [Y/n] ? "
+      answer=$stdin.gets.chomp
+      if answer=="n"
+        puts "ok, switching to 'clk' and 'reset_n'"
+        @reset_name="reset_n"
+        @clk_name="clk"
+        @excluded=[]
+        return
+      end
       @excluded=[@clk,@rst]
       @reset_name=@rst.name.str
       @clk_name=@clk.name.str

data/lib/vertigo/version.rb

@@ -1,3 +1,3 @@
 module Vertigo
-  VERSION="0.8.6"
+  VERSION="0.8.11"
 end

data/tests/parser_tests/test_adder_rca_vhdl93.vhd

@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture rca_vhdl_93 of adder is
+  signal co : std_logic_vector(N-1 downto 0);
+begin
+
+  gen_loop: for i in 0 to N-1 generate
+
+    bit0 : if i=0 generate
+      fa_0: entity work.fa(arch)
+      port map(
+        a  => a(0),
+        b  => b(0),
+        ci => '0',
+        s  => sum(0),
+        co => co(0)
+      );
+    end generate bit0;
+
+    other_bits : if i >0  generate
+      fa_i : entity work.fa(arch)
+      port map(
+        a  => a(i),
+        b  => b(i),
+        ci => co(i-1),
+        s  => sum(i),
+        co => co(i)
+      );
+    end generate other_bits;
+
+  end generate gen_loop;
+
+  carry <= co(N-1);
+
+end architecture;

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: vertigo_vhdl
 version: !ruby/object:Gem::Version
-  version: 0.8.6
+  version: 0.8.11
 platform: ruby
 authors:
 - Jean-Christophe Le Lann
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-03-23 00:00:00.000000000 Z
+date: 2021-11-02 00:00:00.000000000 Z
 dependencies: []
 description: A Ruby handwritten VHDL parser and utilities
 email: jean-christophe.le_lann@ensta-bretagne.fr
@@ -37,167 +37,86 @@ files:
 - lib/vertigo/visitor_vertigo_rkgen.rb
 - tests/ghdl_tests/fsm.vhd
 - tests/ghdl_tests/fsm_synth.vhd
-- tests/ghdl_tests/test_fsm.vhd
-- tests/parser_tests/else.vhd
-- tests/parser_tests/pingpong.vhd
 - tests/parser_tests/test_MUST_fail.vhd
 - tests/parser_tests/test_accelerator.vhd
-- tests/parser_tests/test_accelerator_pp.vhd
+- tests/parser_tests/test_adder_rca_vhdl93.vhd
 - tests/parser_tests/test_aggregate.vhd
-- tests/parser_tests/test_aggregate_pp.vhd
 - tests/parser_tests/test_archi_1.vhd
-- tests/parser_tests/test_archi_1_pp.vhd
 - tests/parser_tests/test_array_array_00.vhd
-- tests/parser_tests/test_array_array_00_pp.vhd
 - tests/parser_tests/test_array_urange.vhd
-- tests/parser_tests/test_array_urange_pp.vhd
 - tests/parser_tests/test_chu-1.vhd
-- tests/parser_tests/test_chu-1_pp.vhd
 - tests/parser_tests/test_concat.vhd
-- tests/parser_tests/test_concat_pp.vhd
 - tests/parser_tests/test_counter.vhd
-- tests/parser_tests/test_counter_pp.vhd
 - tests/parser_tests/test_de2.vhd
-- tests/parser_tests/test_de2_pp.vhd
 - tests/parser_tests/test_encode.vhd
-- tests/parser_tests/test_encode_pp.vhd
 - tests/parser_tests/test_fsm.vhd
-- tests/parser_tests/test_fsm_pp.vhd
 - tests/parser_tests/test_fsm_synth.vhd
-- tests/parser_tests/test_fsm_synth_pp.vhd
 - tests/parser_tests/test_function-01.vhd
-- tests/parser_tests/test_function-01_pp.vhd
 - tests/parser_tests/test_lfsr.vhd
-- tests/parser_tests/test_lfsr_pp.vhd
 - tests/parser_tests/test_microwatt_cache_ram.vhd
-- tests/parser_tests/test_microwatt_cache_ram_pp.vhd
 - tests/parser_tests/test_microwatt_common.vhd
-- tests/parser_tests/test_microwatt_common_pp.vhd
 - tests/parser_tests/test_microwatt_control.vhd
-- tests/parser_tests/test_microwatt_control_pp.vhd
 - tests/parser_tests/test_microwatt_core.vhd
 - tests/parser_tests/test_microwatt_core_debug.vhd
-- tests/parser_tests/test_microwatt_core_debug_pp.vhd
-- tests/parser_tests/test_microwatt_core_pp.vhd
 - tests/parser_tests/test_microwatt_core_tb.vhd
-- tests/parser_tests/test_microwatt_core_tb_pp.vhd
 - tests/parser_tests/test_microwatt_countzero.vhd
-- tests/parser_tests/test_microwatt_countzero_pp.vhd
 - tests/parser_tests/test_microwatt_countzero_tb.vhd
-- tests/parser_tests/test_microwatt_countzero_tb_pp.vhd
 - tests/parser_tests/test_microwatt_cr_file.vhd
-- tests/parser_tests/test_microwatt_cr_file_pp.vhd
 - tests/parser_tests/test_microwatt_cr_hazard.vhd
-- tests/parser_tests/test_microwatt_cr_hazard_pp.vhd
 - tests/parser_tests/test_microwatt_crhelpers.vhd
-- tests/parser_tests/test_microwatt_crhelpers_pp.vhd
 - tests/parser_tests/test_microwatt_dcache.vhd
-- tests/parser_tests/test_microwatt_dcache_pp.vhd
 - tests/parser_tests/test_microwatt_dcache_tb.vhd
-- tests/parser_tests/test_microwatt_dcache_tb_pp.vhd
 - tests/parser_tests/test_microwatt_decode1.vhd
-- tests/parser_tests/test_microwatt_decode1_pp.vhd
 - tests/parser_tests/test_microwatt_decode2.vhd
-- tests/parser_tests/test_microwatt_decode2_pp.vhd
 - tests/parser_tests/test_microwatt_decode_types.vhd
-- tests/parser_tests/test_microwatt_decode_types_pp.vhd
 - tests/parser_tests/test_microwatt_divider.vhd
-- tests/parser_tests/test_microwatt_divider_pp.vhd
 - tests/parser_tests/test_microwatt_divider_tb.vhd
-- tests/parser_tests/test_microwatt_divider_tb_pp.vhd
 - tests/parser_tests/test_microwatt_dmi_dtm_dummy.vhd
-- tests/parser_tests/test_microwatt_dmi_dtm_dummy_pp.vhd
 - tests/parser_tests/test_microwatt_dmi_dtm_tb.vhd
-- tests/parser_tests/test_microwatt_dmi_dtm_tb_pp.vhd
 - tests/parser_tests/test_microwatt_dmi_dtm_xilinx.vhd
-- tests/parser_tests/test_microwatt_dmi_dtm_xilinx_pp.vhd
 - tests/parser_tests/test_microwatt_execute1.vhd
-- tests/parser_tests/test_microwatt_execute1_pp.vhd
 - tests/parser_tests/test_microwatt_fetch1.vhd
-- tests/parser_tests/test_microwatt_fetch1_pp.vhd
 - tests/parser_tests/test_microwatt_fetch2.vhd
-- tests/parser_tests/test_microwatt_fetch2_pp.vhd
 - tests/parser_tests/test_microwatt_glibc_random.vhd
 - tests/parser_tests/test_microwatt_glibc_random_helpers.vhd
-- tests/parser_tests/test_microwatt_glibc_random_helpers_pp.vhd
-- tests/parser_tests/test_microwatt_glibc_random_pp.vhd
 - tests/parser_tests/test_microwatt_gpr_hazard.vhd
-- tests/parser_tests/test_microwatt_gpr_hazard_pp.vhd
 - tests/parser_tests/test_microwatt_helpers.vhd
-- tests/parser_tests/test_microwatt_helpers_pp.vhd
 - tests/parser_tests/test_microwatt_icache.vhd
-- tests/parser_tests/test_microwatt_icache_pp.vhd
 - tests/parser_tests/test_microwatt_icache_tb.vhd
-- tests/parser_tests/test_microwatt_icache_tb_pp.vhd
 - tests/parser_tests/test_microwatt_insn_helpers.vhd
-- tests/parser_tests/test_microwatt_insn_helpers_pp.vhd
 - tests/parser_tests/test_microwatt_loadstore1.vhd
-- tests/parser_tests/test_microwatt_loadstore1_pp.vhd
 - tests/parser_tests/test_microwatt_logical.vhd
-- tests/parser_tests/test_microwatt_logical_pp.vhd
 - tests/parser_tests/test_microwatt_multiply.vhd
-- tests/parser_tests/test_microwatt_multiply_pp.vhd
 - tests/parser_tests/test_microwatt_multiply_tb.vhd
-- tests/parser_tests/test_microwatt_multiply_tb_pp.vhd
 - tests/parser_tests/test_microwatt_plru.vhd
-- tests/parser_tests/test_microwatt_plru_pp.vhd
 - tests/parser_tests/test_microwatt_plru_tb.vhd
-- tests/parser_tests/test_microwatt_plru_tb_pp.vhd
 - tests/parser_tests/test_microwatt_ppc_fx_insns.vhd
-- tests/parser_tests/test_microwatt_ppc_fx_insns_pp.vhd
 - tests/parser_tests/test_microwatt_register_file.vhd
-- tests/parser_tests/test_microwatt_register_file_pp.vhd
 - tests/parser_tests/test_microwatt_rotator.vhd
-- tests/parser_tests/test_microwatt_rotator_pp.vhd
 - tests/parser_tests/test_microwatt_rotator_tb.vhd
-- tests/parser_tests/test_microwatt_rotator_tb_pp.vhd
 - tests/parser_tests/test_microwatt_sim_bram.vhd
 - tests/parser_tests/test_microwatt_sim_bram_helpers.vhd
-- tests/parser_tests/test_microwatt_sim_bram_helpers_pp.vhd
-- tests/parser_tests/test_microwatt_sim_bram_pp.vhd
 - tests/parser_tests/test_microwatt_sim_console.vhd
-- tests/parser_tests/test_microwatt_sim_console_pp.vhd
 - tests/parser_tests/test_microwatt_sim_jtag.vhd
-- tests/parser_tests/test_microwatt_sim_jtag_pp.vhd
 - tests/parser_tests/test_microwatt_sim_jtag_socket.vhd
-- tests/parser_tests/test_microwatt_sim_jtag_socket_pp.vhd
 - tests/parser_tests/test_microwatt_sim_uart.vhd
-- tests/parser_tests/test_microwatt_sim_uart_pp.vhd
 - tests/parser_tests/test_microwatt_soc.vhd
-- tests/parser_tests/test_microwatt_soc_pp.vhd
 - tests/parser_tests/test_microwatt_utils.vhd
-- tests/parser_tests/test_microwatt_utils_pp.vhd
 - tests/parser_tests/test_microwatt_wishbone_arbiter.vhd
-- tests/parser_tests/test_microwatt_wishbone_arbiter_pp.vhd
 - tests/parser_tests/test_microwatt_wishbone_bram_tb.vhd
-- tests/parser_tests/test_microwatt_wishbone_bram_tb_pp.vhd
 - tests/parser_tests/test_microwatt_wishbone_bram_wrapper.vhd
-- tests/parser_tests/test_microwatt_wishbone_bram_wrapper_pp.vhd
 - tests/parser_tests/test_microwatt_wishbone_debug_master.vhd
-- tests/parser_tests/test_microwatt_wishbone_debug_master_pp.vhd
 - tests/parser_tests/test_microwatt_wishbone_types.vhd
-- tests/parser_tests/test_microwatt_wishbone_types_pp.vhd
 - tests/parser_tests/test_microwatt_writeback.vhd
-- tests/parser_tests/test_microwatt_writeback_pp.vhd
 - tests/parser_tests/test_package-1.vhd
-- tests/parser_tests/test_package-1_pp.vhd
 - tests/parser_tests/test_precedence.vhd
-- tests/parser_tests/test_precedence_pp.vhd
 - tests/parser_tests/test_selected_sig.vhd
-- tests/parser_tests/test_selected_sig_pp.vhd
 - tests/parser_tests/test_slice.vhd
-- tests/parser_tests/test_slice_pp.vhd
 - tests/parser_tests/test_tb-00.vhd
-- tests/parser_tests/test_tb-00_pp.vhd
 - tests/parser_tests/test_type_decl_02.vhd
-- tests/parser_tests/test_type_decl_02_pp.vhd
 - tests/parser_tests/test_use.vhd
-- tests/parser_tests/test_use_pp.vhd
 - tests/parser_tests/test_while_1.vhd
-- tests/parser_tests/test_while_1_pp.vhd
 - tests/parser_tests/test_with-00.vhd
-- tests/parser_tests/test_with-00_pp.vhd
-- tests/tb_gen_tests/test_accelerator.vhd
 homepage: http://www.github.com/JC-LL/vertigo
 licenses:
 - GPL-2.0-only
@@ -217,7 +136,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.0.6
+rubygems_version: 3.2.3
 signing_key: 
 specification_version: 4
 summary: VHDL parser and utilities

data/tests/ghdl_tests/test_fsm.vhd

@@ -1,162 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-entity fsm is
-  port (
-    reset_n: in std_logic;
-    clk: in std_logic;
-    switches: in std_logic_vector (7 downto 0);
-    leds: out std_logic_vector (7 downto 0)
-  );
-end entity;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-architecture rtl of fsm is
-  signal wrap_reset_n: std_logic;
-  signal wrap_clk: std_logic;
-  signal wrap_switches: std_logic_vector (7 downto 0);
-  signal wrap_leds: std_logic_vector (7 downto 0);
-  signal state : std_logic_vector (2 downto 0);
-  signal state_c : std_logic_vector (2 downto 0);
-  signal n4_o : std_logic;
-  signal n9_q : std_logic_vector (2 downto 0);
-  signal n12_o : std_logic;
-  signal n14_o : std_logic_vector (2 downto 0);
-  signal n15_o : std_logic;
-  signal n17_o : std_logic_vector (2 downto 0);
-  signal n18_o : std_logic;
-  signal n20_o : std_logic_vector (2 downto 0);
-  signal n21_o : std_logic;
-  signal n23_o : std_logic_vector (2 downto 0);
-  signal n24_o : std_logic;
-  signal n26_o : std_logic_vector (2 downto 0);
-  signal n27_o : std_logic;
-  signal n29_o : std_logic_vector (2 downto 0);
-  signal n30_o : std_logic;
-  signal n32_o : std_logic_vector (2 downto 0);
-  signal n33_o : std_logic;
-  signal n35_o : std_logic_vector (2 downto 0);
-  signal n36_o : std_logic_vector (1 downto 0);
-  signal n37_o : std_logic_vector (2 downto 0);
-  signal n38_o : std_logic_vector (2 downto 0);
-  signal n39_o : std_logic;
-  signal n40_o : std_logic_vector (2 downto 0);
-  signal n44_o : std_logic;
-  signal n45_o : std_logic_vector (7 downto 0);
-  signal n48_o : std_logic;
-  signal n49_o : std_logic_vector (7 downto 0);
-  signal n52_o : std_logic;
-  signal n53_o : std_logic_vector (7 downto 0);
-  signal n56_o : std_logic;
-  signal n57_o : std_logic_vector (7 downto 0);
-  signal n60_o : std_logic;
-  signal n61_o : std_logic_vector (7 downto 0);
-  signal n64_o : std_logic;
-  signal n65_o : std_logic_vector (7 downto 0);
-  signal n68_o : std_logic;
-  signal n69_o : std_logic_vector (7 downto 0);
-begin
-  wrap_reset_n <= reset_n;
-  wrap_clk <= clk;
-  wrap_switches <= switches;
-  leds <= wrap_leds;
-  wrap_leds <= n45_o;
-  -- fsm.vhd:16:10
-  state <= n9_q; -- (signal)
-  -- fsm.vhd:16:16
-  state_c <= n40_o; -- (signal)
-  -- fsm.vhd:20:15
-  n4_o <= not wrap_reset_n;
-  -- fsm.vhd:22:5
-  process (wrap_clk, n4_o)
-  begin
-    if n4_o = '1' then
-      n9_q <= "000";
-    elsif rising_edge (wrap_clk) then
-      n9_q <= state_c;
-    end if;
-  end process;
-  -- fsm.vhd:33:20
-  n12_o <= wrap_switches (0);
-  -- fsm.vhd:33:9
-  n14_o <= state when n12_o = '0' else "001";
-  -- fsm.vhd:37:20
-  n15_o <= wrap_switches (1);
-  -- fsm.vhd:37:9
-  n17_o <= state when n15_o = '0' else "010";
-  -- fsm.vhd:41:20
-  n18_o <= wrap_switches (2);
-  -- fsm.vhd:41:9
-  n20_o <= state when n18_o = '0' else "011";
-  -- fsm.vhd:45:20
-  n21_o <= wrap_switches (3);
-  -- fsm.vhd:45:9
-  n23_o <= state when n21_o = '0' else "100";
-  -- fsm.vhd:49:20
-  n24_o <= wrap_switches (4);
-  -- fsm.vhd:49:9
-  n26_o <= state when n24_o = '0' else "101";
-  -- fsm.vhd:53:20
-  n27_o <= wrap_switches (5);
-  -- fsm.vhd:53:9
-  n29_o <= state when n27_o = '0' else "110";
-  -- fsm.vhd:57:20
-  n30_o <= wrap_switches (6);
-  -- fsm.vhd:57:9
-  n32_o <= state when n30_o = '0' else "111";
-  -- fsm.vhd:61:20
-  n33_o <= wrap_switches (7);
-  -- fsm.vhd:61:9
-  n35_o <= state when n33_o = '0' else "000";
-  -- fsm.vhd:31:10
-  n36_o <= state (1 downto 0);
-  -- fsm.vhd:31:10
-  with n36_o select n37_o <=
-    n14_o when "00",
-    n17_o when "01",
-    n20_o when "10",
-    n23_o when "11",
-    "XXX" when others;
-  -- fsm.vhd:31:10
-  with n36_o select n38_o <=
-    n26_o when "00",
-    n29_o when "01",
-    n32_o when "10",
-    n35_o when "11",
-    "XXX" when others;
-  -- fsm.vhd:31:10
-  n39_o <= state (2);
-  -- fsm.vhd:31:10
-  n40_o <= n37_o when n39_o = '0' else n38_o;
-  -- fsm.vhd:71:56
-  n44_o <= '1' when state = "000" else '0';
-  -- fsm.vhd:71:46
-  n45_o <= n49_o when n44_o = '0' else "00000000";
-  -- fsm.vhd:72:56
-  n48_o <= '1' when state = "001" else '0';
-  -- fsm.vhd:71:60
-  n49_o <= n53_o when n48_o = '0' else "00000001";
-  -- fsm.vhd:73:56
-  n52_o <= '1' when state = "010" else '0';
-  -- fsm.vhd:72:60
-  n53_o <= n57_o when n52_o = '0' else "00000010";
-  -- fsm.vhd:74:56
-  n56_o <= '1' when state = "011" else '0';
-  -- fsm.vhd:73:60
-  n57_o <= n61_o when n56_o = '0' else "00000011";
-  -- fsm.vhd:75:56
-  n60_o <= '1' when state = "100" else '0';
-  -- fsm.vhd:74:60
-  n61_o <= n65_o when n60_o = '0' else "00000100";
-  -- fsm.vhd:76:56
-  n64_o <= '1' when state = "101" else '0';
-  -- fsm.vhd:75:60
-  n65_o <= n69_o when n64_o = '0' else "00000101";
-  -- fsm.vhd:77:56
-  n68_o <= '1' when state = "110" else '0';
-  -- fsm.vhd:76:60
-  n69_o <= "00000111" when n68_o = '0' else "00000110";
-end rtl;

data/tests/parser_tests/else.vhd

@@ -1,64 +0,0 @@
-architecture rtl of entite is
-begin
-
-    comb: process(state_r,inputs_r,inputs_acks_r,vars_r,outputs_acks_r)
-    variable state_v : state_t;
-    variable vars_v : vars_t;
-    variable outputs_v : outputs_t;
-  begin
-    state_v := state_r;
-    case state_v is
-      when S_0 =>
-        req_c.a := '1';
-        state_v := S_1;
-      when S_1 =>
-        vars_c.tmp_0 := ack_c.a = '1';
-        vars_v.va := inputs_v.a;
-        if tmp_0 then
-          req_c.a := '0';
-          req_c.b := '1';
-          state_v := S_2;
-        else
-          null;
-        end if;
-      when S_2 =>
-        vars_c.tmp_1 := ack_c.b = '1';
-        vars_v.vb := inputs_v.b;
-        if tmp_1 then
-          req_c.b := '0';
-          state_v := S_3;
-        else
-          null;
-        end if;
-      when S_3 =>
-        if va /= vb then
-          vars_c.tmp_2 := va > vb;
-          if tmp_2 then
-            vars_c.va := vb;
-            state_v := S_3;
-          else
-            null;
-          end if;
-        else
-          null;
-        end if;
-      when S_4 =>
-        vars_c.tmp_3 := ack_c.result = '1';
-        null;
-        if tmp_3 then
-          req_c.result := '0';
-          null;
-        else
-          null;
-        end if;
-      when others =>
-        null;
-    end case;
-    vars_c <= vars_v;
-    inputs_reqs_c <= inputs_reqs_v;
-    outputs_c <= outputs_v;
-    outputs_reqs_c <= outputs_reqs_v;
-    state_c <= state_v;
-  end process;
-
-end rtl;

data/tests/parser_tests/pingpong.vhd

@@ -1,34 +0,0 @@
--- generated automatically by NewageHLS
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library newage_lib;
-use newage_lib.type_package.all;
-
-
-entity PingPong_sys is
-  port(
-    reset_n : in std_logic;
-    clk : in std_logic;
-    sreset : in std_logic;
-    go : in std_logic;
-    done : out std_logic;
-    inputs : in inputs_t;
-    outputs : out outputs_t;
-    reqs : out reqs_t;
-    acks : in acks_t);
-end entity PingPong_sys;
-
-architecture RTL of PingPong_sys is
-begin
-
-  inst_0 : entity Player1_lib.ping(RTL)
-    port map(
-    );
-
-  inst_1 : entity Player2_lib.pong(RTL)
-    port map(
-    );
-
-end RTL;