vertigo_vhdl 0.8.6 → 0.8.11

data/tests/parser_tests/test_microwatt_core_pp.vhd

@@ -1,231 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.common.all;
-use work.wishbone_types.all;
- 
-entity core is
-  generic(
-    sim : booleanfalse := false;
-    disable_flatten : booleanfalse := false;
-    ex1_bypass : booleantrue := true);
-  port(
-    clk : in std_logic;
-    rst : in std_logic;
-    wishbone_insn_in : in wishbone_slave_out;
-    wishbone_insn_out : out wishbone_master_out;
-    wishbone_data_in : in wishbone_slave_out;
-    wishbone_data_out : out wishbone_master_out;
-    dmi_addr : in std_ulogic_vector(3 downto 0);
-    dmi_din : in std_ulogic_vector(63 downto 0);
-    dmi_dout : out std_ulogic_vector(63 downto 0);
-    dmi_req : in std_ulogic;
-    dmi_wr : in std_ulogic;
-    dmi_ack : out std_ulogic;
-    terminated_out : out std_logic);
-end entity core;
- 
-architecture behave of core is
-  signal fetch2_to_decode1 : fetch2todecode1type;
-  signal fetch1_to_icache : fetch1toicachetype;
-  signal icache_to_fetch2 : icachetofetch2type;
-  signal decode1_to_decode2 : decode1todecode2type;
-  signal decode2_to_execute1 : decode2toexecute1type;
-  signal register_file_to_decode2 : registerfiletodecode2type;
-  signal decode2_to_register_file : decode2toregisterfiletype;
-  signal writeback_to_register_file : writebacktoregisterfiletype;
-  signal decode2_to_cr_file : decode2tocrfiletype;
-  signal cr_file_to_decode2 : crfiletodecode2type;
-  signal writeback_to_cr_file : writebacktocrfiletype;
-  signal execute1_to_writeback : execute1towritebacktype;
-  signal execute1_to_fetch1 : execute1tofetch1type;
-  signal execute1_to_loadstore1 : execute1toloadstore1type;
-  signal loadstore1_to_writeback : loadstore1towritebacktype;
-  signal loadstore1_to_dcache : loadstore1todcachetype;
-  signal dcache_to_loadstore1 : dcachetoloadstore1type;
-  signal fetch1_stall_in : std_ulogic;
-  signal icache_stall_out : std_ulogic;
-  signal fetch2_stall_in : std_ulogic;
-  signal decode1_stall_in : std_ulogic;
-  signal decode2_stall_in : std_ulogic;
-  signal decode2_stall_out : std_ulogic;
-  signal ex1_icache_inval : std_ulogic;
-  signal ex1_stall_out : std_ulogic;
-  signal ls1_stall_out : std_ulogic;
-  signal dcache_stall_out : std_ulogic;
-  signal flush : std_ulogic;
-  signal complete : std_ulogic;
-  signal terminate : std_ulogic;
-  signal core_rst : std_ulogic;
-  signal icache_rst : std_ulogic;
-  signal sim_cr_dump : std_ulogic;
-  signal dbg_core_stop : std_ulogic;
-  signal dbg_core_rst : std_ulogic;
-  signal dbg_icache_rst : std_ulogic;
-  signal dbg_core_is_stopped : std_ulogic;
-   
-  function keep_h(disable : boolean) return string is
-  begin
-    if disable then
-      return "yes";
-    else
-      return "no";
-    end if;
-  end function keep_h;
-  attribute keep_hierarchy : string;
-  attribute keep_hierarchy of fetch1_0 : label is keep_h(disable_flatten);
-  attribute keep_hierarchy of icache_0 : label is keep_h(disable_flatten);
-  attribute keep_hierarchy of fetch2_0 : label is keep_h(disable_flatten);
-  attribute keep_hierarchy of decode1_0 : label is keep_h(disable_flatten);
-  attribute keep_hierarchy of decode2_0 : label is keep_h(disable_flatten);
-  attribute keep_hierarchy of register_file_0 : label is keep_h(disable_flatten);
-  attribute keep_hierarchy of cr_file_0 : label is keep_h(disable_flatten);
-  attribute keep_hierarchy of execute1_0 : label is keep_h(disable_flatten);
-  attribute keep_hierarchy of loadstore1_0 : label is keep_h(disable_flatten);
-  attribute keep_hierarchy of dcache_0 : label is keep_h(disable_flatten);
-  attribute keep_hierarchy of writeback_0 : label is keep_h(disable_flatten);
-  attribute keep_hierarchy of debug_0 : label is keep_h(disable_flatten);
-begin
- 
-  core_rst <= dbg_core_rst or rst;
-  fetch1_0 : entity work.fetch1
-    port map(
-      clk => clk,
-      rst => core_rst,
-      stall_in => fetch1_stall_in,
-      flush_in => flush,
-      stop_in => dbg_core_stop,
-      e_in => execute1_to_fetch1,
-      i_out => fetch1_to_icache);
-   
-  fetch1_stall_in <= icache_stall_out or decode2_stall_out;
-  icache_0 : entity work.icache
-    port map(
-      clk => clk,
-      rst => icache_rst,
-      i_in => fetch1_to_icache,
-      i_out => icache_to_fetch2,
-      flush_in => flush,
-      stall_out => icache_stall_out,
-      wishbone_out => wishbone_insn_out,
-      wishbone_in => wishbone_insn_in);
-   
-  icache_rst <= rst or dbg_icache_rst or ex1_icache_inval;
-  fetch2_0 : entity work.fetch2
-    port map(
-      clk => clk,
-      rst => core_rst,
-      stall_in => fetch2_stall_in,
-      flush_in => flush,
-      i_in => icache_to_fetch2,
-      f_out => fetch2_to_decode1);
-   
-  fetch2_stall_in <= decode2_stall_out;
-  decode1_0 : entity work.decode1
-    port map(
-      clk => clk,
-      rst => core_rst,
-      stall_in => decode1_stall_in,
-      flush_in => flush,
-      f_in => fetch2_to_decode1,
-      d_out => decode1_to_decode2);
-   
-  decode1_stall_in <= decode2_stall_out;
-  decode2_0 : entity work.decode2
-    port map(
-      clk => clk,
-      rst => core_rst,
-      stall_in => decode2_stall_in,
-      stall_out => decode2_stall_out,
-      flush_in => flush,
-      complete_in => complete,
-      stopped_out => dbg_core_is_stopped,
-      d_in => decode1_to_decode2,
-      e_out => decode2_to_execute1,
-      r_in => register_file_to_decode2,
-      r_out => decode2_to_register_file,
-      c_in => cr_file_to_decode2,
-      c_out => decode2_to_cr_file);
-   
-  decode2_stall_in <= ex1_stall_out or ls1_stall_out;
-  register_file_0 : entity work.register_file
-    port map(
-      clk => clk,
-      d_in => decode2_to_register_file,
-      d_out => register_file_to_decode2,
-      w_in => writeback_to_register_file,
-      sim_dump => terminate,
-      sim_dump_done => sim_cr_dump);
-   
-  cr_file_0 : entity work.cr_file
-    port map(
-      clk => clk,
-      d_in => decode2_to_cr_file,
-      d_out => cr_file_to_decode2,
-      w_in => writeback_to_cr_file,
-      sim_dump => sim_cr_dump);
-   
-  execute1_0 : entity work.execute1
-    port map(
-      clk => clk,
-      rst => core_rst,
-      flush_out => flush,
-      stall_out => ex1_stall_out,
-      e_in => decode2_to_execute1,
-      l_out => execute1_to_loadstore1,
-      f_out => execute1_to_fetch1,
-      e_out => execute1_to_writeback,
-      icache_inval => ex1_icache_inval,
-      terminate_out => terminate);
-   
-  loadstore1_0 : entity work.loadstore1
-    port map(
-      clk => clk,
-      rst => core_rst,
-      l_in => execute1_to_loadstore1,
-      l_out => loadstore1_to_writeback,
-      d_out => loadstore1_to_dcache,
-      d_in => dcache_to_loadstore1,
-      dc_stall => dcache_stall_out,
-      stall_out => ls1_stall_out);
-   
-  dcache_0 : entity work.dcache
-    port map(
-      clk => clk,
-      rst => core_rst,
-      d_in => loadstore1_to_dcache,
-      d_out => dcache_to_loadstore1,
-      stall_out => dcache_stall_out,
-      wishbone_in => wishbone_data_in,
-      wishbone_out => wishbone_data_out);
-   
-  writeback_0 : entity work.writeback
-    port map(
-      clk => clk,
-      e_in => execute1_to_writeback,
-      l_in => loadstore1_to_writeback,
-      w_out => writeback_to_register_file,
-      c_out => writeback_to_cr_file,
-      complete_out => complete);
-   
-  debug_0 : entity work.core_debug
-    port map(
-      clk => clk,
-      rst => rst,
-      dmi_addr => dmi_addr,
-      dmi_din => dmi_din,
-      dmi_dout => dmi_dout,
-      dmi_req => dmi_req,
-      dmi_wr => dmi_wr,
-      dmi_ack => dmi_ack,
-      core_stop => dbg_core_stop,
-      core_rst => dbg_core_rst,
-      icache_rst => dbg_icache_rst,
-      terminate => terminate,
-      core_stopped => dbg_core_is_stopped,
-      nia => fetch1_to_icache.nia,
-      terminated_out => terminated_out);
-   
-end behave;

data/tests/parser_tests/test_microwatt_core_tb_pp.vhd

@@ -1,43 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.common.all;
-use work.wishbone_types.all;
- 
-entity core_tb is
-end entity core_tb;
- 
-architecture behave of core_tb is
-  signal clk : std_logic;
-  signal rst : std_logic;
-  constant clk_period : time := 10 ns;
-begin
- 
-  soc0 : entity work.soc
-    port map(
-      rst => rst,
-      system_clk => clk,
-      uart0_rxd => '0',
-      uart0_txd => open);
-   
-   
-  clk_process : process
-  begin
-    clk <= '0';
-    wait clk_period / 2;
-    clk <= '1';
-    wait clk_period / 2;
-  end process;
-   
-  rst_process : process
-  begin
-    rst <= '1';
-    wait 10 * clk_period;
-    rst <= '0';
-    wait ;
-  end process;
-  jtag : entity work.sim_jtag
-   
-end behave;

data/tests/parser_tests/test_microwatt_countzero_pp.vhd

@@ -1,120 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
- 
-entity zero_counter is
-  port(
-    clk : in std_logic;
-    rs : in std_ulogic_vector(63 downto 0);
-    count_right : in std_ulogic;
-    is_32bit : in std_ulogic;
-    result : out std_ulogic_vector(63 downto 0));
-end entity zero_counter;
- 
-architecture behaviour of zero_counter is
-   
-  type intermediate_result is record
-    v16 : std_ulogic_vector(15 downto 0);
-    sel_hi : std_ulogic_vector(1 downto 0);
-    is_32bit : std_ulogic;
-    count_right : std_ulogic;
-  end record;
-  signal r : intermediate_result;
-  signal r_in : intermediate_result;
-   
-  function encoder(v : std_ulogic_vector(3 downto 0);right : std_ulogic) return std_ulogic_vector is
-  begin
-    if right = '0' then
-      if v(3) = '1' then
-        return "11";
-      elsif v(2) = '1' then
-        return "10";
-      elsif v(1) = '1' then
-        return "01";
-      else
-        return "00";
-      end if;
-    else
-      if v(0) = '1' then
-        return "00";
-      elsif v(1) = '1' then
-        return "01";
-      elsif v(2) = '1' then
-        return "10";
-      else
-        return "11";
-      end if;
-    end if;
-  end function encoder;
-begin
- 
-   
-  zerocounter_0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      r <= r_in;
-    end if;
-  end process;
-   
-  zerocounter_1 : process(all)
-    variable v : intermediate_result;
-    variable y : std_ulogic_vector(3 downto 0);
-    variable z : std_ulogic_vector(3 downto 0);
-    variable sel : std_ulogic_vector(5 downto 0);
-    variable v4 : std_ulogic_vector(3 downto 0);
-  begin
-    z(0) := or(rs(15 downto 0));
-    z(1) := or(rs(31 downto 16));
-    z(2) := or(rs(47 downto 32));
-    z(3) := or(rs(63 downto 48));
-    if is_32bit = '0' then
-      v.sel_hi := encoder(z,count_right);
-    else
-      v.sel_hi(1) := '0';
-      if count_right = '0' then
-        v.sel_hi(0) := z(1);
-      else
-        v.sel_hi(0) := z(0);
-      end if;
-    end if;
-    case v.sel_hi is
-      when "00" =>
-        v.v16 := rs(15 downto 0);
-      when "01" =>
-        v.v16 := rs(31 downto 16);
-      when "10" =>
-        v.v16 := rs(47 downto 32);
-      when others =>
-        v.v16 := rs(63 downto 48);
-    end case;
-    v.is_32bit := is_32bit;
-    v.count_right := count_right;
-    r_in <= v;
-    sel(5 downto 4) := r.sel_hi;
-    y(0) := or(r.v16(3 downto 0));
-    y(1) := or(r.v16(7 downto 4));
-    y(2) := or(r.v16(11 downto 8));
-    y(3) := or(r.v16(15 downto 12));
-    sel(3 downto 2) := encoder(y,r.count_right);
-    case sel(3 downto 2) is
-      when "00" =>
-        v4 := r.v16(3 downto 0);
-      when "01" =>
-        v4 := r.v16(7 downto 4);
-      when "10" =>
-        v4 := r.v16(11 downto 8);
-      when others =>
-        v4 := r.v16(15 downto 12);
-    end case;
-    sel(1 downto 0) := encoder(v4,r.count_right);
-    if v4 = "0000" then
-      result <= x"00000000000000" & '0' & r.is_32bit & r.is_32bit & "00000";
-    elsif r.count_right = '0' then
-      result <= x"00000000000000" & "00" & (sel(5) and r.is_32bit) & sel(4 downto 0);
-    else
-      result <= x"00000000000000" & "00" & sel;
-    end if;
-  end process;
-end behaviour;

data/tests/parser_tests/test_microwatt_countzero_tb_pp.vhd

@@ -1,70 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.common.all;
-use work.glibc_random.all;
- 
-entity countzero_tb is
-end entity countzero_tb;
- 
-architecture behave of countzero_tb is
-  constant clk_period : time := 10 ns;
-  signal rs : std_ulogic_vector(63 downto 0);
-  signal is_32bit : std_ulogic;
-  signal count_right : std_ulogic := '0';
-  signal result : std_ulogic_vector(63 downto 0);
-  signal randno : std_ulogic_vector(63 downto 0);
-  signal clk : std_ulogic;
-begin
- 
-  zerocounter_0 : entity work.zero_counter
-    port map(
-      clk => clk,
-      rs => rs,
-      result => result,
-      count_right => count_right,
-      is_32bit => is_32bit);
-   
-   
-  clk_process : process
-  begin
-    clk <= '0';
-    wait clk_period / 2;
-    clk <= '1';
-    wait clk_period / 2;
-  end process;
-   
-  stim_process : process
-    variable r : std_ulogic_vector(63 downto 0);
-  begin
-    report "test zero input";
-    rs <= (others => '0');
-    is_32bit <= '0';
-    count_right <= '0';
-    wait clk_period;
-    assert result = x"0000000000000040"
-      report "bad cntlzd 0 = " & to_hstring(result);
-    count_right <= '1';
-    wait clk_period;
-    assert result = x"0000000000000040"
-      report "bad cnttzd 0 = " & to_hstring(result);
-    is_32bit <= '1';
-    count_right <= '0';
-    wait clk_period;
-    assert result = x"0000000000000020"
-      report "bad cntlzw 0 = " & to_hstring(result);
-    count_right <= '1';
-    wait clk_period;
-    assert result = x"0000000000000020"
-      report "bad cnttzw 0 = " & to_hstring(result);
-    report "test cntlzd/w";
-    count_right <= '0';
-    report "test cnttzd/w";
-    count_right <= '1';
-    assert false
-      report "end of test" severity failure;
-    wait ;
-  end process;
-end behave;

data/tests/parser_tests/test_microwatt_cr_file_pp.vhd

@@ -1,74 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.common.all;
- 
-entity cr_file is
-  generic(
-    sim : booleanfalse := false);
-  port(
-    clk : in std_logic;
-    d_in : in decode2tocrfiletype;
-    d_out : out crfiletodecode2type;
-    w_in : in writebacktocrfiletype;
-    sim_dump : in std_ulogic);
-end entity cr_file;
- 
-architecture behaviour of cr_file is
-  signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
-  signal crs_updated : std_ulogic_vector(31 downto 0);
-  signal xerc : xer_common_t := xerc_init;
-  signal xerc_updated : xer_common_t;
-begin
- 
-   
-  cr_create_0 : process(all)
-    variable hi : integer;
-    variable lo : integer := 0;
-    variable cr_tmp : std_ulogic_vector(31 downto 0) := (others => '0');
-  begin
-    cr_tmp := crs;
-    crs_updated <= cr_tmp;
-    if w_in.write_xerc_enable = '1' then
-      xerc_updated <= w_in.write_xerc_data;
-    else
-      xerc_updated <= xerc;
-    end if;
-  end process;
-   
-  cr_write_0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      if w_in.write_cr_enable = '1' then
-        report "writing " & to_hstring(w_in.write_cr_data) & " to cr mask " & to_hstring(w_in.write_cr_mask);
-        crs <= crs_updated;
-      end if;
-      if w_in.write_xerc_enable = '1' then
-        report "writing xerc";
-        xerc <= xerc_updated;
-      end if;
-    end if;
-  end process;
-   
-  cr_read_0 : process(all)
-  begin
-    if d_in.read = '1' then
-      report "reading cr " & to_hstring(crs_updated);
-    end if;
-    d_out.read_cr_data <= crs_updated;
-    d_out.read_xerc_data <= xerc_updated;
-  end process;
-  if sim generate
-     
-    dump_cr : process(all)
-    begin
-      if sim_dump = '1' then
-        report "cr 00000000" & to_hstring(crs);
-        assert false
-          report "end of test" severity failure;
-      end if;
-    end process;
-  end generate;
-end behaviour;

data/tests/parser_tests/test_microwatt_cr_hazard_pp.vhd

@@ -1,51 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity cr_hazard is
-  generic(
-    pipeline_depth : natural2 := 2);
-  port(
-    clk : in std_ulogic;
-    stall_in : in std_ulogic;
-    cr_read_in : in std_ulogic;
-    cr_write_in : in std_ulogic;
-    stall_out : out std_ulogic);
-end entity cr_hazard;
- 
-architecture behaviour of cr_hazard is
-   
-  type pipeline_entry_type is record
-    valid : std_ulogic;
-  end record;
-  constant pipeline_entry_init : pipeline_entry_type := (valid => '0');
-   
-  type pipeline_t is array(range 0 to pipeline_depth - 1) of pipeline_entry_type;
-  constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
-  signal r : pipeline_t;
-  signal rin : pipeline_t := pipeline_t_init;
-begin
- 
-   
-  cr_hazard0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      if stall_in = '0' then
-        r <= rin;
-      end if;
-    end if;
-  end process;
-   
-  cr_hazard1 : process(all)
-    variable v : pipeline_t;
-  begin
-    v := r;
-    stall_out <= '0';
-    v(0).valid := cr_write_in;
-    if cr_read_in = '0' then
-      stall_out <= '0';
-    end if;
-    rin <= v;
-  end process;
-end behaviour;

data/tests/parser_tests/test_microwatt_crhelpers_pp.vhd

@@ -1,48 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-library work;
-use work.common.all;
- 
-package crhelpers is
-   
-  subtype crnum_t is integer range 0 to 7;
-   
-  subtype crmask_t is std_ulogic_vector(7 downto 0);
-  function fxm_to_num(fxm : crmask_t) return crnum_t
-  function num_to_fxm(num : crnum_t) return crmask_t
- 
-end crhelpers;
- 
-package body crhelpers is
-   
-  function fxm_to_num(fxm : crmask_t) return crnum_t is
-  begin
-    ;
-    return 7;
-  end function fxm_to_num;
-   
-  function num_to_fxm(num : crnum_t) return crmask_t is
-  begin
-    case num is
-      when 0 =>
-        return "10000000";
-      when 1 =>
-        return "01000000";
-      when 2 =>
-        return "00100000";
-      when 3 =>
-        return "00010000";
-      when 4 =>
-        return "00001000";
-      when 5 =>
-        return "00000100";
-      when 6 =>
-        return "00000010";
-      when 7 =>
-        return "00000001";
-      when others =>
-        return "00000000";
-    end case;
-  end function num_to_fxm;
-end crhelpers;