vertigo_vhdl 0.8.6 → 0.8.11

data/tests/parser_tests/test_microwatt_fetch1_pp.vhd

@@ -1,88 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.common.all;
- 
-entity fetch1 is
-  generic(
-    reset_address : std_logic_vector(63 downto 0)(others => '0') := (others => '0'));
-  port(
-    clk : in std_ulogic;
-    rst : in std_ulogic;
-    stall_in : in std_ulogic;
-    flush_in : in std_ulogic;
-    stop_in : in std_ulogic;
-    e_in : in execute1tofetch1type;
-    i_out : out fetch1toicachetype);
-end entity fetch1;
- 
-architecture behaviour of fetch1 is
-   
-  type stop_state_t is (running,stopped,restarting);
-   
-  type reg_internal_t is record
-    stop_state : stop_state_t;
-  end record;
-  signal r : fetch1toicachetype;
-  signal r_next : fetch1toicachetype;
-  signal r_int : reg_internal_t;
-  signal r_next_int : reg_internal_t;
-begin
- 
-   
-  regs : process(clk)
-  begin
-    if rising_edge(clk) then
-      if r /= r_next then
-        report "fetch1 rst:" & std_ulogic'image(rst) & " r:" & std_ulogic'image(e_in.redirect) & " s:" & std_ulogic'image(stall_in) & " t:" & std_ulogic'image(stop_in) & " nia:" & to_hstring(r_next.nia) & " sm:" & std_ulogic'image(r_next.stop_mark);
-      end if;
-      r <= r_next;
-      r_int <= r_next_int;
-    end if;
-  end process;
-   
-  comb : process(all)
-    variable v : fetch1toicachetype;
-    variable v_int : reg_internal_t;
-    variable increment : boolean;
-  begin
-    v := r;
-    v_int := r_int;
-    if rst = '1' then
-      v.nia := reset_address;
-      v_int.stop_state := running;
-    elsif e_in.redirect = '1' then
-      v.nia := e_in.redirect_nia;
-    elsif stall_in = '0' then
-      increment := true;
-      case v_int.stop_state is
-        when running =>
-          if stop_in = '1' then
-            increment := false;
-            v_int.stop_state := stopped;
-          end if;
-        when stopped =>
-          increment := false;
-          if stop_in = '0' then
-            v_int.stop_state := restarting;
-          end if;
-        when restarting =>
-          if stop_in = '0' then
-            v_int.stop_state := running;
-          else
-            v_int.stop_state := stopped;
-          end if;
-      end case;
-      if increment then
-        v.nia := std_logic_vector(unsigned(v.nia) + 4);
-      end if;
-    end if;
-    v.req := rst;
-    v.stop_mark := stop_in;
-    r_next <= v;
-    r_next_int <= v_int;
-    i_out <= r;
-  end process;
-end behaviour;

data/tests/parser_tests/test_microwatt_fetch2_pp.vhd

@@ -1,79 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.common.all;
-use work.wishbone_types.all;
- 
-entity fetch2 is
-  port(
-    clk : in std_ulogic;
-    rst : in std_ulogic;
-    stall_in : in std_ulogic;
-    flush_in : in std_ulogic;
-    i_in : in icachetofetch2type;
-    f_out : out fetch2todecode1type);
-end entity fetch2;
- 
-architecture behaviour of fetch2 is
-   
-  type reg_internal_type is record
-    stash : icachetofetch2type;
-    stash_valid : std_ulogic;
-    stopped : std_ulogic;
-  end record;
-  signal r_int : reg_internal_type;
-  signal rin_int : reg_internal_type;
-  signal r : fetch2todecode1type;
-  signal rin : fetch2todecode1type;
-begin
- 
-   
-  regs : process(clk)
-  begin
-    if rising_edge(clk) then
-      if (r /= rin) then
-        report "fetch2 rst:" & std_ulogic'image(rst) & " s:" & std_ulogic'image(stall_in) & " f:" & std_ulogic'image(flush_in) & " t:" & std_ulogic'image(rin.stop_mark) & " v:" & std_ulogic'image(rin.valid) & " nia:" & to_hstring(rin.nia);
-      end if;
-      if rst = '1' or flush_in = '1' or stall_in = '0' then
-        r <= rin;
-      end if;
-      r_int <= rin_int;
-    end if;
-  end process;
-   
-  comb : process(all)
-    variable v : fetch2todecode1type;
-    variable v_int : reg_internal_type;
-    variable v_i_in : icachetofetch2type;
-  begin
-    v := r;
-    v_int := r_int;
-    if stall_in = '1' and v_int.stash_valid = '0' then
-      v_int.stash := i_in;
-      v_int.stash_valid := '1';
-    end if;
-    v_i_in := i_in;
-    if v_int.stash_valid = '1' and stall_in = '0' then
-      v_i_in := v_int.stash;
-      v_int.stash_valid := '0';
-    end if;
-    v.valid := v_i_in.valid;
-    v.stop_mark := v_i_in.stop_mark;
-    v.nia := v_i_in.nia;
-    v.insn := v_i_in.insn;
-    if flush_in = '1' then
-      v_int.stash.valid := '0';
-    end if;
-    if flush_in = '1' or v.stop_mark = '1' then
-      v.valid := '0';
-    end if;
-    if rst = '1' then
-      v_int.stash_valid := '0';
-    end if;
-    rin <= v;
-    rin_int <= v_int;
-    f_out <= r;
-  end process;
-end behaviour;

data/tests/parser_tests/test_microwatt_glibc_random_helpers_pp.vhd

@@ -1,25 +0,0 @@
--- generated by Vertigo VHDL tool
- 
-package glibc_random_helpers is
-   
-  procedure srand(
-    v : integer);
-  attribute foreign of srand : procedure is "vhpidirect srand";
-  function random() return integer
-  attribute foreign of random : function is "vhpidirect random";
- 
-end glibc_random_helpers;
- 
-package body glibc_random_helpers is
-   
-  procedure srand(
-    v : integer) is
-  begin
-    assert false;
-  end srand;
-   
-  function random() return integer is
-  begin
-    assert false;
-  end function random;
-end glibc_random_helpers;

data/tests/parser_tests/test_microwatt_glibc_random_pp.vhd

@@ -1,41 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.glibc_random_helpers.all;
- 
-package glibc_random is
-  function pseudorand(a : integer) return std_ulogic_vector
-  function pseudorand1() return std_ulogic
- 
-end glibc_random;
- 
-package body glibc_random is
-   
-  function pseudorand(a : integer) return std_ulogic_vector is
-    variable tmp1 : std_ulogic_vector(31 downto 0);
-    variable tmp2 : std_ulogic_vector(31 downto 0);
-    variable tmp3 : std_ulogic_vector(31 downto 0);
-    variable tmp4 : std_ulogic_vector(31 downto 0);
-    variable ret : std_ulogic_vector(63 downto 0);
-  begin
-    tmp1 := std_ulogic_vector(to_unsigned(random,32));
-    tmp2 := std_ulogic_vector(to_unsigned(random,32));
-    if a <= 32 then
-      ret := tmp1 & tmp2;
-    else
-      tmp3 := std_ulogic_vector(to_unsigned(random,32));
-      tmp4 := std_ulogic_vector(to_unsigned(random,32));
-      ret := tmp1(15 downto 0) & tmp2(15 downto 0) & tmp3(15 downto 0) & tmp4(15 downto 0);
-    end if;
-    return ret((a - 1) downto 0);
-  end function pseudorand;
-   
-  function pseudorand1() return std_ulogic is
-    variable tmp : std_ulogic_vector(31 downto 0);
-  begin
-    tmp := std_ulogic_vector(to_unsigned(random,32));
-    return tmp(0);
-  end function pseudorand1;
-end glibc_random;

data/tests/parser_tests/test_microwatt_gpr_hazard_pp.vhd

@@ -1,68 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity gpr_hazard is
-  generic(
-    pipeline_depth : natural2 := 2);
-  port(
-    clk : in std_ulogic;
-    stall_in : in std_ulogic;
-    gpr_write_valid_in : in std_ulogic;
-    gpr_write_in : in std_ulogic_vector(5 downto 0);
-    bypass_avail : in std_ulogic;
-    gpr_read_valid_in : in std_ulogic;
-    gpr_read_in : in std_ulogic_vector(5 downto 0);
-    stall_out : out std_ulogic;
-    use_bypass : out std_ulogic);
-end entity gpr_hazard;
- 
-architecture behaviour of gpr_hazard is
-   
-  type pipeline_entry_type is record
-    valid : std_ulogic;
-    bypass : std_ulogic;
-    gpr : std_ulogic_vector(5 downto 0);
-  end record;
-  constant pipeline_entry_init : pipeline_entry_type := (valid => '0',bypass => '0',gpr => (others => '0'));
-   
-  type pipeline_t is array(range 0 to pipeline_depth - 1) of pipeline_entry_type;
-  constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
-  signal r : pipeline_t;
-  signal rin : pipeline_t := pipeline_t_init;
-begin
- 
-   
-  gpr_hazard0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      r <= rin;
-    end if;
-  end process;
-   
-  gpr_hazard1 : process(all)
-    variable v : pipeline_t;
-  begin
-    v := r;
-    stall_out <= '0';
-    use_bypass <= '0';
-    if gpr_read_valid_in = '1' then
-      if r(0).valid = '1' and r(0).gpr = gpr_read_in then
-        if r(0).bypass = '1' and stall_in = '0' then
-          use_bypass <= '1';
-        else
-          stall_out <= '1';
-        end if;
-      end if;
-    end if;
-    if stall_in = '0' then
-      v(0).valid := gpr_write_valid_in;
-      v(0).bypass := bypass_avail;
-      v(0).gpr := gpr_write_in;
-    else
-      ;
-    end if;
-    rin <= v;
-  end process;
-end behaviour;

data/tests/parser_tests/test_microwatt_helpers_pp.vhd

@@ -1,153 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
- 
-package helpers is
-  function fls_32(val : std_ulogic_vector(31 downto 0)) return integer
-  function ffs_32(val : std_ulogic_vector(31 downto 0)) return integer
-  function fls_64(val : std_ulogic_vector(63 downto 0)) return integer
-  function ffs_64(val : std_ulogic_vector(63 downto 0)) return integer
-  function popcnt8(val : std_ulogic_vector(7 downto 0)) return std_ulogic_vector
-  function popcnt32(val : std_ulogic_vector(31 downto 0)) return std_ulogic_vector
-  function popcnt64(val : std_ulogic_vector(63 downto 0)) return std_ulogic_vector
-  function cmp_one_byte(a : std_ulogic_vector(7 downto 0);b : std_ulogic_vector(7 downto 0)) return std_ulogic_vector
-  function ppc_signed_compare(a : signed(63 downto 0);b : signed(63 downto 0);so : std_ulogic) return std_ulogic_vector
-  function ppc_unsigned_compare(a : unsigned(63 downto 0);b : unsigned(63 downto 0);so : std_ulogic) return std_ulogic_vector
-  function ra_or_zero(ra : std_ulogic_vector(63 downto 0);reg : std_ulogic_vector(4 downto 0)) return std_ulogic_vector
-  function byte_reverse(val : std_ulogic_vector(63 downto 0);size : integer) return std_ulogic_vector
-  function sign_extend(val : std_ulogic_vector(63 downto 0);size : natural) return std_ulogic_vector
- 
-end helpers;
- 
-package body helpers is
-   
-  function fls_32(val : std_ulogic_vector(31 downto 0)) return integer is
-    variable ret : integer;
-  begin
-    ret := 32;
-    return ret;
-  end function fls_32;
-   
-  function ffs_32(val : std_ulogic_vector(31 downto 0)) return integer is
-    variable ret : integer;
-  begin
-    ret := 32;
-    return ret;
-  end function ffs_32;
-   
-  function fls_64(val : std_ulogic_vector(63 downto 0)) return integer is
-    variable ret : integer;
-  begin
-    ret := 64;
-    return ret;
-  end function fls_64;
-   
-  function ffs_64(val : std_ulogic_vector(63 downto 0)) return integer is
-    variable ret : integer;
-  begin
-    ret := 64;
-    return ret;
-  end function ffs_64;
-   
-  function popcnt8(val : std_ulogic_vector(7 downto 0)) return std_ulogic_vector is
-    variable ret : unsigned(3 downto 0) := (others => '0');
-  begin
-    ;
-    return std_ulogic_vector(resize(ret,val'length));
-  end function popcnt8;
-   
-  function popcnt32(val : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
-    variable ret : unsigned(5 downto 0) := (others => '0');
-  begin
-    ;
-    return std_ulogic_vector(resize(ret,val'length));
-  end function popcnt32;
-   
-  function popcnt64(val : std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
-    variable ret : unsigned(6 downto 0) := (others => '0');
-  begin
-    ;
-    return std_ulogic_vector(resize(ret,val'length));
-  end function popcnt64;
-   
-  function cmp_one_byte(a : std_ulogic_vector(7 downto 0);b : std_ulogic_vector(7 downto 0)) return std_ulogic_vector is
-    variable ret : std_ulogic_vector(7 downto 0);
-  begin
-    if a = b then
-      ret := x"ff";
-    else
-      ret := x"00";
-    end if;
-    return ret;
-  end function cmp_one_byte;
-   
-  function ppc_signed_compare(a : signed(63 downto 0);b : signed(63 downto 0);so : std_ulogic) return std_ulogic_vector is
-    variable ret : std_ulogic_vector(2 downto 0);
-  begin
-    if a < b then
-      ret := "100";
-    elsif a > b then
-      ret := "010";
-    else
-      ret := "001";
-    end if;
-    return ret & so;
-  end function ppc_signed_compare;
-   
-  function ppc_unsigned_compare(a : unsigned(63 downto 0);b : unsigned(63 downto 0);so : std_ulogic) return std_ulogic_vector is
-    variable ret : std_ulogic_vector(2 downto 0);
-  begin
-    if a < b then
-      ret := "100";
-    elsif a > b then
-      ret := "010";
-    else
-      ret := "001";
-    end if;
-    return ret & so;
-  end function ppc_unsigned_compare;
-   
-  function ra_or_zero(ra : std_ulogic_vector(63 downto 0);reg : std_ulogic_vector(4 downto 0)) return std_ulogic_vector is
-  begin
-    if to_integer(unsigned(reg)) = 0 then
-      return x"0000000000000000";
-    else
-      return ra;
-    end if;
-  end function ra_or_zero;
-   
-  function byte_reverse(val : std_ulogic_vector(63 downto 0);size : integer) return std_ulogic_vector is
-    variable ret : std_ulogic_vector(63 downto 0) := (others => '0');
-  begin
-    case size is
-      when 2 =>
-        ;
-      when 4 =>
-        ;
-      when 8 =>
-        ;
-      when others =>
-        report "bad byte reverse length " & integer'image(size) severity failure;
-    end case;
-    return ret;
-  end function byte_reverse;
-   
-  function sign_extend(val : std_ulogic_vector(63 downto 0);size : natural) return std_ulogic_vector is
-    variable ret : signed(63 downto 0) := (others => '0');
-    variable upper : integer := 0;
-  begin
-    case size is
-      when 2 =>
-        ret := resize(signed(val(15 downto 0)),64);
-      when 4 =>
-        ret := resize(signed(val(31 downto 0)),64);
-      when 8 =>
-        ret := resize(signed(val(63 downto 0)),64);
-      when others =>
-        report "bad byte reverse length " & integer'image(size) severity failure;
-    end case;
-    return std_ulogic_vector(ret);
-  end function sign_extend;
-end helpers;