vertigo_vhdl 0.8.6 → 0.8.11

data/tests/parser_tests/test_microwatt_loadstore1_pp.vhd

@@ -1,222 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.common.all;
-use work.helpers.all;
- 
-entity loadstore1 is
-  port(
-    clk : in std_ulogic;
-    rst : in std_ulogic;
-    l_in : in execute1toloadstore1type;
-    l_out : out loadstore1towritebacktype;
-    d_out : out loadstore1todcachetype;
-    d_in : in dcachetoloadstore1type;
-    dc_stall : in std_ulogic;
-    stall_out : out std_ulogic);
-end entity loadstore1;
- 
-architecture behave of loadstore1 is
-   
-  type state_t is (idle,second_req,first_ack_wait,last_ack_wait,ld_update);
-   
-  type reg_stage_t is record
-    load : std_ulogic;
-    addr : std_ulogic_vector(63 downto 0);
-    store_data : std_ulogic_vector(63 downto 0);
-    load_data : std_ulogic_vector(63 downto 0);
-    write_reg : gpr_index_t;
-    length : std_ulogic_vector(3 downto 0);
-    byte_reverse : std_ulogic;
-    sign_extend : std_ulogic;
-    update : std_ulogic;
-    update_reg : gpr_index_t;
-    xerc : xer_common_t;
-    reserve : std_ulogic;
-    rc : std_ulogic;
-    nc : std_ulogic;
-    state : state_t;
-    second_bytes : std_ulogic_vector(7 downto 0);
-  end record;
-   
-  type byte_sel_t is array(range 0 to 7) of std_ulogic;
-   
-  subtype byte_trim_t is std_ulogic_vector(1 downto 0);
-   
-  type trim_ctl_t is array(range 0 to 7) of byte_trim_t;
-  signal r : reg_stage_t;
-  signal rin : reg_stage_t;
-  signal lsu_sum : std_ulogic_vector(63 downto 0);
-   
-  function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
-  begin
-    case length is
-      when "0001" =>
-        return "00000001";
-      when "0010" =>
-        return "00000011";
-      when "0100" =>
-        return "00001111";
-      when "1000" =>
-        return "11111111";
-      when others =>
-        return "00000000";
-    end case;
-  end function length_to_sel;
-   
-  function xfer_data_sel(size : in std_logic_vector(3 downto 0);address : in std_logic_vector(2 downto 0)) return std_ulogic_vector is
-    variable longsel : std_ulogic_vector(15 downto 0);
-  begin
-    longsel := "00000000" & length_to_sel(size);
-    return std_ulogic_vector(shift_left(unsigned(longsel),to_integer(unsigned(address))));
-  end function xfer_data_sel;
-begin
- 
-  lsu_sum <= std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2)) when l_in.valid = '1' else  (others => '0');
-   
-  loadstore1_0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      if rst = '1' then
-        r.state <= idle;
-      else
-        r <= rin;
-      end if;
-    end if;
-  end process;
-   
-  loadstore1_1 : process(all)
-    variable v : reg_stage_t;
-    variable brev_lenm1 : unsigned(2 downto 0);
-    variable byte_offset : unsigned(2 downto 0);
-    variable j : integer;
-    variable k : unsigned(2 downto 0);
-    variable kk : unsigned(3 downto 0);
-    variable long_sel : std_ulogic_vector(15 downto 0);
-    variable byte_sel : std_ulogic_vector(7 downto 0);
-    variable req : std_ulogic;
-    variable stall : std_ulogic;
-    variable addr : std_ulogic_vector(63 downto 0);
-    variable wdata : std_ulogic_vector(63 downto 0);
-    variable write_enable : std_ulogic;
-    variable do_update : std_ulogic;
-    variable two_dwords : std_ulogic;
-    variable done : std_ulogic;
-    variable data_permuted : std_ulogic_vector(63 downto 0);
-    variable data_trimmed : std_ulogic_vector(63 downto 0);
-    variable use_second : byte_sel_t;
-    variable trim_ctl : trim_ctl_t;
-    variable negative : std_ulogic;
-  begin
-    v := r;
-    req := '0';
-    stall := '0';
-    done := '0';
-    byte_sel := (others => '0');
-    addr := lsu_sum;
-    write_enable := '0';
-    do_update := '0';
-    two_dwords := or(r.second_bytes);
-    if r.load = '1' then
-      byte_offset := unsigned(r.addr(2 downto 0));
-      brev_lenm1 := "000";
-      if r.byte_reverse = '1' then
-        brev_lenm1 := unsigned(r.length(2 downto 0)) - 1;
-      end if;
-      negative := (r.length(3) and data_permuted(63)) or (r.length(2) and data_permuted(31)) or (r.length(1) and data_permuted(15)) or (r.length(0) and data_permuted(7));
-    end if;
-    case r.state is
-      when idle =>
-        if l_in.valid = '1' then
-          v.load := l_in.load;
-          v.addr := lsu_sum;
-          v.write_reg := l_in.write_reg;
-          v.length := l_in.length;
-          v.byte_reverse := l_in.byte_reverse;
-          v.sign_extend := l_in.sign_extend;
-          v.update := l_in.update;
-          v.update_reg := l_in.update_reg;
-          v.xerc := l_in.xerc;
-          v.reserve := l_in.reserve;
-          v.rc := l_in.rc;
-          v.nc := l_in.ci;
-          if lsu_sum(31 downto 28) = "1100" then
-            v.nc := '1';
-          end if;
-          long_sel := xfer_data_sel(l_in.length,v.addr(2 downto 0));
-          byte_sel := long_sel(7 downto 0);
-          v.second_bytes := long_sel(15 downto 8);
-          v.addr := lsu_sum;
-          if v.load = '0' then
-            byte_offset := unsigned(lsu_sum(2 downto 0));
-            brev_lenm1 := "000";
-            if l_in.byte_reverse = '1' then
-              brev_lenm1 := unsigned(l_in.length(2 downto 0)) - 1;
-            end if;
-          end if;
-          req := '1';
-          stall := '1';
-          if long_sel(15 downto 8) = "00000000" then
-            v.state := last_ack_wait;
-          else
-            v.state := second_req;
-          end if;
-        end if;
-      when second_req =>
-        addr := std_ulogic_vector(unsigned(r.addr(63 downto 3)) + 1) & "000";
-        byte_sel := r.second_bytes;
-        req := '1';
-        stall := '1';
-        v.state := first_ack_wait;
-      when first_ack_wait =>
-        stall := '1';
-        if d_in.valid = '1' then
-          v.state := last_ack_wait;
-          if r.load = '1' then
-            v.load_data := data_permuted;
-          end if;
-        end if;
-      when last_ack_wait =>
-        stall := '1';
-        if d_in.valid = '1' then
-          write_enable := r.load;
-          if r.load = '1' and r.update = '1' then
-            v.state := ld_update;
-          else
-            do_update := r.update;
-            stall := '0';
-            done := '1';
-            v.state := idle;
-          end if;
-        end if;
-      when ld_update =>
-        do_update := '1';
-        v.state := idle;
-        done := '1';
-    end case;
-    d_out.valid <= req;
-    d_out.load <= v.load;
-    d_out.nc <= v.nc;
-    d_out.reserve <= v.reserve;
-    d_out.addr <= addr;
-    d_out.data <= v.store_data;
-    d_out.byte_sel <= byte_sel;
-    l_out.valid <= done;
-    if do_update = '1' then
-      l_out.write_enable <= '1';
-      l_out.write_reg <= r.update_reg;
-      l_out.write_data <= r.addr;
-    else
-      l_out.write_enable <= write_enable;
-      l_out.write_reg <= r.write_reg;
-      l_out.write_data <= data_trimmed;
-    end if;
-    l_out.xerc <= r.xerc;
-    l_out.rc <= r.rc and done;
-    l_out.store_done <= d_in.store_done;
-    stall_out <= stall;
-    rin <= v;
-  end process;
-end behave;

data/tests/parser_tests/test_microwatt_logical_pp.vhd

@@ -1,87 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.decode_types.all;
- 
-entity logical is
-  port(
-    rs : in std_ulogic_vector(63 downto 0);
-    rb : in std_ulogic_vector(63 downto 0);
-    op : in insn_type_t;
-    invert_in : in std_ulogic;
-    invert_out : in std_ulogic;
-    result : out std_ulogic_vector(63 downto 0);
-    datalen : in std_logic_vector(3 downto 0);
-    popcnt : out std_ulogic_vector(63 downto 0);
-    parity : out std_ulogic_vector(63 downto 0));
-end entity logical;
- 
-architecture behaviour of logical is
-   
-  subtype twobit is unsigned(1 downto 0);
-   
-  type twobit32 is array(range 0 to 31) of twobit;
-  signal pc2 : twobit32;
-   
-  subtype threebit is unsigned(2 downto 0);
-   
-  type threebit16 is array(range 0 to 15) of threebit;
-  signal pc4 : threebit16;
-   
-  subtype fourbit is unsigned(3 downto 0);
-   
-  type fourbit8 is array(range 0 to 7) of fourbit;
-  signal pc8 : fourbit8;
-   
-  subtype sixbit is unsigned(5 downto 0);
-   
-  type sixbit2 is array(range 0 to 1) of sixbit;
-  signal pc32 : sixbit2;
-  signal par0 : std_ulogic;
-  signal par1 : std_ulogic;
-begin
- 
-   
-  logical_0 : process(all)
-    variable rb_adj : std_ulogic_vector(63 downto 0);
-    variable tmp : std_ulogic_vector(63 downto 0);
-  begin
-    rb_adj := rb;
-    if invert_in = '1' then
-      rb_adj := rb;
-    end if;
-    case op is
-      when op_and =>
-        tmp := rs and rb_adj;
-      when op_or =>
-        tmp := rs or rb_adj;
-      when others =>
-        tmp := rs xor rb_adj;
-    end case;
-    result <= tmp;
-    if invert_out = '1' then
-      result <= tmp;
-    end if;
-    ;
-    ;
-    popcnt <= (others => '0');
-    if datalen(3 downto 2) = "00" then
-      ;
-    elsif datalen(3) = '0' then
-      ;
-    else
-      popcnt(6 downto 0) <= std_ulogic_vector(('0' & pc32(0)) + ('0' & pc32(1)));
-    end if;
-    par0 <= rs(0) xor rs(8) xor rs(16) xor rs(24);
-    par1 <= rs(32) xor rs(40) xor rs(48) xor rs(56);
-    parity <= (others => '0');
-    if datalen(3) = '1' then
-      parity(0) <= par0 xor par1;
-    else
-      parity(0) <= par0;
-      parity(32) <= par1;
-    end if;
-  end process;
-end behaviour;

data/tests/parser_tests/test_microwatt_multiply_pp.vhd

@@ -1,84 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.common.all;
-use work.decode_types.all;
- 
-entity multiply is
-  generic(
-    pipeline_depth : natural16 := 16);
-  port(
-    clk : in std_logic;
-    m_in : in execute1tomultiplytype;
-    m_out : out multiplytoexecute1type);
-end entity multiply;
- 
-architecture behaviour of multiply is
-  signal m : execute1tomultiplytype;
-   
-  type multiply_pipeline_stage is record
-    valid : std_ulogic;
-    insn_type : insn_type_t;
-    data : signed(129 downto 0);
-    is_32bit : std_ulogic;
-  end record;
-  constant multiplypipelinestageinit : multiply_pipeline_stage := (valid => '0',insn_type => op_illegal,is_32bit => '0',data => (others => '0'));
-   
-  type multiply_pipeline_type is array(range 0 to pipeline_depth - 1) of multiply_pipeline_stage;
-  constant multiplypipelineinit : multiply_pipeline_type := (others => multiplypipelinestageinit);
-   
-  type reg_type is record
-    multiply_pipeline : multiply_pipeline_type;
-  end record;
-  signal r : reg_type;
-  signal rin : reg_type := (multiply_pipeline => multiplypipelineinit);
-begin
- 
-   
-  multiply_0 : process(clk)
-  begin
-    if rising_edge(clk) then
-      m <= m_in;
-      r <= rin;
-    end if;
-  end process;
-   
-  multiply_1 : process(all)
-    variable v : reg_type;
-    variable d : std_ulogic_vector(129 downto 0);
-    variable d2 : std_ulogic_vector(63 downto 0);
-    variable ov : std_ulogic;
-  begin
-    v := r;
-    m_out <= multiplytoexecute1init;
-    v.multiply_pipeline(0).valid := m.valid;
-    v.multiply_pipeline(0).insn_type := m.insn_type;
-    v.multiply_pipeline(0).data := signed(m.data1) * signed(m.data2);
-    v.multiply_pipeline(0).is_32bit := m.is_32bit;
-    d := std_ulogic_vector(v.multiply_pipeline(pipeline_depth - 1).data);
-    ov := '0';
-    case v.multiply_pipeline(pipeline_depth - 1).insn_type is
-      when op_mul_l64 =>
-        d2 := d(63 downto 0);
-        if v.multiply_pipeline(pipeline_depth - 1).is_32bit = '1' then
-          ov := (or(d(63 downto 31))) and (and(d(63 downto 31)));
-        else
-          ov := (or(d(127 downto 63))) and (and(d(127 downto 63)));
-        end if;
-      when op_mul_h32 =>
-        d2 := d(63 downto 32) & d(63 downto 32);
-      when op_mul_h64 =>
-        d2 := d(127 downto 64);
-      when others =>
-        d2 := (others => '0');
-    end case;
-    m_out.write_reg_data <= d2;
-    m_out.overflow <= ov;
-    if v.multiply_pipeline(pipeline_depth - 1).valid = '1' then
-      m_out.valid <= '1';
-    end if;
-    rin <= v;
-  end process;
-end behaviour;

data/tests/parser_tests/test_microwatt_multiply_tb_pp.vhd

@@ -1,75 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.decode_types.all;
-use work.common.all;
-use work.glibc_random.all;
-use work.ppc_fx_insns.all;
- 
-entity multiply_tb is
-end entity multiply_tb;
- 
-architecture behave of multiply_tb is
-  signal clk : std_ulogic;
-  constant clk_period : time := 10 ns;
-  constant pipeline_depth : integer := 4;
-  signal m1 : execute1tomultiplytype;
-  signal m2 : multiplytoexecute1type;
-begin
- 
-  multiply_0 : entity work.multiply
-    port map(
-      clk => clk,
-      m_in => m1,
-      m_out => m2);
-   
-   
-  clk_process : process
-  begin
-    clk <= '0';
-    wait clk_period / 2;
-    clk <= '1';
-    wait clk_period / 2;
-  end process;
-   
-  stim_process : process
-    variable ra : std_ulogic_vector(63 downto 0);
-    variable rb : std_ulogic_vector(63 downto 0);
-    variable rt : std_ulogic_vector(63 downto 0);
-    variable behave_rt : std_ulogic_vector(63 downto 0);
-    variable si : std_ulogic_vector(15 downto 0);
-  begin
-    wait clk_period;
-    m1.valid <= '1';
-    m1.insn_type <= op_mul_l64;
-    m1.data1 <= '0' & x"0000000000001000";
-    m1.data2 <= '0' & x"0000000000001111";
-    wait clk_period;
-    assert m2.valid = '0';
-    m1.valid <= '0';
-    wait clk_period;
-    assert m2.valid = '0';
-    wait clk_period;
-    assert m2.valid = '0';
-    wait clk_period;
-    assert m2.valid = '1';
-    assert m2.write_reg_data = x"0000000001111000";
-    wait clk_period;
-    assert m2.valid = '0';
-    m1.valid <= '1';
-    wait clk_period;
-    assert m2.valid = '0';
-    m1.valid <= '0';
-    wait clk_period * (pipeline_depth - 1);
-    assert m2.valid = '1';
-    assert m2.write_reg_data = x"0000000001111000";
-    ;
-    ;
-    ;
-    assert false
-      report "end of test" severity failure;
-    wait ;
-  end process;
-end behave;

data/tests/parser_tests/test_microwatt_plru_pp.vhd

@@ -1,46 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.math_real.all;
- 
-entity plru is
-  generic(
-    bits : positive2 := 2);
-  port(
-    clk : in std_ulogic;
-    rst : in std_ulogic;
-    acc : in std_ulogic_vector(bits - 1 downto 0);
-    acc_en : in std_ulogic;
-    lru : out std_ulogic_vector(bits - 1 downto 0));
-end entity plru;
- 
-architecture rtl of plru is
-  constant count : positive := 2 ** bits - 1;
-   
-  subtype node_t is integer range 0 to count;
-   
-  type tree_t is array(range node_t) of std_ulogic;
-  signal tree : tree_t;
-begin
- 
-   
-  get_lru : process(tree)
-    variable node : node_t;
-  begin
-    node := 0;
-  end process;
-   
-  update_lru : process(clk)
-    variable node : node_t;
-    variable abit : std_ulogic;
-  begin
-    if rising_edge(clk) then
-      if rst = '1' then
-        tree <= (others => '0');
-      elsif acc_en = '1' then
-        node := 0;
-      end if;
-    end if;
-  end process;
-end rtl;

data/tests/parser_tests/test_microwatt_plru_tb_pp.vhd

@@ -1,93 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-library work;
-use work.common.all;
-use work.wishbone_types.all;
- 
-entity plru_tb is
-end entity plru_tb;
- 
-architecture behave of plru_tb is
-  signal clk : std_ulogic;
-  signal rst : std_ulogic;
-  constant clk_period : time := 10 ns;
-  signal acc_en : std_ulogic;
-  signal acc : std_ulogic_vector(2 downto 0);
-  signal lru : std_ulogic_vector(2 downto 0);
-begin
- 
-  plru0 : entity work.plru
-    port map(
-      clk => clk,
-      rst => rst,
-      acc => acc,
-      acc_en => acc_en,
-      lru => lru);
-   
-   
-  clk_process : process
-  begin
-    clk <= '0';
-    wait clk_period / 2;
-    clk <= '1';
-    wait clk_period / 2;
-  end process;
-   
-  rst_process : process
-  begin
-    rst <= '1';
-    wait 2 * clk_period;
-    rst <= '0';
-    wait ;
-  end process;
-   
-  stim : process
-  begin
-    wait 4 * clk_period;
-    report "accessing 1:";
-    acc <= "001";
-    acc_en <= '1';
-    wait clk_period;
-    report "lru:" & to_hstring(lru);
-    report "accessing 2:";
-    acc <= "010";
-    wait clk_period;
-    report "lru:" & to_hstring(lru);
-    report "accessing 7:";
-    acc <= "111";
-    wait clk_period;
-    report "lru:" & to_hstring(lru);
-    report "accessing 4:";
-    acc <= "100";
-    wait clk_period;
-    report "lru:" & to_hstring(lru);
-    report "accessing 3:";
-    acc <= "011";
-    wait clk_period;
-    report "lru:" & to_hstring(lru);
-    report "accessing 5:";
-    acc <= "101";
-    wait clk_period;
-    report "lru:" & to_hstring(lru);
-    report "accessing 3:";
-    acc <= "011";
-    wait clk_period;
-    report "lru:" & to_hstring(lru);
-    report "accessing 5:";
-    acc <= "101";
-    wait clk_period;
-    report "lru:" & to_hstring(lru);
-    report "accessing 6:";
-    acc <= "110";
-    wait clk_period;
-    report "lru:" & to_hstring(lru);
-    report "accessing 0:";
-    acc <= "000";
-    wait clk_period;
-    report "lru:" & to_hstring(lru);
-    assert false
-      report "end of test" severity failure;
-    wait ;
-  end process;
-end behave;