udb 0.1.14 → 0.1.15

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: '033857ac50551c786b5857f54a78a91f6a2c3d8c46554eb0dae62cbc489b9ab4'
-  data.tar.gz: dce0e09b88581e3cc6dc13de86d7e5a72c8c2377e66aca53994d6a0c239ec3a2
+  metadata.gz: 0c4e7059a447d2f815adfb15bfe6152a60e2a238167245bc3fbaf26de73859c3
+  data.tar.gz: fd573fc43f859b0fd40cb3a283015af2aa4a7f33fe1c2c2b1285f6e5fde2a3a9
 SHA512:
-  metadata.gz: 5b0efc566225e863a99ba9c1818a47ef57590bdd7d8e5f37a3937b6c7fb7b94bfe409d96a9e0c886fcb74e2eac312bc3023ebe72e55128043f578acf6a576dca
-  data.tar.gz: fe01c90f6363a506d6191b2a6ac5f39acb91ca241a00a83951b83e2af680895cb56b140d826f0010bb00f21e723794b03415f543afe41c54fe701d942ed2e444
+  metadata.gz: cf76d15fcf97eba3aa58b29fbb4f6a45d486541f1bcba5ca35b3d7b15a67e957e9d60eaf9b7a1e2b7e53eeb4ddf0b6d9f0b1fbbdc6ba89befcfbbb5b1b8804be
+  data.tar.gz: a3051975397d7412e1cd39c2a4e352f2d42763c0d2663fb553198ca9c175725dbf47694f48a56c8615219b5d457a1aed20cb89b1094d75382279dfe23c619d63

data/.data/cfgs/example_rv64_with_overlay.yaml

@@ -563,8 +563,8 @@ params:
   SV48X4_TRANSLATION: true
   SV57X4_TRANSLATION: false
   VMID_WIDTH: 8
-  STVEC_MODE_DIRECT: true
-  STVEC_MODE_VECTORED: true
+  STVEC_MODES: [0, 1]
+  STVEC_BASE_ALIGNMENT_VECTORED: 0x4
   SATP_MODE_BARE: true
   VSSTAGE_MODE_BARE: true
   REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT: true
@@ -591,16 +591,15 @@ params:
   MTVEC_MODES: [0, 1]
   MTVEC_ACCESS: rw
   MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
-  MTVEC_BASE_ALIGNMENT_DIRECT: 4
-  MTVEC_BASE_ALIGNMENT_VECTORED: 4
+  MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
+  MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
   MSTATUS_FS_LEGAL_VALUES: [0, 1, 2, 3]
   HW_MSTATUS_FS_DIRTY_UPDATE: precise
   MSTATUS_VS_LEGAL_VALUES: [0, 1, 2, 3]
   HW_MSTATUS_VS_DIRTY_UPDATE: precise
   FORCE_UPGRADE_CBO_INVAL_TO_FLUSH: true
   REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT: true
-  VSTVEC_MODE_DIRECT: true
-  VSTVEC_MODE_VECTORED: true
+  VSTVEC_MODES: [0, 1]
   TRAP_ON_ECALL_FROM_VS: true
   TRAP_ON_ECALL_FROM_S: true
   TRAP_ON_ECALL_FROM_M: true

data/.data/cfgs/mc100-32-full-example.yaml

@@ -50,8 +50,8 @@ params:
   MTVEC_ACCESS: rw
   MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
   MTVEC_MODES: [0, 1]
-  MTVEC_BASE_ALIGNMENT_DIRECT: 4
-  MTVEC_BASE_ALIGNMENT_VECTORED: 4
+  MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
+  MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
   MUTABLE_MISA_C: false
   MUTABLE_MISA_M: false
   TIME_CSR_IMPLEMENTED: false

data/.data/cfgs/qc_iu.yaml

@@ -186,6 +186,6 @@ params:
   MCOUNTINHIBIT_IMPLEMENTED: true
   MTVEC_ACCESS: rw
   MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
-  MTVEC_BASE_ALIGNMENT_DIRECT: 4
-  MTVEC_BASE_ALIGNMENT_VECTORED: 4
+  MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
+  MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
   TIME_CSR_IMPLEMENTED: true

data/.data/cfgs/rv32-riscv-tests.yaml

@@ -58,8 +58,8 @@ params:
   MCOUNTINHIBIT_IMPLEMENTED: true
   MTVEC_ACCESS: rw
   MTVEC_MODES: [0, 1]
-  MTVEC_BASE_ALIGNMENT_DIRECT: 4
-  MTVEC_BASE_ALIGNMENT_VECTORED: 4
+  MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
+  MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
   MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
   MUTABLE_MISA_C: false
   MUTABLE_MISA_M: false
@@ -188,8 +188,8 @@ params:
       false,
       false,
     ]
-  STVEC_MODE_DIRECT: true
-  STVEC_MODE_VECTORED: true
+  STVEC_MODES: [0, 1]
+  STVEC_BASE_ALIGNMENT_VECTORED: 0x4
   SATP_MODE_BARE: true
   TRAP_ON_ECALL_FROM_S: true
   MSTATUS_VS_LEGAL_VALUES: [0]

data/.data/cfgs/rv32-vector.yaml

@@ -68,8 +68,8 @@ params:
   MCOUNTINHIBIT_IMPLEMENTED: true
   MTVEC_ACCESS: rw
   MTVEC_MODES: [0, 1]
-  MTVEC_BASE_ALIGNMENT_DIRECT: 4
-  MTVEC_BASE_ALIGNMENT_VECTORED: 4
+  MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
+  MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
   MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
   MUTABLE_MISA_C: false
   MUTABLE_MISA_D: false
@@ -200,8 +200,8 @@ params:
       false,
       false,
     ]
-  STVEC_MODE_DIRECT: true
-  STVEC_MODE_VECTORED: true
+  STVEC_MODES: [0, 1]
+  STVEC_BASE_ALIGNMENT_VECTORED: 0x4
   SATP_MODE_BARE: true
   TRAP_ON_ECALL_FROM_S: true
   TRAP_ON_ECALL_FROM_U: true

data/.data/cfgs/rv64-riscv-tests.yaml

@@ -56,8 +56,8 @@ params:
   MCOUNTINHIBIT_IMPLEMENTED: true
   MTVEC_ACCESS: rw
   MTVEC_MODES: [0, 1]
-  MTVEC_BASE_ALIGNMENT_DIRECT: 4
-  MTVEC_BASE_ALIGNMENT_VECTORED: 4
+  MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
+  MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
   MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
   MUTABLE_MISA_C: false
   MUTABLE_MISA_M: false
@@ -186,8 +186,8 @@ params:
       false,
       false,
     ]
-  STVEC_MODE_DIRECT: true
-  STVEC_MODE_VECTORED: true
+  STVEC_MODES: [0, 1]
+  STVEC_BASE_ALIGNMENT_VECTORED: 0x4
   SATP_MODE_BARE: true
   TRAP_ON_ECALL_FROM_S: true
   TRAP_ON_ECALL_FROM_U: true

data/.data/cfgs/rv64-vector.yaml

@@ -67,8 +67,8 @@ params:
   MCOUNTINHIBIT_IMPLEMENTED: true
   MTVEC_ACCESS: rw
   MTVEC_MODES: [0, 1]
-  MTVEC_BASE_ALIGNMENT_DIRECT: 4
-  MTVEC_BASE_ALIGNMENT_VECTORED: 4
+  MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
+  MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
   MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
   MUTABLE_MISA_C: false
   MUTABLE_MISA_D: false
@@ -198,8 +198,8 @@ params:
       false,
       false,
     ]
-  STVEC_MODE_DIRECT: true
-  STVEC_MODE_VECTORED: true
+  STVEC_MODES: [0, 1]
+  STVEC_BASE_ALIGNMENT_VECTORED: 0x4
   SATP_MODE_BARE: true
   TRAP_ON_ECALL_FROM_S: true
   TRAP_ON_ECALL_FROM_U: true

data/.data/spec/schemas/README.adoc

@@ -80,6 +80,9 @@ version should be released.  Follow these steps:
 . The CI `schema-release` workflow will automatically publish the new version
   as a GitHub release under the tag `schemas/<schema_name>/<version>` when the
   changes are merged to `main`.
+. Published schema version assets are immutable. If a release already exists
+  with different content, the publish workflow fails; bump the schema `$id`
+  instead of overwriting an existing version.
 . Previous schema versions remain available via their GitHub release tags and
   at `https://riscv.github.io/riscv-unified-db/schemas/<schema_name>/<old-version>/<schema_name>`.
 

data/.data/spec/schemas/schema_defs.json

@@ -1,6 +1,6 @@
 {
   "$schema": "http://json-schema.org/draft-07/schema#",
-  "$id": "v0.1",
+  "$id": "v0.2",
   "title": "Common patterns used by all schemas",
   "$defs": {
     "$source": {
@@ -863,7 +863,7 @@
       "description": "An unsigned power of 2 that fits in 32 bits",
       "type": "integer",
       "enum": [
-        1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4095, 8192, 16384,
+        1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384,
         32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304,
         8388608, 16777216, 33554432, 67108864, 134217728, 268435456, 536870912,
         1073741824, 2147483648
@@ -873,7 +873,7 @@
       "description": "An unsigned power of 2 that fits in 64 bits",
       "type": "integer",
       "enum": [
-        1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4095, 8192, 16384,
+        1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384,
         32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304,
         8388608, 16777216, 33554432, 67108864, 134217728, 268435456, 536870912,
         1073741824, 2147483648, 4294967296, 8589934592, 17179869184,

data/.data/spec/std/isa/csr/H/hcounteren.layout

@@ -76,7 +76,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.TM`# .2+h! [.rotate]#`mcounteren.TM`# .2+h! [.rotate]#`scounteren.TM`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.TM`# .2+h! [.rotate]#`mcounteren.TM`# .2+h! [.rotate]#`scounteren.TM`# 2+^.>! `time` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -116,7 +116,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.IR`# .2+h! [.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.IR`# .2+h! [.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# 2+^.>! `instret` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -154,7 +154,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM<%= hpm_num %>`# .2+h! [.rotate]#`mcounteren.HPM<%= hpm_num %>`# .2+h! [.rotate]#`scounteren.HPM<%= hpm_num %>`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM<%= hpm_num %>`# .2+h! [.rotate]#`mcounteren.HPM<%= hpm_num %>`# .2+h! [.rotate]#`scounteren.HPM<%= hpm_num %>`# 2+^.>! `hpmcounter<%= hpm_num %>` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`

data/.data/spec/std/isa/csr/H/hcounteren.yaml

@@ -79,7 +79,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.TM`# .2+h! [.rotate]#`mcounteren.TM`# .2+h! [.rotate]#`scounteren.TM`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.TM`# .2+h! [.rotate]#`mcounteren.TM`# .2+h! [.rotate]#`scounteren.TM`# 2+^.>! `time` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -119,7 +119,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.IR`# .2+h! [.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.IR`# .2+h! [.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# 2+^.>! `instret` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -156,7 +156,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM3`# .2+h! [.rotate]#`mcounteren.HPM3`# .2+h! [.rotate]#`scounteren.HPM3`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM3`# .2+h! [.rotate]#`mcounteren.HPM3`# .2+h! [.rotate]#`scounteren.HPM3`# 2+^.>! `hpmcounter3` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -193,7 +193,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM4`# .2+h! [.rotate]#`mcounteren.HPM4`# .2+h! [.rotate]#`scounteren.HPM4`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM4`# .2+h! [.rotate]#`mcounteren.HPM4`# .2+h! [.rotate]#`scounteren.HPM4`# 2+^.>! `hpmcounter4` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -230,7 +230,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM5`# .2+h! [.rotate]#`mcounteren.HPM5`# .2+h! [.rotate]#`scounteren.HPM5`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM5`# .2+h! [.rotate]#`mcounteren.HPM5`# .2+h! [.rotate]#`scounteren.HPM5`# 2+^.>! `hpmcounter5` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -267,7 +267,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM6`# .2+h! [.rotate]#`mcounteren.HPM6`# .2+h! [.rotate]#`scounteren.HPM6`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM6`# .2+h! [.rotate]#`mcounteren.HPM6`# .2+h! [.rotate]#`scounteren.HPM6`# 2+^.>! `hpmcounter6` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -304,7 +304,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM7`# .2+h! [.rotate]#`mcounteren.HPM7`# .2+h! [.rotate]#`scounteren.HPM7`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM7`# .2+h! [.rotate]#`mcounteren.HPM7`# .2+h! [.rotate]#`scounteren.HPM7`# 2+^.>! `hpmcounter7` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -341,7 +341,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM8`# .2+h! [.rotate]#`mcounteren.HPM8`# .2+h! [.rotate]#`scounteren.HPM8`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM8`# .2+h! [.rotate]#`mcounteren.HPM8`# .2+h! [.rotate]#`scounteren.HPM8`# 2+^.>! `hpmcounter8` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -378,7 +378,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM9`# .2+h! [.rotate]#`mcounteren.HPM9`# .2+h! [.rotate]#`scounteren.HPM9`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM9`# .2+h! [.rotate]#`mcounteren.HPM9`# .2+h! [.rotate]#`scounteren.HPM9`# 2+^.>! `hpmcounter9` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -415,7 +415,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM10`# .2+h! [.rotate]#`mcounteren.HPM10`# .2+h! [.rotate]#`scounteren.HPM10`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM10`# .2+h! [.rotate]#`mcounteren.HPM10`# .2+h! [.rotate]#`scounteren.HPM10`# 2+^.>! `hpmcounter10` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -452,7 +452,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM11`# .2+h! [.rotate]#`mcounteren.HPM11`# .2+h! [.rotate]#`scounteren.HPM11`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM11`# .2+h! [.rotate]#`mcounteren.HPM11`# .2+h! [.rotate]#`scounteren.HPM11`# 2+^.>! `hpmcounter11` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -489,7 +489,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM12`# .2+h! [.rotate]#`mcounteren.HPM12`# .2+h! [.rotate]#`scounteren.HPM12`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM12`# .2+h! [.rotate]#`mcounteren.HPM12`# .2+h! [.rotate]#`scounteren.HPM12`# 2+^.>! `hpmcounter12` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -526,7 +526,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM13`# .2+h! [.rotate]#`mcounteren.HPM13`# .2+h! [.rotate]#`scounteren.HPM13`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM13`# .2+h! [.rotate]#`mcounteren.HPM13`# .2+h! [.rotate]#`scounteren.HPM13`# 2+^.>! `hpmcounter13` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -563,7 +563,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM14`# .2+h! [.rotate]#`mcounteren.HPM14`# .2+h! [.rotate]#`scounteren.HPM14`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM14`# .2+h! [.rotate]#`mcounteren.HPM14`# .2+h! [.rotate]#`scounteren.HPM14`# 2+^.>! `hpmcounter14` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -600,7 +600,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM15`# .2+h! [.rotate]#`mcounteren.HPM15`# .2+h! [.rotate]#`scounteren.HPM15`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM15`# .2+h! [.rotate]#`mcounteren.HPM15`# .2+h! [.rotate]#`scounteren.HPM15`# 2+^.>! `hpmcounter15` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -637,7 +637,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM16`# .2+h! [.rotate]#`mcounteren.HPM16`# .2+h! [.rotate]#`scounteren.HPM16`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM16`# .2+h! [.rotate]#`mcounteren.HPM16`# .2+h! [.rotate]#`scounteren.HPM16`# 2+^.>! `hpmcounter16` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -674,7 +674,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM17`# .2+h! [.rotate]#`mcounteren.HPM17`# .2+h! [.rotate]#`scounteren.HPM17`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM17`# .2+h! [.rotate]#`mcounteren.HPM17`# .2+h! [.rotate]#`scounteren.HPM17`# 2+^.>! `hpmcounter17` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -711,7 +711,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM18`# .2+h! [.rotate]#`mcounteren.HPM18`# .2+h! [.rotate]#`scounteren.HPM18`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM18`# .2+h! [.rotate]#`mcounteren.HPM18`# .2+h! [.rotate]#`scounteren.HPM18`# 2+^.>! `hpmcounter18` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -748,7 +748,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM19`# .2+h! [.rotate]#`mcounteren.HPM19`# .2+h! [.rotate]#`scounteren.HPM19`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM19`# .2+h! [.rotate]#`mcounteren.HPM19`# .2+h! [.rotate]#`scounteren.HPM19`# 2+^.>! `hpmcounter19` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -785,7 +785,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM20`# .2+h! [.rotate]#`mcounteren.HPM20`# .2+h! [.rotate]#`scounteren.HPM20`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM20`# .2+h! [.rotate]#`mcounteren.HPM20`# .2+h! [.rotate]#`scounteren.HPM20`# 2+^.>! `hpmcounter20` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -822,7 +822,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM21`# .2+h! [.rotate]#`mcounteren.HPM21`# .2+h! [.rotate]#`scounteren.HPM21`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM21`# .2+h! [.rotate]#`mcounteren.HPM21`# .2+h! [.rotate]#`scounteren.HPM21`# 2+^.>! `hpmcounter21` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -859,7 +859,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM22`# .2+h! [.rotate]#`mcounteren.HPM22`# .2+h! [.rotate]#`scounteren.HPM22`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM22`# .2+h! [.rotate]#`mcounteren.HPM22`# .2+h! [.rotate]#`scounteren.HPM22`# 2+^.>! `hpmcounter22` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -896,7 +896,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM23`# .2+h! [.rotate]#`mcounteren.HPM23`# .2+h! [.rotate]#`scounteren.HPM23`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM23`# .2+h! [.rotate]#`mcounteren.HPM23`# .2+h! [.rotate]#`scounteren.HPM23`# 2+^.>! `hpmcounter23` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -933,7 +933,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM24`# .2+h! [.rotate]#`mcounteren.HPM24`# .2+h! [.rotate]#`scounteren.HPM24`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM24`# .2+h! [.rotate]#`mcounteren.HPM24`# .2+h! [.rotate]#`scounteren.HPM24`# 2+^.>! `hpmcounter24` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -970,7 +970,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM25`# .2+h! [.rotate]#`mcounteren.HPM25`# .2+h! [.rotate]#`scounteren.HPM25`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM25`# .2+h! [.rotate]#`mcounteren.HPM25`# .2+h! [.rotate]#`scounteren.HPM25`# 2+^.>! `hpmcounter25` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1007,7 +1007,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM26`# .2+h! [.rotate]#`mcounteren.HPM26`# .2+h! [.rotate]#`scounteren.HPM26`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM26`# .2+h! [.rotate]#`mcounteren.HPM26`# .2+h! [.rotate]#`scounteren.HPM26`# 2+^.>! `hpmcounter26` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1044,7 +1044,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM27`# .2+h! [.rotate]#`mcounteren.HPM27`# .2+h! [.rotate]#`scounteren.HPM27`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM27`# .2+h! [.rotate]#`mcounteren.HPM27`# .2+h! [.rotate]#`scounteren.HPM27`# 2+^.>! `hpmcounter27` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1081,7 +1081,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM28`# .2+h! [.rotate]#`mcounteren.HPM28`# .2+h! [.rotate]#`scounteren.HPM28`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM28`# .2+h! [.rotate]#`mcounteren.HPM28`# .2+h! [.rotate]#`scounteren.HPM28`# 2+^.>! `hpmcounter28` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1118,7 +1118,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM29`# .2+h! [.rotate]#`mcounteren.HPM29`# .2+h! [.rotate]#`scounteren.HPM29`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM29`# .2+h! [.rotate]#`mcounteren.HPM29`# .2+h! [.rotate]#`scounteren.HPM29`# 2+^.>! `hpmcounter29` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1155,7 +1155,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM30`# .2+h! [.rotate]#`mcounteren.HPM30`# .2+h! [.rotate]#`scounteren.HPM30`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM30`# .2+h! [.rotate]#`mcounteren.HPM30`# .2+h! [.rotate]#`scounteren.HPM30`# 2+^.>! `hpmcounter30` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`
@@ -1192,7 +1192,7 @@ fields:
 
       [separator="!",%autowidth]
       !===
-      .2+h! [.rotate]#`hcounteren.HPM31`# .2+h! [.rotate]#`mcounteren.HPM31`# .2+h! [.rotate]#`scounteren.HPM31`# 2+^.>! `cycle` access behavior
+      .2+h! [.rotate]#`hcounteren.HPM31`# .2+h! [.rotate]#`mcounteren.HPM31`# .2+h! [.rotate]#`scounteren.HPM31`# 2+^.>! `hpmcounter31` access behavior
       .>h! VS-mode .>h! VU-mode
 
       ! 0 ! 0 ! - ! `IllegalInstruction` ! `IllegalInstruction`

data/.data/spec/std/isa/csr/H/htinst.yaml

@@ -10,9 +10,9 @@ address: 0x64a
 writable: true
 long_name: Hypervisor Trap Instruction Register
 description: |
-  When a trap is taken into HS-mode, mtinst is written with a value that, if nonzero,
+  When a trap is taken into HS-mode, htinst is written with a value that, if nonzero,
   provides information about the instruction that trapped, to assist software in handling the trap.
-  The values that may be written to mtinst on a trap are documented in TODO.
+  The values that may be written to htinst on a trap are documented in TODO.
 
   htinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap.
 priv_mode: S
@@ -34,7 +34,7 @@ fields:
           || (TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED != "always zero")
           || (TINST_VALUE_ON_LOAD_ACCESS_FAULT != "always zero")
           || (TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED != "always zero")
-          || (TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT != "always_zero")
+          || (TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT != "always zero")
           || (TINST_VALUE_ON_UCALL != "always zero")
           || (TINST_VALUE_ON_SCALL != "always zero")
           || (TINST_VALUE_ON_MCALL != "always zero")

data/.data/spec/std/isa/csr/H/htval.yaml

@@ -19,8 +19,8 @@ description: |
   Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in htval corresponds to the faulting portion of the access as indicated by the virtual address in stval. For instruction guest-page faults on systems with variable-length instructions, a nonzero htval corresponds to the faulting portion of the instruction as indicated by the virtual address in stval.
 
   htval is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any.
-priv_mode: M
-length: MXLEN
+priv_mode: S
+length: SXLEN
 definedBy:
   extension:
     name: H
@@ -38,5 +38,5 @@ fields:
         return CsrFieldType::RO;
       }
     description: |
-      Exception-specific information for a trap into M-mode.
+      Exception-specific information for a trap into HS-mode.
     reset_value: UNDEFINED_LEGAL

data/.data/spec/std/isa/csr/H/mtinst.yaml

@@ -34,7 +34,7 @@ fields:
           || (TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED != "always zero")
           || (TINST_VALUE_ON_LOAD_ACCESS_FAULT != "always zero")
           || (TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED != "always zero")
-          || (TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT != "always_zero")
+          || (TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT != "always zero")
           || (TINST_VALUE_ON_UCALL != "always zero")
           || (TINST_VALUE_ON_SCALL != "always zero")
           || (TINST_VALUE_ON_MCALL != "always zero")

data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml

@@ -48,7 +48,7 @@ fields:
       allOf:
         - xlen: 64
         - extension:
-            name: M
+            name: Sm
     description: If set, then counting of events in M-mode is inhibited.
     reset_value: UNDEFINED_LEGAL
 

data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml

@@ -24,7 +24,7 @@ fields:
     type: RW
     definedBy:
       extension:
-        name: M
+        name: Sm
     description: If set, then counting of events in M-mode is inhibited.
     reset_value: UNDEFINED_LEGAL
 

data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml

@@ -45,7 +45,7 @@ fields:
       allOf:
         - xlen: 64
         - extension:
-            name: M
+            name: Sm
     description: If set, then counting of events in M-mode is inhibited.
     reset_value: UNDEFINED_LEGAL
 

data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml

@@ -24,7 +24,7 @@ fields:
     type: RW
     definedBy:
       extension:
-        name: M
+        name: Sm
     description: If set, then counting of events in M-mode is inhibited.
     reset_value: UNDEFINED_LEGAL
 

data/.data/spec/std/isa/csr/Sscofpmf/scountovf.layout

@@ -41,7 +41,7 @@ fields:
       [when="HPM_COUNTER_EN[<%= of_num %>] == false"]
       This field is read-only zero because the counter is not enabled.
     type(): |
-      return HPM_COUNTER_EN[<%= of_num %>] ? CsrFieldType::RO : CsrFieldType::ROH;
+      return HPM_COUNTER_EN[<%= of_num %>] ? CsrFieldType::ROH : CsrFieldType::RO;
     reset_value(): |
       return HPM_COUNTER_EN[<%= of_num %>] ? UNDEFINED_LEGAL : 0;
 <%- end -%>