udb 0.1.14 → 0.1.15

data/.data/spec/std/isa/inst/F/fsw.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: fs2
       location: 24-20
     - name: xs1
@@ -29,7 +30,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/I/sd.yaml

@@ -51,7 +51,7 @@ operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
   if (xlen() == 32) {
-    if (implemented?(ExtensionName::Zclsd)) {
+    if (implemented?(ExtensionName::Zilsd)) {
       data = {X[xs2 + 1], X[xs2]};
     } else {
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);

data/.data/spec/std/isa/inst/Q/fadd.q.yaml

@@ -11,8 +11,8 @@ definedBy:
   extension:
     name: Q
 description: |
-  `fadd.q` is analogous to `fadd.d` and performs double-precision floating-point addition between
-  `qs1` and `qs2` and writes the final result to `qd`.
+  `fadd.q` is analogous to `fadd.d` and performs quad-precision floating-point addition between
+  `fs1` and `fs2` and writes the final result to `fd`.
 assembly: fd, fs1, fs2, rm
 encoding:
   match: 0000011------------------1010011

data/.data/spec/std/isa/inst/Q/fclass.q.yaml

@@ -8,13 +8,13 @@ kind: instruction
 name: fclass.q
 long_name: Floating-Point Classify Quad-Precision
 description: |
-  The `fclass.q` instruction examines the value in floating-point register `rs1` and writes to integer
-  register `rd` a 10-bit mask that indicates the class of the floating-point number.
+  The `fclass.q` instruction examines the value in floating-point register `fs1` and writes to integer
+  register `xd` a 10-bit mask that indicates the class of the floating-point number.
 
-  The format of the mask is described in table given below. The corresponding bit in `rd`
-  will be set if the property is true and clear otherwise. All other bits in `rd` are cleared.
+  The format of the mask is described in table given below. The corresponding bit in `xd`
+  will be set if the property is true and clear otherwise. All other bits in `xd` are cleared.
 
-  Note that exactly one bit in `rd` will be set. `fclass.q` does not set the floating-point
+  Note that exactly one bit in `xd` will be set. `fclass.q` does not set the floating-point
   exception flags.
 
   .Format of result of `fclass` instruction.

data/.data/spec/std/isa/inst/Q/fleq.q.yaml

@@ -13,7 +13,6 @@ description: |
 
   `fleq.q` is defined like `fle.q`, except that quiet _NaN_ inputs do not cause the invalid
   operation exception flag to be set.
-  This instruction is encoded like its `flt` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/inst/Q/fli.q.yaml

@@ -9,7 +9,7 @@ name: fli.q
 long_name: Floating-Point Load Immediate Quad-Precision
 description: |
   The `fli.q` instruction loads one of 32 quad-precision floating-point constants, encoded in the `xs1`
-  field, into floating-point register `rd`.
+  field, into floating-point register `fd`.
   `fli.q` is encoded like `fmv.w.x`, but with _fmt_ = Q.
 definedBy:
   extension:

data/.data/spec/std/isa/inst/Q/flq.yaml

@@ -24,6 +24,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: fd

data/.data/spec/std/isa/inst/Q/fltq.q.yaml

@@ -13,7 +13,6 @@ description: |
 
   `fltq.q` is defined like `flt.q`, except that quiet _NaN_ inputs do not cause the invalid
   operation exception flag to be set.
-  This instruction is encoded like its `fle` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/inst/Q/fmaxm.q.yaml

@@ -13,7 +13,6 @@ description: |
   If both inputs are _NaN_s, the result is the canonical _NaN_.
   If either input is _NaN_, the result is the canonical _NaN_.
   Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
-  This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/inst/Q/fminm.q.yaml

@@ -13,7 +13,6 @@ description: |
   If both inputs are _NaN_s, the result is the canonical _NaN_.
   If either input is _NaN_, the result is the canonical _NaN_.
   Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
-  This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/inst/Q/fmvp.q.x.yaml

@@ -8,7 +8,7 @@ kind: instruction
 name: fmvp.q.x
 long_name: Floating-Point Move Pair from Integer Registers to Quad-Precision Register
 description: |
-  The `fmvp.q.x` instruction moves a double-precision number from a pair of integer registers into
+  The `fmvp.q.x` instruction moves a quad-precision number from a pair of integer registers into
   a floating-point register.
   Integer registers `xs1` and `xs2` supply bits 63:0 and 127:64, respectively; the result is written to
   floating-point register `fd`.

data/.data/spec/std/isa/inst/Q/fsq.yaml

@@ -23,6 +23,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: fs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/V/vmv.v.i.yaml

@@ -24,6 +24,7 @@ encoding:
   variables:
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/Zcb/c.mul.yaml

@@ -28,6 +28,7 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |
 
   if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) {

data/.data/spec/std/isa/inst/Zcb/c.not.yaml

@@ -25,6 +25,7 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |
 
   if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {

data/.data/spec/std/isa/inst/Zcb/c.zext.b.yaml

@@ -14,9 +14,7 @@ description: |
 
 definedBy:
   extension:
-    allOf:
-      - name: Zcb
-      - name: Zbb
+    name: Zcb
 assembly: xd
 encoding:
   match: 100111---1100001
@@ -28,12 +26,9 @@ access:
   u: always
   vs: always
   vu: always
+data_independent_timing: true
 operation(): |2
 
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
     raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
   }

data/.data/spec/std/isa/inst/Zcb/c.zext.w.yaml

@@ -17,7 +17,7 @@ definedBy:
     - extension:
         allOf:
           - name: Zcb
-          - name: Zbb
+          - name: Zba
 assembly: xd
 encoding:
   match: 100111---1110001

data/.data/spec/std/isa/inst/Zcmop/c.mop.1.yaml

@@ -28,4 +28,6 @@ access:
   vs: always
   vu: always
 data_independent_timing: false
+hints:
+  - { $ref: inst/Zicfiss/c.sspush.yaml# }
 operation(): "" #do nothing

data/.data/spec/std/isa/inst/Zcmop/c.mop.5.yaml

@@ -28,4 +28,6 @@ access:
   vs: always
   vu: always
 data_independent_timing: false
+hints:
+  - { $ref: inst/Zicfiss/c.sspopchk.yaml# }
 operation(): "" #do nothing

data/.data/spec/std/isa/inst/Zcmop/c.mop.N.layout

@@ -42,4 +42,11 @@ access:
   vs: always
   vu: always
 data_independent_timing: false
+<% if n == 1 -%>
+hints:
+  - { $ref: inst/Zicfiss/c.sspush.yaml# }
+<% elsif n == 5 -%>
+hints:
+  - { $ref: inst/Zicfiss/c.sspopchk.yaml# }
+<% end -%>
 operation(): "" #do nothing

data/.data/spec/std/isa/inst/Zfa/fli.s.yaml

@@ -25,5 +25,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/Zfa/fmaxm.s.yaml

@@ -27,5 +27,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/Zfa/fminm.s.yaml

@@ -27,5 +27,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/Zfa/fround.s.yaml

@@ -33,7 +33,7 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);

data/.data/spec/std/isa/inst/Zfa/froundnx.s.yaml

@@ -27,5 +27,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: true
+data_independent_timing: false
 operation(): |

data/.data/spec/std/isa/inst/Zfh/flh.yaml

@@ -8,7 +8,7 @@ kind: instruction
 name: flh
 long_name: Half-precision floating-point load
 description: |
-  The `flh` instruction loads a single-precision floating-point value from memory at address _xs1_ + _imm_ into floating-point register _xd_.
+  The `flh` instruction loads a half-precision floating-point value from memory at address _xs1_ + _imm_ into floating-point register _xd_.
 
   `flh` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
 
@@ -16,13 +16,16 @@ description: |
 
 definedBy:
   extension:
-    name: Zfhmin
+    anyOf:
+      - name: Zfhmin
+      - name: Zfbfmin
 assembly: fd, imm(xs1)
 encoding:
   match: "-----------------001-----0000111"
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: fd

data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml

@@ -14,7 +14,9 @@ description: |
   the payloads of non-canonical NaNs are preserved.
 definedBy:
   extension:
-    name: Zfhmin
+    anyOf:
+      - name: Zfhmin
+      - name: Zfbfmin
 assembly: fd, xs1
 encoding:
   match: 111101000000-----000-----1010011

data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml

@@ -9,7 +9,9 @@ name: fmv.x.h
 long_name: Move half-precision value from floating-point to integer register
 definedBy:
   extension:
-    name: Zfhmin
+    anyOf:
+      - name: Zfhmin
+      - name: Zfbfmin
 assembly: xd, fs1
 description: |
   Moves the half-precision value in floating-point register fs1 represented in IEEE 754-2008

data/.data/spec/std/isa/inst/Zfh/fsh.yaml

@@ -19,13 +19,16 @@ description: |
 
 definedBy:
   extension:
-    name: Zfhmin
+    anyOf:
+      - name: Zfhmin
+      - name: Zfbfmin
 assembly: fs2, imm(xs1)
 encoding:
   match: "-----------------001-----0100111"
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: fs2

data/.data/spec/std/isa/inst/Zicfiss/c.sspopchk.yaml

@@ -0,0 +1,30 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: c.sspopchk
+long_name: Compressed Shadow Stack Pop and Check
+description: |
+  C.SSPOPCHK pops a value from the shadow stack and checks it against link
+  register `x5`.
+
+  This instruction uses the `c.mop.5` codepoint provided by Zcmop and expands
+  to `sspopchk x5`.
+definedBy:
+  extension:
+    allOf:
+      - name: Zicfiss
+      - name: Zcmop
+assembly: x5
+encoding:
+  match: "0110001010000001"
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zicfiss/c.sspush.yaml

@@ -0,0 +1,29 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: c.sspush
+long_name: Compressed Shadow Stack Push
+description: |
+  C.SSPUSH pushes link register `x1` to the shadow stack.
+
+  This instruction uses the `c.mop.1` codepoint provided by Zcmop and expands
+  to `sspush x1`.
+definedBy:
+  extension:
+    allOf:
+      - name: Zicfiss
+      - name: Zcmop
+assembly: x1
+encoding:
+  match: "0110000010000001"
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zicond/czero.eqz.yaml

@@ -30,6 +30,6 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   X[xd] = (X[xs2] == 0) ? 0 : X[xs1];

data/.data/spec/std/isa/inst/Zicond/czero.nez.yaml

@@ -30,6 +30,6 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   X[xd] = (X[xs2] != 0) ? 0 : X[xs1];

data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml

@@ -34,6 +34,18 @@ access:
   vs: always
   vu: always
 pseudoinstructions:
+  - when: xd == 0 && csr == 0x001
+    to: fsflags xs1
+  - when: xd == 0 && csr == 0x002
+    to: fsrm xs1
+  - when: xd == 0 && csr == 0x003
+    to: fscsr xs1
+  - when: csr == 0x001
+    to: fsflags xd, xs1
+  - when: csr == 0x002
+    to: fsrm xd, xs1
+  - when: csr == 0x003
+    to: fscsr xd, xs1
   - when: xd == 0
     to: csrw csr, xs1
 operation(): |

data/.data/spec/std/isa/inst/Zilx/lxd.yaml

@@ -0,0 +1,38 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxd
+long_name: Load indexed doubleword
+description: |
+  Load 64 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1001000----------011-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = read_memory(64, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxh.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxh
+long_name: Load indexed halfword
+description: |
+  Load 16 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+  Sign extend the result to XLEN.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1001000----------001-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = sext(read_memory(16, virtual_address, $encoding), 16);

data/.data/spec/std/isa/inst/Zilx/lxhu.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxhu
+long_name: Load indexed halfword unsigned
+description: |
+  Load 16 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+  Zero extend the result to XLEN.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1001000----------101-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = read_memory(16, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsb.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsb
+long_name: Load scaled indexed byte
+description: |
+  Load 8 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+  Sign extend the result to XLEN.
+
+  The `lxb` mnemonic is an assembler pseudoinstruction for `lxsb`.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------000-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+pseudoinstructions:
+  - when: "true"
+    to: lxb xd, (xs2), xs1
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = sext(read_memory(8, virtual_address, $encoding), 8);

data/.data/spec/std/isa/inst/Zilx/lxsbu.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsbu
+long_name: Load scaled indexed byte unsigned
+description: |
+  Load 8 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+  Zero extend the result to XLEN.
+
+  The `lxbu` mnemonic is an assembler pseudoinstruction for `lxsbu`.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------100-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+pseudoinstructions:
+  - when: "true"
+    to: lxbu xd, (xs2), xs1
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = read_memory(8, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsd.yaml

@@ -0,0 +1,38 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsd
+long_name: Load scaled indexed doubleword
+description: |
+  Load 64 bits of data into register `xd` from the effective address
+  `X[xs2] + (X[xs1] << 3)`, where `xs2` is the base and `xs1` is the index.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------011-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1] `<< 3);
+
+  X[xd] = read_memory(64, virtual_address, $encoding);