udb 0.1.14 → 0.1.15

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Files changed (256) hide show
  1. checksums.yaml +4 -4
  2. data/.data/cfgs/example_rv64_with_overlay.yaml +5 -6
  3. data/.data/cfgs/mc100-32-full-example.yaml +2 -2
  4. data/.data/cfgs/qc_iu.yaml +2 -2
  5. data/.data/cfgs/rv32-riscv-tests.yaml +4 -4
  6. data/.data/cfgs/rv32-vector.yaml +4 -4
  7. data/.data/cfgs/rv64-riscv-tests.yaml +4 -4
  8. data/.data/cfgs/rv64-vector.yaml +4 -4
  9. data/.data/spec/schemas/README.adoc +3 -0
  10. data/.data/spec/schemas/schema_defs.json +3 -3
  11. data/.data/spec/std/isa/csr/H/hcounteren.layout +3 -3
  12. data/.data/spec/std/isa/csr/H/hcounteren.yaml +31 -31
  13. data/.data/spec/std/isa/csr/H/htinst.yaml +3 -3
  14. data/.data/spec/std/isa/csr/H/htval.yaml +3 -3
  15. data/.data/spec/std/isa/csr/H/mtinst.yaml +1 -1
  16. data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml +1 -1
  17. data/.data/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml +1 -1
  18. data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml +1 -1
  19. data/.data/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml +1 -1
  20. data/.data/spec/std/isa/csr/Sscofpmf/scountovf.layout +1 -1
  21. data/.data/spec/std/isa/csr/Sscofpmf/scountovf.yaml +29 -29
  22. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml +4 -4
  23. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml +1 -1
  24. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml +4 -4
  25. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml +1 -1
  26. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml +4 -4
  27. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml +1 -1
  28. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml +4 -4
  29. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml +1 -1
  30. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml +4 -4
  31. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml +1 -1
  32. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml +4 -4
  33. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml +1 -1
  34. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml +4 -4
  35. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml +1 -1
  36. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml +4 -4
  37. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml +1 -1
  38. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml +4 -4
  39. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml +1 -1
  40. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml +4 -4
  41. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml +1 -1
  42. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml +4 -4
  43. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml +1 -1
  44. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml +4 -4
  45. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml +1 -1
  46. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml +4 -4
  47. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml +1 -1
  48. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml +4 -4
  49. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml +1 -1
  50. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml +4 -4
  51. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml +1 -1
  52. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml +4 -4
  53. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml +1 -1
  54. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml +4 -4
  55. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml +1 -1
  56. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml +4 -4
  57. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml +1 -1
  58. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml +4 -4
  59. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml +1 -1
  60. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml +4 -4
  61. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml +1 -1
  62. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml +4 -4
  63. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml +4 -4
  64. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml +1 -1
  65. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml +4 -4
  66. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml +1 -1
  67. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml +1 -1
  68. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml +4 -4
  69. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml +1 -1
  70. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml +4 -4
  71. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml +1 -1
  72. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml +4 -4
  73. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml +1 -1
  74. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml +4 -4
  75. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml +1 -1
  76. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml +4 -4
  77. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml +1 -1
  78. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml +4 -4
  79. data/.data/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml +1 -1
  80. data/.data/spec/std/isa/csr/Zihpm/mhpmcounterN.layout +4 -4
  81. data/.data/spec/std/isa/csr/Zihpm/mhpmcounterNh.layout +1 -1
  82. data/.data/spec/std/isa/csr/hstatus.yaml +1 -1
  83. data/.data/spec/std/isa/csr/mcycle.yaml +6 -6
  84. data/.data/spec/std/isa/csr/minstret.yaml +3 -3
  85. data/.data/spec/std/isa/csr/minstreth.yaml +1 -1
  86. data/.data/spec/std/isa/csr/mstatus.yaml +13 -19
  87. data/.data/spec/std/isa/csr/mtvec.yaml +16 -57
  88. data/.data/spec/std/isa/csr/sie.yaml +30 -4
  89. data/.data/spec/std/isa/csr/sip.yaml +16 -2
  90. data/.data/spec/std/isa/csr/stvec.yaml +11 -12
  91. data/.data/spec/std/isa/csr/vstval.yaml +1 -1
  92. data/.data/spec/std/isa/csr/vstvec.yaml +14 -15
  93. data/.data/spec/std/isa/ext/Q.yaml +1 -1
  94. data/.data/spec/std/isa/ext/Shlcofideleg.yaml +24 -0
  95. data/.data/spec/std/isa/ext/Shvstvecd.yaml +2 -2
  96. data/.data/spec/std/isa/ext/Sspm.yaml +5 -0
  97. data/.data/spec/std/isa/ext/Sstvecd.yaml +2 -2
  98. data/.data/spec/std/isa/ext/Sstvecv.yaml +2 -2
  99. data/.data/spec/std/isa/ext/Supm.yaml +17 -0
  100. data/.data/spec/std/isa/ext/Zcb.yaml +3 -0
  101. data/.data/spec/std/isa/ext/Zfbfmin.yaml +3 -5
  102. data/.data/spec/std/isa/ext/Ziccid.yaml +29 -0
  103. data/.data/spec/std/isa/ext/Zicfilp.yaml +5 -1
  104. data/.data/spec/std/isa/ext/Zicfiss.yaml +20 -1
  105. data/.data/spec/std/isa/ext/Zihpm.yaml +3 -0
  106. data/.data/spec/std/isa/ext/Zilx.yaml +58 -0
  107. data/.data/spec/std/isa/ext/Zkt.yaml +33 -1
  108. data/.data/spec/std/isa/ext/Zvabd.yaml +21 -0
  109. data/.data/spec/std/isa/ext/Zvbc.yaml +3 -0
  110. data/.data/spec/std/isa/ext/Zvkb.yaml +3 -0
  111. data/.data/spec/std/isa/ext/Zvkg.yaml +3 -0
  112. data/.data/spec/std/isa/ext/Zvkned.yaml +3 -0
  113. data/.data/spec/std/isa/ext/Zvknha.yaml +3 -0
  114. data/.data/spec/std/isa/ext/Zvknhb.yaml +4 -2
  115. data/.data/spec/std/isa/ext/Zvksed.yaml +3 -0
  116. data/.data/spec/std/isa/ext/Zvksh.yaml +3 -0
  117. data/.data/spec/std/isa/ext/Zvkt.yaml +3 -0
  118. data/.data/spec/std/isa/inst/C/c.add.yaml +1 -0
  119. data/.data/spec/std/isa/inst/C/c.addi.yaml +1 -0
  120. data/.data/spec/std/isa/inst/C/c.addiw.yaml +1 -0
  121. data/.data/spec/std/isa/inst/C/c.addw.yaml +1 -0
  122. data/.data/spec/std/isa/inst/C/c.and.yaml +1 -0
  123. data/.data/spec/std/isa/inst/C/c.andi.yaml +1 -0
  124. data/.data/spec/std/isa/inst/C/c.lui.yaml +1 -0
  125. data/.data/spec/std/isa/inst/C/c.mv.yaml +1 -0
  126. data/.data/spec/std/isa/inst/C/c.nop.yaml +13 -2
  127. data/.data/spec/std/isa/inst/C/c.or.yaml +1 -0
  128. data/.data/spec/std/isa/inst/C/c.slli.yaml +1 -0
  129. data/.data/spec/std/isa/inst/C/c.srai.yaml +1 -0
  130. data/.data/spec/std/isa/inst/C/c.srli.yaml +1 -0
  131. data/.data/spec/std/isa/inst/C/c.sub.yaml +1 -0
  132. data/.data/spec/std/isa/inst/C/c.subw.yaml +1 -0
  133. data/.data/spec/std/isa/inst/C/c.xor.yaml +1 -0
  134. data/.data/spec/std/isa/inst/D/fld.yaml +1 -0
  135. data/.data/spec/std/isa/inst/D/fsd.yaml +1 -0
  136. data/.data/spec/std/isa/inst/F/fadd.s.yaml +1 -1
  137. data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml +1 -1
  138. data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml +1 -1
  139. data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml +1 -1
  140. data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml +1 -1
  141. data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml +1 -1
  142. data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml +1 -1
  143. data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml +1 -1
  144. data/.data/spec/std/isa/inst/F/fdiv.s.yaml +1 -1
  145. data/.data/spec/std/isa/inst/F/feq.s.yaml +1 -1
  146. data/.data/spec/std/isa/inst/F/fle.s.yaml +1 -1
  147. data/.data/spec/std/isa/inst/F/fleq.s.yaml +1 -1
  148. data/.data/spec/std/isa/inst/F/flt.s.yaml +1 -1
  149. data/.data/spec/std/isa/inst/F/fltq.s.yaml +1 -1
  150. data/.data/spec/std/isa/inst/F/flw.yaml +2 -1
  151. data/.data/spec/std/isa/inst/F/fmadd.s.yaml +1 -1
  152. data/.data/spec/std/isa/inst/F/fmax.s.yaml +1 -1
  153. data/.data/spec/std/isa/inst/F/fmin.s.yaml +1 -1
  154. data/.data/spec/std/isa/inst/F/fmsub.s.yaml +1 -1
  155. data/.data/spec/std/isa/inst/F/fmul.s.yaml +1 -1
  156. data/.data/spec/std/isa/inst/F/fmv.w.x.yaml +1 -1
  157. data/.data/spec/std/isa/inst/F/fmv.x.w.yaml +1 -1
  158. data/.data/spec/std/isa/inst/F/fnmadd.s.yaml +1 -1
  159. data/.data/spec/std/isa/inst/F/fnmsub.s.yaml +1 -1
  160. data/.data/spec/std/isa/inst/F/fsgnj.s.yaml +1 -1
  161. data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml +1 -1
  162. data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml +1 -1
  163. data/.data/spec/std/isa/inst/F/fsqrt.s.yaml +1 -1
  164. data/.data/spec/std/isa/inst/F/fsub.s.yaml +1 -1
  165. data/.data/spec/std/isa/inst/F/fsw.yaml +2 -1
  166. data/.data/spec/std/isa/inst/I/sd.yaml +1 -1
  167. data/.data/spec/std/isa/inst/Q/fadd.q.yaml +2 -2
  168. data/.data/spec/std/isa/inst/Q/fclass.q.yaml +5 -5
  169. data/.data/spec/std/isa/inst/Q/fleq.q.yaml +0 -1
  170. data/.data/spec/std/isa/inst/Q/fli.q.yaml +1 -1
  171. data/.data/spec/std/isa/inst/Q/flq.yaml +1 -0
  172. data/.data/spec/std/isa/inst/Q/fltq.q.yaml +0 -1
  173. data/.data/spec/std/isa/inst/Q/fmaxm.q.yaml +0 -1
  174. data/.data/spec/std/isa/inst/Q/fminm.q.yaml +0 -1
  175. data/.data/spec/std/isa/inst/Q/fmvp.q.x.yaml +1 -1
  176. data/.data/spec/std/isa/inst/Q/fsq.yaml +1 -0
  177. data/.data/spec/std/isa/inst/V/vmv.v.i.yaml +1 -0
  178. data/.data/spec/std/isa/inst/Zcb/c.mul.yaml +1 -0
  179. data/.data/spec/std/isa/inst/Zcb/c.not.yaml +1 -0
  180. data/.data/spec/std/isa/inst/Zcb/c.zext.b.yaml +2 -7
  181. data/.data/spec/std/isa/inst/Zcb/c.zext.w.yaml +1 -1
  182. data/.data/spec/std/isa/inst/Zcmop/c.mop.1.yaml +2 -0
  183. data/.data/spec/std/isa/inst/Zcmop/c.mop.5.yaml +2 -0
  184. data/.data/spec/std/isa/inst/Zcmop/c.mop.N.layout +7 -0
  185. data/.data/spec/std/isa/inst/Zfa/fli.s.yaml +1 -1
  186. data/.data/spec/std/isa/inst/Zfa/fmaxm.s.yaml +1 -1
  187. data/.data/spec/std/isa/inst/Zfa/fminm.s.yaml +1 -1
  188. data/.data/spec/std/isa/inst/Zfa/fround.s.yaml +1 -1
  189. data/.data/spec/std/isa/inst/Zfa/froundnx.s.yaml +1 -1
  190. data/.data/spec/std/isa/inst/Zfh/flh.yaml +5 -2
  191. data/.data/spec/std/isa/inst/Zfh/fmv.h.x.yaml +3 -1
  192. data/.data/spec/std/isa/inst/Zfh/fmv.x.h.yaml +3 -1
  193. data/.data/spec/std/isa/inst/Zfh/fsh.yaml +4 -1
  194. data/.data/spec/std/isa/inst/Zicfiss/c.sspopchk.yaml +30 -0
  195. data/.data/spec/std/isa/inst/Zicfiss/c.sspush.yaml +29 -0
  196. data/.data/spec/std/isa/inst/Zicond/czero.eqz.yaml +1 -1
  197. data/.data/spec/std/isa/inst/Zicond/czero.nez.yaml +1 -1
  198. data/.data/spec/std/isa/inst/Zicsr/csrrw.yaml +12 -0
  199. data/.data/spec/std/isa/inst/Zilx/lxd.yaml +38 -0
  200. data/.data/spec/std/isa/inst/Zilx/lxh.yaml +35 -0
  201. data/.data/spec/std/isa/inst/Zilx/lxhu.yaml +35 -0
  202. data/.data/spec/std/isa/inst/Zilx/lxsb.yaml +40 -0
  203. data/.data/spec/std/isa/inst/Zilx/lxsbu.yaml +40 -0
  204. data/.data/spec/std/isa/inst/Zilx/lxsd.yaml +38 -0
  205. data/.data/spec/std/isa/inst/Zilx/lxsh.yaml +35 -0
  206. data/.data/spec/std/isa/inst/Zilx/lxshu.yaml +35 -0
  207. data/.data/spec/std/isa/inst/Zilx/lxsuwb.yaml +40 -0
  208. data/.data/spec/std/isa/inst/Zilx/lxsuwbu.yaml +40 -0
  209. data/.data/spec/std/isa/inst/Zilx/lxsuwd.yaml +39 -0
  210. data/.data/spec/std/isa/inst/Zilx/lxsuwh.yaml +40 -0
  211. data/.data/spec/std/isa/inst/Zilx/lxsuwhu.yaml +40 -0
  212. data/.data/spec/std/isa/inst/Zilx/lxsuww.yaml +40 -0
  213. data/.data/spec/std/isa/inst/Zilx/lxsuwwu.yaml +40 -0
  214. data/.data/spec/std/isa/inst/Zilx/lxsw.yaml +35 -0
  215. data/.data/spec/std/isa/inst/Zilx/lxswu.yaml +39 -0
  216. data/.data/spec/std/isa/inst/Zilx/lxw.yaml +35 -0
  217. data/.data/spec/std/isa/inst/Zilx/lxwu.yaml +39 -0
  218. data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml +67 -0
  219. data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml +67 -0
  220. data/.data/spec/std/isa/inst/Zvabd/vabs.v.yaml +61 -0
  221. data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml +72 -0
  222. data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml +72 -0
  223. data/.data/spec/std/isa/isa/fp.idl +42 -18
  224. data/.data/spec/std/isa/param/CACHE_BLOCK_SIZE.yaml +70 -6
  225. data/.data/spec/std/isa/param/ELEN.yaml +27 -5
  226. data/.data/spec/std/isa/param/HCOUNTENABLE_EN.yaml +13 -0
  227. data/.data/spec/std/isa/param/HPM_COUNTER_EN.yaml +13 -3
  228. data/.data/spec/std/isa/param/HPM_EVENTS.yaml +0 -3
  229. data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml +8 -0
  230. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml +71 -65
  231. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml +71 -65
  232. data/.data/spec/std/isa/param/STVAL_WIDTH.yaml +3 -2
  233. data/.data/spec/std/isa/param/STVEC_BASE_ALIGNMENT_VECTORED.yaml +100 -0
  234. data/.data/spec/std/isa/param/STVEC_MODES.yaml +31 -0
  235. data/.data/spec/std/isa/param/SV32_VSMODE_TRANSLATION.yaml +1 -1
  236. data/.data/spec/std/isa/param/SXLEN.yaml +2 -2
  237. data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT.yaml +1 -1
  238. data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT.yaml +1 -1
  239. data/.data/spec/std/isa/param/TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT.yaml +1 -1
  240. data/.data/spec/std/isa/param/TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED.yaml +1 -1
  241. data/.data/spec/std/isa/param/TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED.yaml +1 -1
  242. data/.data/spec/std/isa/param/UXLEN.yaml +1 -1
  243. data/.data/spec/std/isa/param/VLEN.yaml +16 -7
  244. data/.data/spec/std/isa/param/VSTVEC_MODES.yaml +31 -0
  245. data/lib/udb/Z3_VERSION +1 -1
  246. data/lib/udb/obj/csr.rb +1 -1
  247. data/lib/udb/obj/csr_field.rb +1 -1
  248. data/lib/udb/obj/extension.rb +1 -1
  249. data/lib/udb/version.rb +1 -1
  250. data/lib/udb/version_spec.rb +1 -1
  251. data/lib/udb/z3.rb +29 -7
  252. metadata +37 -8
  253. data/.data/spec/std/isa/param/STVEC_MODE_DIRECT.yaml +0 -21
  254. data/.data/spec/std/isa/param/STVEC_MODE_VECTORED.yaml +0 -19
  255. data/.data/spec/std/isa/param/VSTVEC_MODE_DIRECT.yaml +0 -21
  256. data/.data/spec/std/isa/param/VSTVEC_MODE_VECTORED.yaml +0 -21
data/.data/spec/std/isa/ext/Zkt.yaml CHANGED
@@ -203,6 +203,21 @@ description: |
203
203
  | | ✓ | sraw _rd_, _rs1_, _rs2_ | 'sraw'
204
204
  |===
205
205
 
206
+ === Zicond (Conditional Zero)
207
+
208
+ All instructions are included.
209
+
210
+ [%header,cols="^1,^1,4,8"]
211
+ |===
212
+ |RV32
213
+ |RV64
214
+ |Mnemonic
215
+ |Instruction
216
+
217
+ | ✓ | ✓ | czero.eqz _rd_, _rs1_, _rs2_ | 'czero.eqz'
218
+ | ✓ | ✓ | czero.nez _rd_, _rs1_, _rs2_ | 'czero.nez'
219
+ |===
220
+
206
221
  === RVM (Multiply)
207
222
 
208
223
  Multiplication is included; division and remaindering excluded.
@@ -221,7 +236,7 @@ description: |
221
236
  | | ✓ | mulw _rd_, _rs1_, _rs2_ | 'mulw'
222
237
  |===
223
238
 
224
- === RVC (Compressed)
239
+ === Zca (Compressed)
225
240
 
226
241
  Same criteria as in RVI. Organised by quadrants.
227
242
 
@@ -250,6 +265,23 @@ description: |
250
265
  | ✓ | ✓ | c.add | 'c_add'
251
266
  |===
252
267
 
268
+ === Zcb Extension
269
+
270
+ These instructions are compressed versions of `I` and `M` instructions that are
271
+ included in `Zkt`.
272
+
273
+ [%header,cols="^1,^1,4,8"]
274
+ |===
275
+ |RV32
276
+ |RV64
277
+ |Mnemonic
278
+ |Instruction
279
+
280
+ | ✓ | ✓ | c.mul | 'c_mul'
281
+ | ✓ | ✓ | c.not | 'c_not'
282
+ | ✓ | ✓ | c.zext.b | 'c_zext_b'
283
+ |===
284
+
253
285
  === RVK (Scalar Cryptography)
254
286
 
255
287
  All K-specific instructions are included.
data/.data/spec/std/isa/ext/Zvabd.yaml ADDED
@@ -0,0 +1,21 @@
1
+ # Copyright (c) Alibaba Damo Academy
2
+ # SPDX-License-Identifier: BSD-3-Clause-Clear
3
+
4
+ # yaml-language-server: $schema=../../../schemas/ext_schema.json
5
+
6
+ $schema: "ext_schema.json#"
7
+ kind: extension
8
+ name: Zvabd
9
+ long_name: Vector Integer Absolute Difference
10
+ description: |
11
+ The Zvabd extension defines element-wise absolute difference instructions for
12
+ vectors of integers, including widening absolute-difference-and-accumulate
13
+ variants. These operations are widely used in image registration, object
14
+ recognition, motion estimation, and loop filters for video workloads.
15
+ type: unprivileged
16
+ versions:
17
+ - version: "0.7.0"
18
+ state: frozen
19
+ requirements:
20
+ extension:
21
+ name: Zve32x
data/.data/spec/std/isa/ext/Zvbc.yaml CHANGED
@@ -17,3 +17,6 @@ versions:
17
17
  - version: "1.0.0"
18
18
  state: ratified
19
19
  ratification_date: 2023-09
20
+ requirements:
21
+ extension:
22
+ name: Zve64x
data/.data/spec/std/isa/ext/Zvkb.yaml CHANGED
@@ -14,3 +14,6 @@ versions:
14
14
  - version: "1.0.0"
15
15
  state: ratified
16
16
  ratification_date: 2023-09
17
+ requirements:
18
+ extension:
19
+ name: Zve32x
data/.data/spec/std/isa/ext/Zvkg.yaml CHANGED
@@ -24,3 +24,6 @@ versions:
24
24
  - version: "1.0.0"
25
25
  state: ratified
26
26
  ratification_date: 2023-09
27
+ requirements:
28
+ extension:
29
+ name: Zve32x
data/.data/spec/std/isa/ext/Zvkned.yaml CHANGED
@@ -20,3 +20,6 @@ versions:
20
20
  - version: "1.0.0"
21
21
  state: ratified
22
22
  ratification_date: 2023-09
23
+ requirements:
24
+ extension:
25
+ name: Zve32x
data/.data/spec/std/isa/ext/Zvknha.yaml CHANGED
@@ -15,3 +15,6 @@ versions:
15
15
  - version: "1.0.0"
16
16
  state: ratified
17
17
  ratification_date: 2023-09
18
+ requirements:
19
+ extension:
20
+ name: Zve32x
data/.data/spec/std/isa/ext/Zvknhb.yaml CHANGED
@@ -17,5 +17,7 @@ versions:
17
17
  ratification_date: 2023-09
18
18
  requirements:
19
19
  extension:
20
- name: Zvknha
21
- version: "= 1.0.0"
20
+ allOf:
21
+ - name: Zvknha
22
+ version: "= 1.0.0"
23
+ - name: Zve64x
data/.data/spec/std/isa/ext/Zvksed.yaml CHANGED
@@ -22,3 +22,6 @@ versions:
22
22
  - version: "1.0.0"
23
23
  state: ratified
24
24
  ratification_date: 2023-09
25
+ requirements:
26
+ extension:
27
+ name: Zve32x
data/.data/spec/std/isa/ext/Zvksh.yaml CHANGED
@@ -18,3 +18,6 @@ versions:
18
18
  - version: "1.0.0"
19
19
  state: ratified
20
20
  ratification_date: 2023-09
21
+ requirements:
22
+ extension:
23
+ name: Zve32x
data/.data/spec/std/isa/ext/Zvkt.yaml CHANGED
@@ -26,3 +26,6 @@ versions:
26
26
  - version: "1.0.0"
27
27
  state: ratified
28
28
  ratification_date: 2023-09
29
+ requirements:
30
+ extension:
31
+ name: Zvl32b
data/.data/spec/std/isa/inst/C/c.add.yaml CHANGED
@@ -28,6 +28,7 @@ access:
28
28
  u: always
29
29
  vs: always
30
30
  vu: always
31
+ data_independent_timing: true
31
32
  hints:
32
33
  - { $ref: inst/Zihintntl/c.ntl.p1.yaml# }
33
34
  - { $ref: inst/Zihintntl/c.ntl.pall.yaml# }
data/.data/spec/std/isa/inst/C/c.addi.yaml CHANGED
@@ -31,6 +31,7 @@ access:
31
31
  u: always
32
32
  vs: always
33
33
  vu: always
34
+ data_independent_timing: true
34
35
  operation(): |
35
36
  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
36
37
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
data/.data/spec/std/isa/inst/C/c.addiw.yaml CHANGED
@@ -32,6 +32,7 @@ access:
32
32
  u: always
33
33
  vs: always
34
34
  vu: always
35
+ data_independent_timing: true
35
36
  operation(): |
36
37
  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
37
38
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
data/.data/spec/std/isa/inst/C/c.addw.yaml CHANGED
@@ -29,6 +29,7 @@ access:
29
29
  u: always
30
30
  vs: always
31
31
  vu: always
32
+ data_independent_timing: true
32
33
  operation(): |
33
34
  Bits<32> t0 = X[creg2reg(xd)][31:0];
34
35
  Bits<32> t1 = X[creg2reg(xs2)][31:0];
data/.data/spec/std/isa/inst/C/c.and.yaml CHANGED
@@ -27,6 +27,7 @@ access:
27
27
  u: always
28
28
  vs: always
29
29
  vu: always
30
+ data_independent_timing: true
30
31
  operation(): |
31
32
  XReg t0 = X[creg2reg(xd)];
32
33
  XReg t1 = X[creg2reg(xs2)];
data/.data/spec/std/isa/inst/C/c.andi.yaml CHANGED
@@ -28,6 +28,7 @@ access:
28
28
  u: always
29
29
  vs: always
30
30
  vu: always
31
+ data_independent_timing: true
31
32
  operation(): |
32
33
  # shamt is between 0-63
33
34
  X[creg2reg(xd)] = X[creg2reg(xd)] & $signed(imm);
data/.data/spec/std/isa/inst/C/c.lui.yaml CHANGED
@@ -31,6 +31,7 @@ access:
31
31
  u: always
32
32
  vs: always
33
33
  vu: always
34
+ data_independent_timing: true
34
35
  operation(): |
35
36
  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
36
37
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
data/.data/spec/std/isa/inst/C/c.mv.yaml CHANGED
@@ -28,6 +28,7 @@ access:
28
28
  u: always
29
29
  vs: always
30
30
  vu: always
31
+ data_independent_timing: true
31
32
  operation(): |
32
33
  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
33
34
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
data/.data/spec/std/isa/inst/C/c.nop.yaml CHANGED
@@ -8,18 +8,29 @@ kind: instruction
8
8
  name: c.nop
9
9
  long_name: Non-operation
10
10
  description: |
11
+ C.NOP does not change any user-visible state, except for advancing the pc and
12
+ accepting any HINTs.
11
13
  C.NOP expands into `addi x0, x0, 0`.
14
+ C.NOP with non-zero immediate values are HINTs.
12
15
  definedBy:
13
16
  extension:
14
17
  name: Zca
15
- assembly: ""
18
+ assembly: imm
16
19
  encoding:
17
- match: "0000000000000001"
20
+ match: 000-00000-----01
21
+ variables:
22
+ - name: imm
23
+ location: 12|6-2
24
+ sign_extend: true
25
+ pseudoinstructions:
26
+ - when: imm == 0
27
+ to: "c.nop"
18
28
  access:
19
29
  s: always
20
30
  u: always
21
31
  vs: always
22
32
  vu: always
33
+ data_independent_timing: true
23
34
  operation(): |
24
35
  if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
25
36
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
data/.data/spec/std/isa/inst/C/c.or.yaml CHANGED
@@ -27,6 +27,7 @@ access:
27
27
  u: always
28
28
  vs: always
29
29
  vu: always
30
+ data_independent_timing: true
30
31
  operation(): |
31
32
  XReg t0 = X[creg2reg(xd)];
32
33
  XReg t1 = X[creg2reg(xs2)];
data/.data/spec/std/isa/inst/C/c.slli.yaml CHANGED
@@ -36,6 +36,7 @@ access:
36
36
  u: always
37
37
  vs: always
38
38
  vu: always
39
+ data_independent_timing: true
39
40
  operation(): |
40
41
  # shamt is between 0-63
41
42
  X[xd] = X[xd] << shamt;
data/.data/spec/std/isa/inst/C/c.srai.yaml CHANGED
@@ -37,6 +37,7 @@ access:
37
37
  u: always
38
38
  vs: always
39
39
  vu: always
40
+ data_independent_timing: true
40
41
  operation(): |
41
42
  # shamt is between 0-63
42
43
  X[creg2reg(xd)] = X[creg2reg(xd)] >>> shamt;
data/.data/spec/std/isa/inst/C/c.srli.yaml CHANGED
@@ -37,6 +37,7 @@ access:
37
37
  u: always
38
38
  vs: always
39
39
  vu: always
40
+ data_independent_timing: true
40
41
  operation(): |
41
42
  # shamt is between 0-63
42
43
  X[creg2reg(xd)] = X[creg2reg(xd)] >> shamt;
data/.data/spec/std/isa/inst/C/c.sub.yaml CHANGED
@@ -27,6 +27,7 @@ access:
27
27
  u: always
28
28
  vs: always
29
29
  vu: always
30
+ data_independent_timing: true
30
31
  operation(): |
31
32
  XReg t0 = X[creg2reg(xd)];
32
33
  XReg t1 = X[creg2reg(xs2)];
data/.data/spec/std/isa/inst/C/c.subw.yaml CHANGED
@@ -29,6 +29,7 @@ access:
29
29
  u: always
30
30
  vs: always
31
31
  vu: always
32
+ data_independent_timing: true
32
33
  operation(): |
33
34
  Bits<32> t0 = X[creg2reg(xd)][31:0];
34
35
  Bits<32> t1 = X[creg2reg(xs2)][31:0];
data/.data/spec/std/isa/inst/C/c.xor.yaml CHANGED
@@ -27,6 +27,7 @@ access:
27
27
  u: always
28
28
  vs: always
29
29
  vu: always
30
+ data_independent_timing: true
30
31
  operation(): |
31
32
  XReg t0 = X[creg2reg(xd)];
32
33
  XReg t1 = X[creg2reg(xs2)];
data/.data/spec/std/isa/inst/D/fld.yaml CHANGED
@@ -21,6 +21,7 @@ encoding:
21
21
  variables:
22
22
  - name: imm
23
23
  location: 31-20
24
+ sign_extend: true
24
25
  - name: xs1
25
26
  location: 19-15
26
27
  - name: fd
data/.data/spec/std/isa/inst/D/fsd.yaml CHANGED
@@ -20,6 +20,7 @@ encoding:
20
20
  variables:
21
21
  - name: imm
22
22
  location: 31-25|11-7
23
+ sign_extend: true
23
24
  - name: fs2
24
25
  location: 24-20
25
26
  - name: xs1
data/.data/spec/std/isa/inst/F/fadd.s.yaml CHANGED
@@ -30,7 +30,7 @@ access:
30
30
  u: always
31
31
  vs: always
32
32
  vu: always
33
- data_independent_timing: true
33
+ data_independent_timing: false
34
34
  operation(): |
35
35
  check_f_ok($encoding);
36
36
  RoundingMode mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml CHANGED
@@ -30,7 +30,7 @@ access:
30
30
  u: always
31
31
  vs: always
32
32
  vu: always
33
- data_independent_timing: true
33
+ data_independent_timing: false
34
34
  operation(): |
35
35
  check_f_ok($encoding);
36
36
  RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml CHANGED
@@ -30,7 +30,7 @@ access:
30
30
  u: always
31
31
  vs: always
32
32
  vu: always
33
- data_independent_timing: true
33
+ data_independent_timing: false
34
34
  operation(): |
35
35
  check_f_ok($encoding);
36
36
  RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml CHANGED
@@ -30,7 +30,7 @@ access:
30
30
  u: always
31
31
  vs: always
32
32
  vu: always
33
- data_independent_timing: true
33
+ data_independent_timing: false
34
34
  operation(): |
35
35
  check_f_ok($encoding);
36
36
  RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml CHANGED
@@ -29,7 +29,7 @@ access:
29
29
  u: always
30
30
  vs: always
31
31
  vu: always
32
- data_independent_timing: true
32
+ data_independent_timing: false
33
33
  operation(): |
34
34
  check_f_ok($encoding);
35
35
  RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fcvt.s.wu.yaml CHANGED
@@ -37,7 +37,7 @@ access:
37
37
  u: always
38
38
  vs: always
39
39
  vu: always
40
- data_independent_timing: true
40
+ data_independent_timing: false
41
41
  operation(): |
42
42
  check_f_ok($encoding);
43
43
  RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml CHANGED
@@ -56,7 +56,7 @@ access:
56
56
  u: always
57
57
  vs: always
58
58
  vu: always
59
- data_independent_timing: true
59
+ data_independent_timing: false
60
60
  operation(): |
61
61
  check_f_ok($encoding);
62
62
  RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml CHANGED
@@ -55,7 +55,7 @@ access:
55
55
  u: always
56
56
  vs: always
57
57
  vu: always
58
- data_independent_timing: true
58
+ data_independent_timing: false
59
59
  operation(): |
60
60
  check_f_ok($encoding);
61
61
  RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fdiv.s.yaml CHANGED
@@ -30,7 +30,7 @@ access:
30
30
  u: always
31
31
  vs: always
32
32
  vu: always
33
- data_independent_timing: true
33
+ data_independent_timing: false
34
34
  operation(): |
35
35
  check_f_ok($encoding);
36
36
  RoundingMode mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/feq.s.yaml CHANGED
@@ -30,7 +30,7 @@ access:
30
30
  u: always
31
31
  vs: always
32
32
  vu: always
33
- data_independent_timing: true
33
+ data_independent_timing: false
34
34
  operation(): |
35
35
  check_f_ok($encoding);
36
36
 
data/.data/spec/std/isa/inst/F/fle.s.yaml CHANGED
@@ -30,7 +30,7 @@ access:
30
30
  u: always
31
31
  vs: always
32
32
  vu: always
33
- data_independent_timing: true
33
+ data_independent_timing: false
34
34
  operation(): |
35
35
  check_f_ok($encoding);
36
36
 
data/.data/spec/std/isa/inst/F/fleq.s.yaml CHANGED
@@ -28,7 +28,7 @@ access:
28
28
  u: always
29
29
  vs: always
30
30
  vu: always
31
- data_independent_timing: true
31
+ data_independent_timing: false
32
32
  operation(): |
33
33
  check_f_ok($encoding);
34
34
 
data/.data/spec/std/isa/inst/F/flt.s.yaml CHANGED
@@ -30,7 +30,7 @@ access:
30
30
  u: always
31
31
  vs: always
32
32
  vu: always
33
- data_independent_timing: true
33
+ data_independent_timing: false
34
34
  operation(): |
35
35
  check_f_ok($encoding);
36
36
 
data/.data/spec/std/isa/inst/F/fltq.s.yaml CHANGED
@@ -28,7 +28,7 @@ access:
28
28
  u: always
29
29
  vs: always
30
30
  vu: always
31
- data_independent_timing: true
31
+ data_independent_timing: false
32
32
  operation(): |
33
33
  check_f_ok($encoding);
34
34
 
data/.data/spec/std/isa/inst/F/flw.yaml CHANGED
@@ -20,6 +20,7 @@ encoding:
20
20
  variables:
21
21
  - name: imm
22
22
  location: 31-20
23
+ sign_extend: true
23
24
  - name: xs1
24
25
  location: 19-15
25
26
  - name: fd
@@ -29,7 +30,7 @@ access:
29
30
  u: always
30
31
  vs: always
31
32
  vu: always
32
- data_independent_timing: true
33
+ data_independent_timing: false
33
34
  operation(): |
34
35
  check_f_ok($encoding);
35
36
 
data/.data/spec/std/isa/inst/F/fmadd.s.yaml CHANGED
@@ -31,7 +31,7 @@ access:
31
31
  u: always
32
32
  vs: always
33
33
  vu: always
34
- data_independent_timing: true
34
+ data_independent_timing: false
35
35
  operation(): |
36
36
  check_f_ok($encoding);
37
37
  RoundingMode mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fmax.s.yaml CHANGED
@@ -37,7 +37,7 @@ access:
37
37
  u: always
38
38
  vs: always
39
39
  vu: always
40
- data_independent_timing: true
40
+ data_independent_timing: false
41
41
  operation(): |
42
42
  check_f_ok($encoding);
43
43
 
data/.data/spec/std/isa/inst/F/fmin.s.yaml CHANGED
@@ -37,7 +37,7 @@ access:
37
37
  u: always
38
38
  vs: always
39
39
  vu: always
40
- data_independent_timing: true
40
+ data_independent_timing: false
41
41
  operation(): |
42
42
  check_f_ok($encoding);
43
43
 
data/.data/spec/std/isa/inst/F/fmsub.s.yaml CHANGED
@@ -31,7 +31,7 @@ access:
31
31
  u: always
32
32
  vs: always
33
33
  vu: always
34
- data_independent_timing: true
34
+ data_independent_timing: false
35
35
  operation(): |
36
36
  check_f_ok($encoding);
37
37
  RoundingMode mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fmul.s.yaml CHANGED
@@ -30,7 +30,7 @@ access:
30
30
  u: always
31
31
  vs: always
32
32
  vu: always
33
- data_independent_timing: true
33
+ data_independent_timing: false
34
34
  operation(): |
35
35
  check_f_ok($encoding);
36
36
  RoundingMode mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fmv.w.x.yaml CHANGED
@@ -27,7 +27,7 @@ access:
27
27
  u: always
28
28
  vs: always
29
29
  vu: always
30
- data_independent_timing: true
30
+ data_independent_timing: false
31
31
  operation(): |
32
32
  check_f_ok($encoding);
33
33
 
data/.data/spec/std/isa/inst/F/fmv.x.w.yaml CHANGED
@@ -28,7 +28,7 @@ access:
28
28
  u: always
29
29
  vs: always
30
30
  vu: always
31
- data_independent_timing: true
31
+ data_independent_timing: false
32
32
  operation(): |
33
33
  check_f_ok($encoding);
34
34
 
data/.data/spec/std/isa/inst/F/fnmadd.s.yaml CHANGED
@@ -32,7 +32,7 @@ access:
32
32
  u: always
33
33
  vs: always
34
34
  vu: always
35
- data_independent_timing: true
35
+ data_independent_timing: false
36
36
  operation(): |
37
37
  check_f_ok($encoding);
38
38
  RoundingMode mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fnmsub.s.yaml CHANGED
@@ -32,7 +32,7 @@ access:
32
32
  u: always
33
33
  vs: always
34
34
  vu: always
35
- data_independent_timing: true
35
+ data_independent_timing: false
36
36
  operation(): |
37
37
  check_f_ok($encoding);
38
38
  RoundingMode mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fsgnj.s.yaml CHANGED
@@ -31,7 +31,7 @@ access:
31
31
  u: always
32
32
  vs: always
33
33
  vu: always
34
- data_independent_timing: true
34
+ data_independent_timing: false
35
35
  pseudoinstructions:
36
36
  - when: (fs2 == fs1)
37
37
  to: fmv.s fd, fs1
data/.data/spec/std/isa/inst/F/fsgnjn.s.yaml CHANGED
@@ -30,7 +30,7 @@ access:
30
30
  u: always
31
31
  vs: always
32
32
  vu: always
33
- data_independent_timing: true
33
+ data_independent_timing: false
34
34
  pseudoinstructions:
35
35
  - when: (fs2 == fs1)
36
36
  to: fneg.s fd, fs1
data/.data/spec/std/isa/inst/F/fsgnjx.s.yaml CHANGED
@@ -30,7 +30,7 @@ access:
30
30
  u: always
31
31
  vs: always
32
32
  vu: always
33
- data_independent_timing: true
33
+ data_independent_timing: false
34
34
  pseudoinstructions:
35
35
  - when: (fs2 == fs1)
36
36
  to: fabs.s fd, fs1
data/.data/spec/std/isa/inst/F/fsqrt.s.yaml CHANGED
@@ -27,7 +27,7 @@ access:
27
27
  u: always
28
28
  vs: always
29
29
  vu: always
30
- data_independent_timing: true
30
+ data_independent_timing: false
31
31
  operation(): |
32
32
  check_f_ok($encoding);
33
33
  RoundingMode mode = rm_to_mode(rm, $encoding);
data/.data/spec/std/isa/inst/F/fsub.s.yaml CHANGED
@@ -29,7 +29,7 @@ access:
29
29
  u: always
30
30
  vs: always
31
31
  vu: always
32
- data_independent_timing: true
32
+ data_independent_timing: false
33
33
  operation(): |
34
34
  check_f_ok($encoding);
35
35
  RoundingMode mode = rm_to_mode(rm, $encoding);