udb 0.1.14 → 0.1.15

data/.data/spec/std/isa/inst/Zilx/lxsh.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsh
+long_name: Load scaled indexed halfword
+description: |
+  Load 16 bits of data into register `xd` from the effective address
+  `X[xs2] + (X[xs1] << 1)`, where `xs2` is the base and `xs1` is the index.
+  Sign extend the result to XLEN.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------001-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1] `<< 1);
+
+  X[xd] = sext(read_memory(16, virtual_address, $encoding), 16);

data/.data/spec/std/isa/inst/Zilx/lxshu.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxshu
+long_name: Load scaled indexed halfword unsigned
+description: |
+  Load 16 bits of data into register `xd` from the effective address
+  `X[xs2] + (X[xs1] << 1)`, where `xs2` is the base and `xs1` is the index.
+  Zero extend the result to XLEN.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------101-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1] `<< 1);
+
+  X[xd] = read_memory(16, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsuwb.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuwb
+long_name: Load scaled indexed byte with unsigned word index
+description: |
+  Load 8 bits of data into register `xd` from the effective address
+  `X[xs2] + zext32(X[xs1])`, where `xs2` is the base and `xs1` is the index.
+  The index is zero-extended from `X[xs1][31:0]` before forming the address.
+  Sign extend the loaded byte to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------000-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1][31:0];
+
+  X[xd] = sext(read_memory(8, virtual_address, $encoding), 8);

data/.data/spec/std/isa/inst/Zilx/lxsuwbu.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuwbu
+long_name: Load scaled indexed byte unsigned with unsigned word index
+description: |
+  Load 8 bits of data into register `xd` from the effective address
+  `X[xs2] + zext32(X[xs1])`, where `xs2` is the base and `xs1` is the index.
+  The index is zero-extended from `X[xs1][31:0]` before forming the address.
+  Zero extend the loaded byte to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------100-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1][31:0];
+
+  X[xd] = read_memory(8, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsuwd.yaml

@@ -0,0 +1,39 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuwd
+long_name: Load scaled indexed doubleword with unsigned word index
+description: |
+  Load 64 bits of data into register `xd` from the effective address
+  `X[xs2] + (zext32(X[xs1]) << 3)`, where `xs2` is the base and `xs1` is the
+  index. The index is zero-extended from `X[xs1][31:0]` before scaling.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------011-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1][31:0] `<< 3);
+
+  X[xd] = read_memory(64, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsuwh.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuwh
+long_name: Load scaled indexed halfword with unsigned word index
+description: |
+  Load 16 bits of data into register `xd` from the effective address
+  `X[xs2] + (zext32(X[xs1]) << 1)`, where `xs2` is the base and `xs1` is the
+  index. The index is zero-extended from `X[xs1][31:0]` before scaling.
+  Sign extend the loaded halfword to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------001-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1][31:0] `<< 1);
+
+  X[xd] = sext(read_memory(16, virtual_address, $encoding), 16);

data/.data/spec/std/isa/inst/Zilx/lxsuwhu.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuwhu
+long_name: Load scaled indexed halfword unsigned with unsigned word index
+description: |
+  Load 16 bits of data into register `xd` from the effective address
+  `X[xs2] + (zext32(X[xs1]) << 1)`, where `xs2` is the base and `xs1` is the
+  index. The index is zero-extended from `X[xs1][31:0]` before scaling.
+  Zero extend the loaded halfword to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------101-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1][31:0] `<< 1);
+
+  X[xd] = read_memory(16, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsuww.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuww
+long_name: Load scaled indexed word with unsigned word index
+description: |
+  Load 32 bits of data into register `xd` from the effective address
+  `X[xs2] + (zext32(X[xs1]) << 2)`, where `xs2` is the base and `xs1` is the
+  index. The index is zero-extended from `X[xs1][31:0]` before scaling.
+  Sign extend the loaded word to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------010-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1][31:0] `<< 2);
+
+  X[xd] = sext(read_memory(32, virtual_address, $encoding), 32);

data/.data/spec/std/isa/inst/Zilx/lxsuwwu.yaml

@@ -0,0 +1,40 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsuwwu
+long_name: Load scaled indexed word unsigned with unsigned word index
+description: |
+  Load 32 bits of data into register `xd` from the effective address
+  `X[xs2] + (zext32(X[xs1]) << 2)`, where `xs2` is the base and `xs1` is the
+  index. The index is zero-extended from `X[xs1][31:0]` before scaling.
+  Zero extend the loaded word to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1111000----------110-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1][31:0] `<< 2);
+
+  X[xd] = read_memory(32, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxsw.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxsw
+long_name: Load scaled indexed word
+description: |
+  Load 32 bits of data into register `xd` from the effective address
+  `X[xs2] + (X[xs1] << 2)`, where `xs2` is the base and `xs1` is the index.
+  On RV64, the loaded word is sign-extended to 64 bits.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------010-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1] `<< 2);
+
+  X[xd] = sext(read_memory(32, virtual_address, $encoding), 32);

data/.data/spec/std/isa/inst/Zilx/lxswu.yaml

@@ -0,0 +1,39 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxswu
+long_name: Load scaled indexed word unsigned
+description: |
+  Load 32 bits of data into register `xd` from the effective address
+  `X[xs2] + (X[xs1] << 2)`, where `xs2` is the base and `xs1` is the index.
+  Zero extend the result to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1101000----------110-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + (X[xs1] `<< 2);
+
+  X[xd] = read_memory(32, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zilx/lxw.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxw
+long_name: Load indexed word
+description: |
+  Load 32 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+  On RV64, the loaded word is sign-extended to 64 bits.
+definedBy:
+  extension:
+    name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1001000----------010-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = sext(read_memory(32, virtual_address, $encoding), 32);

data/.data/spec/std/isa/inst/Zilx/lxwu.yaml

@@ -0,0 +1,39 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: lxwu
+long_name: Load indexed word unsigned
+description: |
+  Load 32 bits of data into register `xd` from the effective address
+  `X[xs2] + X[xs1]`, where `xs2` is the base and `xs1` is the index.
+  Zero extend the result to 64 bits.
+
+  This instruction is defined only for RV64.
+definedBy:
+  allOf:
+    - xlen: 64
+    - extension:
+        name: Zilx
+assembly: xd, (xs2), xs1
+encoding:
+  match: 1001000----------110-----0101111
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg virtual_address = X[xs2] + X[xs1];
+
+  X[xd] = read_memory(32, virtual_address, $encoding);

data/.data/spec/std/isa/inst/Zvabd/vabd.vv.yaml

@@ -0,0 +1,67 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vabd.vv
+long_name: Vector Single-Width Signed Integer Absolute Difference
+description: |
+  Computes the element-wise absolute difference of two signed integer SEW-bit
+  source operands vs1 and vs2 and writes the result to vd according to mask vm.
+
+  Reserved when SEW is neither 8 nor 16.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 010001-----------010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+
+  if (state.sew != 8 && state.sew != 16) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 start_bit_pos = i * state.sew;
+    U32 end_bit_pos = start_bit_pos + state.sew - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if ($signed(V[vs2][end_bit_pos:start_bit_pos]) >= $signed(V[vs1][end_bit_pos:start_bit_pos])) {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] - V[vs1][end_bit_pos:start_bit_pos];
+      } else {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs1][end_bit_pos:start_bit_pos] - V[vs2][end_bit_pos:start_bit_pos];
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvabd/vabdu.vv.yaml

@@ -0,0 +1,67 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vabdu.vv
+long_name: Vector Single-Width Unsigned Integer Absolute Difference
+description: |
+  Computes the element-wise absolute difference of two unsigned integer SEW-bit
+  source operands vs1 and vs2 and writes the result to vd according to mask vm.
+
+  Reserved when SEW is neither 8 nor 16.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 010011-----------010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+
+  if (state.sew != 8 && state.sew != 16) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 start_bit_pos = i * state.sew;
+    U32 end_bit_pos = start_bit_pos + state.sew - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if (V[vs2][end_bit_pos:start_bit_pos] >= V[vs1][end_bit_pos:start_bit_pos]) {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] - V[vs1][end_bit_pos:start_bit_pos];
+      } else {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs1][end_bit_pos:start_bit_pos] - V[vs2][end_bit_pos:start_bit_pos];
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;