udb 0.1.14 → 0.1.15

data/.data/spec/std/isa/inst/Zvabd/vabs.v.yaml

@@ -0,0 +1,61 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vabs.v
+long_name: Vector Single-Width Signed Integer Absolute
+description: |
+  An absolute value operation is performed on each element of vs2, storing the
+  result in vector register vd according to mask vm.
+
+  vabs.v supports SEW of 8, 16, and 32 when Zve32x is implemented.
+  When Zve64x is implemented, vabs.v also supports SEW of 64.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, vm
+encoding:
+  match: 010010------10000010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 start_bit_pos = i * state.sew;
+    U32 end_bit_pos = start_bit_pos + state.sew - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if (V[vs2][end_bit_pos:end_bit_pos] == 1'b1) {
+        V[vd][end_bit_pos:start_bit_pos] = -$signed(V[vs2][end_bit_pos:start_bit_pos]);
+      } else {
+        V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos];
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvabd/vwabda.vv.yaml

@@ -0,0 +1,72 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vwabda.vv
+long_name: Vector Widening Signed Integer Absolute Difference and Accumulate, Overwrite Addend
+description: |
+  Computes the element-wise absolute difference of two signed integer SEW-bit
+  source operands vs1 and vs2, and accumulates the results into the elements of
+  a 2*SEW-bit operand vd.
+
+  Reserved when SEW is neither 8 nor 16.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 010101-----------010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+
+  if (state.sew != 8 && state.sew != 16) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  U32 sew2 = state.sew + state.sew;
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 src_start = i * state.sew;
+    U32 src_end = src_start + state.sew - 1;
+    U32 dst_start = i * sew2;
+    U32 dst_end = dst_start + sew2 - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if ($signed(V[vs2][src_end:src_start]) >= $signed(V[vs1][src_end:src_start])) {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (V[vs2][src_end:src_start] - V[vs1][src_end:src_start]);
+      } else {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (V[vs1][src_end:src_start] - V[vs2][src_end:src_start]);
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zvabd/vwabdau.vv.yaml

@@ -0,0 +1,72 @@
+# Copyright (c) Alibaba Damo Academy
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: vwabdau.vv
+long_name: Vector Widening Unsigned Integer Absolute Difference and Accumulate, Overwrite Addend
+description: |
+  Computes the element-wise absolute difference of two unsigned integer SEW-bit
+  source operands vs1 and vs2, and accumulates the results into the elements of
+  a 2*SEW-bit operand vd.
+
+  Reserved when SEW is neither 8 nor 16.
+definedBy:
+  extension:
+    name: Zvabd
+assembly: vd, vs2, vs1, vm
+encoding:
+  match: 010110-----------010-----1010111
+  variables:
+    - name: vm
+      location: 25
+    - name: vs2
+      location: 24-20
+    - name: vs1
+      location: 19-15
+    - name: vd
+      location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  VectorState state = vector_state();
+
+  if (state.sew != 8 && state.sew != 16) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  }
+
+  VectorLmulType lmul_type = state.lmul_type;
+
+  XReg vlen = VLEN;
+  XReg vlmax;
+  if (lmul_type == VectorLmulType::Multiply) {
+    vlmax = (vlen << state.log2_lmul) >> state.log2_sew;
+  } else {
+    vlmax = (vlen >> state.log2_lmul) >> state.log2_sew;
+  }
+
+  U32 sew2 = state.sew + state.sew;
+
+  for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
+    U32 src_start = i * state.sew;
+    U32 src_end = src_start + state.sew - 1;
+    U32 dst_start = i * sew2;
+    U32 dst_end = dst_start + sew2 - 1;
+    if (vm == 1'b1 || V[0][i:i] == 1'b1) {
+      # active element
+      if (V[vs2][src_end:src_start] >= V[vs1][src_end:src_start]) {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (V[vs2][src_end:src_start] - V[vs1][src_end:src_start]);
+      } else {
+        V[vd][dst_end:dst_start] = V[vd][dst_end:dst_start] + (V[vs1][src_end:src_start] - V[vs2][src_end:src_start]);
+      }
+    }
+    # inactive element: handled according to vtype.VMA policy
+  }
+  # tail elements (i >= vl): handled according to vtype.VTA policy
+
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/isa/fp.idl

@@ -405,6 +405,9 @@ function f32_muladd {
     Translated from Berkeley Softfloat softfloat_mulAddF32.
   }
   body {
+    if (is_sp_signaling_nan?(a) || is_sp_signaling_nan?(b) || is_sp_signaling_nan?(c)) {
+      set_fp_flag(FpFlag::NV);
+    }
     Bits<1>  signA    = signF32UI(a);
     Bits<16>  expA     = expF32UI(a);
     Bits<32> sigA     = fracF32UI(a);
@@ -584,8 +587,11 @@ function f32_sqrt {
     Translated from Berkeley Softfloat f32_sqrt.
   }
   body {
+    if (is_sp_signaling_nan?(a)) {
+      set_fp_flag(FpFlag::NV);
+    }
     Bits<1> signA = signF32UI(a);
-    Bits<8> expA  = expF32UI(a);
+    Bits<16> expA  = expF32UI(a);
     Bits<32> fracA = fracF32UI(a);
 
     if (expA == 8'hFF) {
@@ -606,7 +612,8 @@ function f32_sqrt {
       fracA = norm.sig;
     }
 
-    Bits<16> expZ = ((expA - 16'h007F) >> 1) + 16'h007E;
+    Bits<16> adjExp = expA - 16'h007F;
+    Bits<16> expZ = ((adjExp >> 1) ^ (adjExp & 16'h8000)) + 16'h007E;
     Bits<1> oddExpA = expA[0];
     Bits<32> sigA32 = (fracA | 32'h00800000) << 8;
     Bits<32> sigZ = (sigA32 `* softfloat_approxRecipSqrt32_1(oddExpA, sigA32)) >> 32;
@@ -653,19 +660,22 @@ function softfloat_approxRecip32_1 {
   arguments
     Bits<32> a
   description {
-    Returns a 32-bit approximation of 1/a, where a is in [1, 2).
-    Translated from Berkeley Softfloat softfloat_approxRecip32_1.
+    Returns floor(0x7FFFFFFFFFFFFFFF / a), matching the platform-specific
+    Berkeley SoftFloat macro on 64-bit hosts. Computed via binary long division.
   }
   body {
-    Bits<32> index = (a >> 27) & 0xF;
-    Bits<16> eps = a >> 11;
-    Bits<32> r0 = softfloat_approxRecip_1k0s[index]
-                  - ((softfloat_approxRecip_1k1s[index] `* eps) >> 20);
-    Bits<32> sigma0 = ~((r0 `* a) >> 7);
-    Bits<32> r = (r0 << 16) + ((r0 `* sigma0) >> 24);
-    Bits<32> sqrSigma0 = (sigma0 `* sigma0) >> 32;
-    r = r + ((r `* sqrSigma0) >> 48);
-    return r;
+    Bits<64> a64 = {32'h0, a};
+    Bits<64> a_top = a64 << 31;
+    Bits<64> rem = 64'h7FFFFFFFFFFFFFFF;
+    Bits<32> q = 0;
+    for (U32 i = 0; i < 32; i++) {
+      Bits<64> d = a_top >> i;
+      if (rem >= d) {
+        q = q | (32'h1 << (31 - i));
+        rem = rem - d;
+      }
+    }
+    return q;
   }
 }
 
@@ -710,6 +720,9 @@ function f32_div {
     Translated from Berkeley Softfloat f32_div.
   }
   body {
+    if (is_sp_signaling_nan?(a) || is_sp_signaling_nan?(b)) {
+      set_fp_flag(FpFlag::NV);
+    }
     Bits<1> signA = signF32UI(a);
     Bits<16> expA  = expF32UI(a);
     Bits<32> sigA = fracF32UI(a);
@@ -771,7 +784,7 @@ function f32_div {
     Bits<32> sigZ = (sigA `* recip32) >> 32;
     sigZ = sigZ + 2;
 
-    if ((sigZ & 0x3F) < 2) {
+    if ((sigZ & 7) <= 2) {
       sigZ = sigZ & ~32'h3;
       Bits<64> rem = (sigA `<< 31) - (sigZ `* sigB);
       if ((rem & 64'h8000000000000000) != 0) {
@@ -798,6 +811,9 @@ function f32_mul {
     Translated from Berkeley Softfloat f32_mul.
   }
   body {
+    if (is_sp_signaling_nan?(a) || is_sp_signaling_nan?(b)) {
+      set_fp_flag(FpFlag::NV);
+    }
     Bits<1> signA = signF32UI(a);
     Bits<16> expA  = expF32UI(a);
     Bits<23> fracA = fracF32UI(a);
@@ -1326,6 +1342,9 @@ function softfloat_addMagsF32 {
     Returns sum of the magnitudes of 2 floating point numbers
   }
   body {
+    if (is_sp_signaling_nan?(a) || is_sp_signaling_nan?(b)) {
+      set_fp_flag(FpFlag::NV);
+    }
 
     # extract exponents and significands of a and b
     Bits<16> expA = expF32UI(a);
@@ -1433,6 +1452,9 @@ function softfloat_subMagsF32 {
     Returns difference of the magnitudes of 2 floating point numbers
   }
   body {
+    if (is_sp_signaling_nan?(a) || is_sp_signaling_nan?(b)) {
+      set_fp_flag(FpFlag::NV);
+    }
 
     # extract exponents and significands of a and b
     Bits<16> expA = expF32UI(a);
@@ -1886,7 +1908,7 @@ function round_f32_to_integral {
 }
 
 struct ExpAndSig {
-  Bits<8> exp;
+  Bits<16> exp;
   Bits<32> sig;
 }
 
@@ -1897,11 +1919,13 @@ function softfloat_normSubnormalF32Sig {
   description {
     Normalize a subnormal F32 significand.
     Returns (exp, sig32) where exp is the adjusted exponent (two's complement
-    in Bits<8>) and sig32 is the normalized significand with implicit leading 1
-    at bit 23.
+    in Bits<16>) and sig32 is the normalized significand with implicit leading 1
+    at bit 23. The exponent is widened to Bits<16> (rather than the natural
+    Bits<8>) so that callers can add two adjusted exponents together (e.g.
+    expA + expB - bias) without overflow.
   }
   body {
-    Bits<8> shiftDist = count_leading_zeros(32, sig) - 8;
+    Bits<16> shiftDist = count_leading_zeros(32, sig) - 8;
     ExpAndSig ret;
     ret.exp = 1 - shiftDist;
     ret.sig = sig << shiftDist;

data/.data/spec/std/isa/param/CACHE_BLOCK_SIZE.yaml

@@ -6,14 +6,78 @@
 $schema: param_schema.json#
 kind: parameter
 name: CACHE_BLOCK_SIZE
-description: "The observable size of a cache block, in bytes
-
-  "
-long_name: TODO
+description: The observable size of a cache block, in bytes. A cache block is a
+  naturally aligned power-of-two (NAPOT) range of memory.
+long_name: cache block size
 schema:
   type: integer
-  minimum: 1
-  maximum: 18446744073709551615
+  enum:
+    [
+      0x1,
+      0x2,
+      0x4,
+      0x8,
+      0x10,
+      0x20,
+      0x40,
+      0x80,
+      0x100,
+      0x200,
+      0x400,
+      0x800,
+      0x1000,
+      0x2000,
+      0x4000,
+      0x8000,
+      0x10000,
+      0x20000,
+      0x40000,
+      0x80000,
+      0x100000,
+      0x200000,
+      0x400000,
+      0x800000,
+      0x1000000,
+      0x2000000,
+      0x4000000,
+      0x8000000,
+      0x10000000,
+      0x20000000,
+      0x40000000,
+      0x80000000,
+      0x100000000,
+      0x200000000,
+      0x400000000,
+      0x800000000,
+      0x1000000000,
+      0x2000000000,
+      0x4000000000,
+      0x8000000000,
+      0x10000000000,
+      0x20000000000,
+      0x40000000000,
+      0x80000000000,
+      0x100000000000,
+      0x200000000000,
+      0x400000000000,
+      0x800000000000,
+      0x1000000000000,
+      0x2000000000000,
+      0x4000000000000,
+      0x8000000000000,
+      0x10000000000000,
+      0x20000000000000,
+      0x40000000000000,
+      0x80000000000000,
+      0x100000000000000,
+      0x200000000000000,
+      0x400000000000000,
+      0x800000000000000,
+      0x1000000000000000,
+      0x2000000000000000,
+      0x4000000000000000,
+      0x8000000000000000,
+    ]
 definedBy:
   extension:
     anyOf:

data/.data/spec/std/isa/param/ELEN.yaml

@@ -8,13 +8,35 @@ kind: parameter
 name: ELEN
 description: |
   The maximum size in bits of a vector element that any operation can produce or consume.
-long_name: TODO
+long_name: maximum vector element bit width
 schema:
+  description: |
+    An unsigned power of 2 that is at least 8. The ISA states no maximum; the
+    absolute upper bound is (max VLEN) * (#VRs) = 64Ki * 32 = 2Mi, since an
+    element cannot exceed the total vector register state.
   type: integer
-#    requirements:
-#      idl(): |
-#        -> (ELEN >='h8) && (popcount(ELEN) == 1);
-#      reason: ELEN >= 8, which must be a power of 2.
+  enum:
+    [
+      0x8,
+      0x10,
+      0x20,
+      0x40,
+      0x80,
+      0x100,
+      0x200,
+      0x400,
+      0x800,
+      0x1000,
+      0x2000,
+      0x4000,
+      0x8000,
+      0x10000,
+      0x20000,
+      0x40000,
+      0x80000,
+      0x100000,
+      0x200000,
+    ]
 definedBy:
   extension:
     name: Zvl32b

data/.data/spec/std/isa/param/HCOUNTENABLE_EN.yaml

@@ -25,3 +25,16 @@ schema:
 definedBy:
   extension:
     name: H
+requirements:
+  idl(): |
+    for (U32 i = 0; i < 3; i++) {
+      !implemented?(ExtensionName::Zicntr) -> !HCOUNTENABLE_EN[i];
+    }
+    for (U32 i = 3; i < 32; i++) {
+      !implemented?(ExtensionName::Zihpm) -> !HCOUNTENABLE_EN[i];
+      (!HPM_COUNTER_EN[i]) -> !HCOUNTENABLE_EN[i];
+    }
+  reason: |
+    Counters 0-2 are defined by Zicntr
+    Counters 3..31 are defined by Zihpm
+    When mhpmcounter[i] is not implemented, it cannot be enabled.

data/.data/spec/std/isa/param/HPM_COUNTER_EN.yaml

@@ -7,10 +7,20 @@ $schema: param_schema.json#
 kind: parameter
 name: HPM_COUNTER_EN
 description: |
-  List of HPM counters that are enabled.
-  There is one entry for each hpmcounter.
+  Whether each HPM counter is implemented in hardware.
 
-  The first three entries *must* be false (as they correspond to CY, IR, TM in, _e.g._ `mhmpcountinhibit`)
+  `HPM_COUNTER_EN[n]` being `false` means `hpmcounter<n>`/`mhpmcounter<n>` and the
+  corresponding `mhpmevent<n>` are not implemented and are hardwired read-only zero.
+  (It does *not* mean the counter is implemented but currently stopped from counting;
+  that is a separate, run-time concept controlled by `mcountinhibit`.)
+
+  There is one entry for each hpmcounter, indexed 0-31.
+
+  Indices 0-2 *must* be false: they are placeholders for the three counters
+  (`cycle`/`mcycle` (CY), `time` (TM), and `instret`/`minstret` (IR)) whose
+  implementation this parameter does not control. These counters are associated
+  with indexes 0, 1, and 2. The rest of the HPM counters logically follow at
+  indexes 3-31.
   Index 3 in HPM_COUNTER_EN corresponds to mhpmcounter3.
   Index 31 in HPM_COUNTER_EN corresponds to mhpmcounter31.
 long_name: TODO

data/.data/spec/std/isa/param/HPM_EVENTS.yaml

@@ -28,9 +28,6 @@ definedBy:
           - name: HPM_COUNTER_EN
             index: 4
             equal: true
-          - name: HPM_COUNTER_EN
-            index: 4
-            equal: true
           - name: HPM_COUNTER_EN
             index: 5
             equal: true

data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml

@@ -27,6 +27,14 @@ definedBy:
     name: Sm
 requirements:
   idl(): |
+    for (U32 i = 0; i < 3; i++) {
+      !implemented?(ExtensionName::Zicntr) -> !MCOUNTENABLE_EN[i];
+    }
     for (U32 i=3; i < 32; i++) {
+      !implemented?(ExtensionName::Zihpm) -> !MCOUNTENABLE_EN[i];
       MCOUNTENABLE_EN[i] -> HPM_COUNTER_EN[i];
     }
+  reason: |
+    Counters 0-2 are defined by Zicntr
+    Counters 3..31 are defined by Zihpm
+    When mhpmcounter[i] is not implemented, it cannot be enabled.

data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml

@@ -25,73 +25,79 @@ description: |
   the base, the minimum alignment cannot be less than 4.
 schema:
   description: An unsigned power of 2 greater than or equal to 4 that fits in 64 bits
-  default: 4
+  default: 0x4
   enum:
     [
-      4,
-      8,
-      16,
-      32,
-      64,
-      128,
-      256,
-      512,
-      1024,
-      2048,
-      4095,
-      8192,
-      16384,
-      32768,
-      65536,
-      131072,
-      262144,
-      524288,
-      1048576,
-      2097152,
-      4194304,
-      8388608,
-      16777216,
-      33554432,
-      67108864,
-      134217728,
-      268435456,
-      536870912,
-      1073741824,
-      2147483648,
-      4294967296,
-      8589934592,
-      17179869184,
-      34359738368,
-      68719476736,
-      137438953472,
-      274877906944,
-      549755813888,
-      1099511627776,
-      2199023255552,
-      4398046511104,
-      8796093022208,
-      17592186044416,
-      35184372088832,
-      70368744177664,
-      140737488355328,
-      281474976710656,
-      562949953421312,
-      1125899906842624,
-      2251799813685248,
-      4503599627370496,
-      9007199254740992,
-      18014398509481984,
-      36028797018963968,
-      72057594037927936,
-      144115188075855872,
-      288230376151711744,
-      576460752303423488,
-      1152921504606846976,
-      2305843009213693952,
-      4611686018427387904,
-      9223372036854775808,
+      0x4,
+      0x8,
+      0x10,
+      0x20,
+      0x40,
+      0x80,
+      0x100,
+      0x200,
+      0x400,
+      0x800,
+      0x1000,
+      0x2000,
+      0x4000,
+      0x8000,
+      0x10000,
+      0x20000,
+      0x40000,
+      0x80000,
+      0x100000,
+      0x200000,
+      0x400000,
+      0x800000,
+      0x1000000,
+      0x2000000,
+      0x4000000,
+      0x8000000,
+      0x10000000,
+      0x20000000,
+      0x40000000,
+      0x80000000,
+      0x100000000,
+      0x200000000,
+      0x400000000,
+      0x800000000,
+      0x1000000000,
+      0x2000000000,
+      0x4000000000,
+      0x8000000000,
+      0x10000000000,
+      0x20000000000,
+      0x40000000000,
+      0x80000000000,
+      0x100000000000,
+      0x200000000000,
+      0x400000000000,
+      0x800000000000,
+      0x1000000000000,
+      0x2000000000000,
+      0x4000000000000,
+      0x8000000000000,
+      0x10000000000000,
+      0x20000000000000,
+      0x40000000000000,
+      0x80000000000000,
+      0x100000000000000,
+      0x200000000000000,
+      0x400000000000000,
+      0x800000000000000,
+      0x1000000000000000,
+      0x2000000000000000,
+      0x4000000000000000,
+      0x8000000000000000,
     ]
 
 requirements:
-  idl(): |
-    (MXLEN == 32) -> MTVEC_BASE_ALIGNMENT_DIRECT <= 2147483648;
+  if:
+    param:
+      name: MXLEN
+      equal: 32
+  then:
+    param:
+      name: MTVEC_BASE_ALIGNMENT_DIRECT
+      lessThanOrEqual: 0x80000000