udb 0.1.13 → 0.1.14

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Files changed (189) hide show
  1. checksums.yaml +4 -4
  2. data/.data/cfgs/example_rv64_with_overlay.yaml +15 -18
  3. data/.data/cfgs/qc_iu.yaml +5 -1
  4. data/.data/cfgs/rv32-riscv-tests.yaml +4 -1
  5. data/.data/cfgs/rv32-vector.yaml +4 -1
  6. data/.data/cfgs/rv64-riscv-tests.yaml +4 -1
  7. data/.data/cfgs/rv64-vector.yaml +4 -1
  8. data/.data/spec/custom/isa/qc_iu/ext/Xqccmi.yaml +107 -36
  9. data/.data/spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml +52 -69
  10. data/.data/spec/custom/isa/qc_iu/isa/globals.isa +27 -5
  11. data/.data/spec/schemas/config_schema.json +1 -1
  12. data/.data/spec/schemas/mmr_schema.json +3 -3
  13. data/.data/spec/schemas/schema_defs.json +5 -0
  14. data/.data/spec/std/isa/csr/H/henvcfg.yaml +25 -0
  15. data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +6 -4
  16. data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +6 -4
  17. data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +6 -4
  18. data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +6 -4
  19. data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +6 -4
  20. data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +6 -4
  21. data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +6 -4
  22. data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +6 -4
  23. data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +6 -4
  24. data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +6 -4
  25. data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +6 -4
  26. data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +6 -4
  27. data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +6 -4
  28. data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +6 -4
  29. data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +6 -4
  30. data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +6 -4
  31. data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +6 -4
  32. data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +6 -4
  33. data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +6 -4
  34. data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +6 -4
  35. data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +6 -4
  36. data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +6 -4
  37. data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +6 -4
  38. data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +6 -4
  39. data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +6 -4
  40. data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +6 -4
  41. data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +6 -4
  42. data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +6 -4
  43. data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +6 -4
  44. data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +6 -4
  45. data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +6 -4
  46. data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +6 -4
  47. data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +6 -4
  48. data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +6 -4
  49. data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +6 -4
  50. data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +6 -4
  51. data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +6 -4
  52. data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +6 -4
  53. data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +6 -4
  54. data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +6 -4
  55. data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +6 -4
  56. data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +6 -4
  57. data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +6 -4
  58. data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +6 -4
  59. data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +6 -4
  60. data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +6 -4
  61. data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +6 -4
  62. data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +6 -4
  63. data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +6 -4
  64. data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +6 -4
  65. data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +6 -4
  66. data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +6 -4
  67. data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +6 -4
  68. data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +6 -4
  69. data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +6 -4
  70. data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +6 -4
  71. data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +6 -4
  72. data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +6 -4
  73. data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +6 -4
  74. data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +6 -4
  75. data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +6 -4
  76. data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +6 -4
  77. data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +6 -4
  78. data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +6 -4
  79. data/.data/spec/std/isa/csr/I/pmpaddrN.layout +6 -4
  80. data/.data/spec/std/isa/csr/I/pmpcfg0.yaml +120 -144
  81. data/.data/spec/std/isa/csr/I/pmpcfg1.yaml +60 -72
  82. data/.data/spec/std/isa/csr/I/pmpcfg10.yaml +120 -144
  83. data/.data/spec/std/isa/csr/I/pmpcfg11.yaml +60 -72
  84. data/.data/spec/std/isa/csr/I/pmpcfg12.yaml +120 -144
  85. data/.data/spec/std/isa/csr/I/pmpcfg13.yaml +60 -72
  86. data/.data/spec/std/isa/csr/I/pmpcfg14.yaml +120 -144
  87. data/.data/spec/std/isa/csr/I/pmpcfg15.yaml +60 -72
  88. data/.data/spec/std/isa/csr/I/pmpcfg2.yaml +120 -144
  89. data/.data/spec/std/isa/csr/I/pmpcfg3.yaml +60 -72
  90. data/.data/spec/std/isa/csr/I/pmpcfg4.yaml +120 -144
  91. data/.data/spec/std/isa/csr/I/pmpcfg5.yaml +60 -72
  92. data/.data/spec/std/isa/csr/I/pmpcfg6.yaml +120 -144
  93. data/.data/spec/std/isa/csr/I/pmpcfg7.yaml +60 -72
  94. data/.data/spec/std/isa/csr/I/pmpcfg8.yaml +120 -144
  95. data/.data/spec/std/isa/csr/I/pmpcfg9.yaml +60 -72
  96. data/.data/spec/std/isa/csr/I/pmpcfgN.layout +15 -18
  97. data/.data/spec/std/isa/csr/jvt.yaml +1 -0
  98. data/.data/spec/std/isa/csr/menvcfg.yaml +20 -0
  99. data/.data/spec/std/isa/csr/mstatus.yaml +8 -6
  100. data/.data/spec/std/isa/csr/senvcfg.yaml +26 -0
  101. data/.data/spec/std/isa/inst/B/andn.yaml +10 -12
  102. data/.data/spec/std/isa/inst/B/clmul.yaml +9 -11
  103. data/.data/spec/std/isa/inst/B/clmulh.yaml +9 -11
  104. data/.data/spec/std/isa/inst/B/orn.yaml +9 -11
  105. data/.data/spec/std/isa/inst/B/rev8.yaml +1 -1
  106. data/.data/spec/std/isa/inst/B/rol.yaml +9 -11
  107. data/.data/spec/std/isa/inst/B/rolw.yaml +9 -11
  108. data/.data/spec/std/isa/inst/B/ror.yaml +9 -11
  109. data/.data/spec/std/isa/inst/B/rorw.yaml +9 -11
  110. data/.data/spec/std/isa/inst/B/xnor.yaml +9 -11
  111. data/.data/spec/std/isa/inst/C/c.ldsp.yaml +3 -3
  112. data/.data/spec/std/isa/inst/I/addi.yaml +1 -0
  113. data/.data/spec/std/isa/inst/I/addiw.yaml +1 -0
  114. data/.data/spec/std/isa/inst/I/andi.yaml +1 -0
  115. data/.data/spec/std/isa/inst/I/auipc.yaml +1 -0
  116. data/.data/spec/std/isa/inst/I/lb.yaml +1 -0
  117. data/.data/spec/std/isa/inst/I/lbu.yaml +1 -0
  118. data/.data/spec/std/isa/inst/I/ld.yaml +2 -0
  119. data/.data/spec/std/isa/inst/I/lh.yaml +1 -0
  120. data/.data/spec/std/isa/inst/I/lhu.yaml +1 -0
  121. data/.data/spec/std/isa/inst/I/lui.yaml +1 -0
  122. data/.data/spec/std/isa/inst/I/lw.yaml +1 -0
  123. data/.data/spec/std/isa/inst/I/lwu.yaml +1 -0
  124. data/.data/spec/std/isa/inst/I/ori.yaml +1 -0
  125. data/.data/spec/std/isa/inst/I/sb.yaml +1 -0
  126. data/.data/spec/std/isa/inst/I/sd.yaml +1 -0
  127. data/.data/spec/std/isa/inst/I/sh.yaml +1 -0
  128. data/.data/spec/std/isa/inst/I/slti.yaml +1 -0
  129. data/.data/spec/std/isa/inst/I/sltiu.yaml +1 -0
  130. data/.data/spec/std/isa/inst/I/sw.yaml +1 -0
  131. data/.data/spec/std/isa/inst/I/xori.yaml +1 -0
  132. data/.data/spec/std/isa/inst/V/vadc.vim.yaml +1 -0
  133. data/.data/spec/std/isa/inst/V/vadd.vi.yaml +1 -0
  134. data/.data/spec/std/isa/inst/V/vand.vi.yaml +1 -0
  135. data/.data/spec/std/isa/inst/V/vle8.v.yaml +1 -0
  136. data/.data/spec/std/isa/inst/V/vmadc.vi.yaml +1 -0
  137. data/.data/spec/std/isa/inst/V/vmadc.vim.yaml +1 -0
  138. data/.data/spec/std/isa/inst/V/vmerge.vim.yaml +1 -0
  139. data/.data/spec/std/isa/inst/V/vmseq.vi.yaml +1 -0
  140. data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml +1 -0
  141. data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml +1 -0
  142. data/.data/spec/std/isa/inst/V/vmsle.vi.yaml +1 -0
  143. data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml +1 -0
  144. data/.data/spec/std/isa/inst/V/vmsne.vi.yaml +1 -0
  145. data/.data/spec/std/isa/inst/V/vor.vi.yaml +1 -0
  146. data/.data/spec/std/isa/inst/V/vrsub.vi.yaml +1 -0
  147. data/.data/spec/std/isa/inst/V/vsadd.vi.yaml +1 -0
  148. data/.data/spec/std/isa/inst/V/vsaddu.vi.yaml +1 -0
  149. data/.data/spec/std/isa/inst/V/vse8.v.yaml +1 -0
  150. data/.data/spec/std/isa/inst/Zawrs/wrs.nto.yaml +4 -2
  151. data/.data/spec/std/isa/inst/Zba/add.uw.yaml +9 -11
  152. data/.data/spec/std/isa/inst/Zbb/orc.b.yaml +1 -1
  153. data/.data/spec/std/isa/inst/Zbkb/brev8.yaml +3 -3
  154. data/.data/spec/std/isa/inst/Zbkb/unzip.yaml +2 -2
  155. data/.data/spec/std/isa/inst/Zbkb/zip.yaml +2 -2
  156. data/.data/spec/std/isa/inst/Zbkx/xperm4.yaml +2 -2
  157. data/.data/spec/std/isa/inst/Zbkx/xperm8.yaml +2 -2
  158. data/.data/spec/std/isa/inst/Zicbop/prefetch.i.yaml +2 -0
  159. data/.data/spec/std/isa/inst/Zicbop/prefetch.r.yaml +2 -0
  160. data/.data/spec/std/isa/inst/Zicbop/prefetch.w.yaml +2 -0
  161. data/.data/spec/std/isa/inst/Zks/sm3p0.yaml +1 -1
  162. data/.data/spec/std/isa/inst/Zks/sm3p1.yaml +1 -1
  163. data/.data/spec/std/isa/inst/Zks/sm4ed.yaml +1 -1
  164. data/.data/spec/std/isa/inst/Zks/sm4ks.yaml +1 -1
  165. data/.data/spec/std/isa/isa/builtin_functions.idl +1 -0
  166. data/.data/spec/std/isa/isa/globals.isa +27 -7
  167. data/.data/spec/std/isa/isa/interrupts.idl +1 -0
  168. data/.data/spec/std/isa/param/HSTATEEN_CONTEXT_TYPE.yaml +1 -0
  169. data/.data/spec/std/isa/param/MSTATEEN_CONTEXT_TYPE.yaml +1 -0
  170. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml +1 -0
  171. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml +1 -0
  172. data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +11 -22
  173. data/.data/spec/std/isa/param/NUM_USABLE_PMP_ENTRIES.yaml +35 -0
  174. data/.data/spec/std/isa/param/PMP_NA4_SUPPORTED.yaml +23 -0
  175. data/.data/spec/std/isa/param/PMP_NAPOT_SUPPORTED.yaml +19 -0
  176. data/.data/spec/std/isa/param/{MSTATUS_TVM_IMPLEMENTED.yaml → PMP_TOR_SUPPORTED.yaml} +6 -6
  177. data/.data/spec/std/isa/param/PRECISE_SYNCHRONOUS_EXCEPTIONS.yaml +1 -0
  178. data/.data/spec/std/isa/param/TRAP_ON_EBREAK.yaml +1 -0
  179. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_M.yaml +1 -0
  180. data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -0
  181. data/.data/spec/std/isa/param/ZAWRS_NTO_IS_NOP.yaml +19 -0
  182. data/lib/udb/ESPRESSO_VERSION +1 -1
  183. data/lib/udb/config.rb +14 -2
  184. data/lib/udb/doc_link.rb +3 -4
  185. data/lib/udb/obj/instruction.rb +1 -1
  186. data/lib/udb/obj/non_isa_specification.rb +22 -100
  187. data/lib/udb/version.rb +1 -1
  188. data/lib/udb/z3.rb +2 -2
  189. metadata +7 -3
@@ -37,21 +37,13 @@ fields:
37
37
  h! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
38
38
  h! MT ! 6:5 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
39
39
  h! A ! 4:3
40
- a! Address matching mode. One of:
40
+ a! Address matching mode. Encodings:
41
41
 
42
- [when="PMP_GRANULARITY < 2"]
43
42
  * *OFF* (0) - Null region (disabled)
44
43
  * *TOR* (1) - Top of range
45
44
  * *NA4* (2) - Naturally aligned four-byte region
46
45
  * *NAPOT* (3) - Naturally aligned power of two
47
46
 
48
- [when="PMP_GRANULARITY >= 2"]
49
- * *OFF* (0) - Null region (disabled)
50
- * *TOR* (1) - Top of range
51
- * *NAPOT* (3) - Naturally aligned power of two
52
-
53
- [when="PMP_GRANULARITY >= 2"]
54
- Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
55
47
 
56
48
  h! X ! 2 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
57
49
  h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -60,23 +52,28 @@ fields:
60
52
 
61
53
  The combination of R = 0, W = 1 is reserved.
62
54
  type(): |
63
- if (NUM_PMP_ENTRIES > 40) {
55
+ if (NUM_USABLE_PMP_ENTRIES > 40) {
64
56
  return CsrFieldType::RWR;
65
57
  } else {
58
+ # entry is either not implemented or implemented as read-only zero
66
59
  return CsrFieldType::RO;
67
60
  }
68
61
  reset_value(): |
69
62
  return 0;
70
63
  sw_write(csr_value): |
71
- if ((CSR[pmpcfg10].pmp40cfg & 0x80) == 0) {
72
- # entry is not locked
73
- if (!(((csr_value.pmp40cfg & 0x1) == 0) && ((csr_value.pmp40cfg & 0x2) == 0x2))) {
74
- # not R = 0, W =1, which is reserved
75
- if ((PMP_GRANULARITY < 2) ||
76
- ((csr_value.pmp40cfg & 0x18) != 0x10)) {
77
- # NA4 is not allowed when PMP granularity is larger than 4 bytes
78
- return csr_value.pmp40cfg;
64
+ if (NUM_USABLE_PMP_ENTRIES > 40 && (CSR[pmpcfg10].pmp40cfg & 0x80) == 0) {
65
+ # entry is usable and not locked
66
+ Bits<8> new_cfg = csr_value.pmp40cfg;
67
+ Bits<2> a_mode = (new_cfg & 0x18) >> 3;
68
+ if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
69
+ # not R = 0, W = 1, which is reserved
70
+ if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
71
+ ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
72
+ ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
73
+ # unsupported address matching mode; keep old value
74
+ return CSR[pmpcfg10].pmp40cfg;
79
75
  }
76
+ return new_cfg;
80
77
  }
81
78
  }
82
79
  # fall through: keep old value
@@ -95,21 +92,13 @@ fields:
95
92
  h! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
96
93
  h! MT ! 14:13 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
97
94
  h! A ! 12:11
98
- a! Address matching mode. One of:
95
+ a! Address matching mode. Encodings:
99
96
 
100
- [when="PMP_GRANULARITY < 2"]
101
97
  * *OFF* (0) - Null region (disabled)
102
98
  * *TOR* (1) - Top of range
103
99
  * *NA4* (2) - Naturally aligned four-byte region
104
100
  * *NAPOT* (3) - Naturally aligned power of two
105
101
 
106
- [when="PMP_GRANULARITY >= 2"]
107
- * *OFF* (0) - Null region (disabled)
108
- * *TOR* (1) - Top of range
109
- * *NAPOT* (3) - Naturally aligned power of two
110
-
111
- [when="PMP_GRANULARITY >= 2"]
112
- Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
113
102
 
114
103
  h! X ! 10 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
115
104
  h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -118,23 +107,28 @@ fields:
118
107
 
119
108
  The combination of R = 0, W = 1 is reserved.
120
109
  type(): |
121
- if (NUM_PMP_ENTRIES > 41) {
110
+ if (NUM_USABLE_PMP_ENTRIES > 41) {
122
111
  return CsrFieldType::RWR;
123
112
  } else {
113
+ # entry is either not implemented or implemented as read-only zero
124
114
  return CsrFieldType::RO;
125
115
  }
126
116
  reset_value(): |
127
117
  return 0;
128
118
  sw_write(csr_value): |
129
- if ((CSR[pmpcfg10].pmp41cfg & 0x80) == 0) {
130
- # entry is not locked
131
- if (!(((csr_value.pmp41cfg & 0x1) == 0) && ((csr_value.pmp41cfg & 0x2) == 0x2))) {
132
- # not R = 0, W =1, which is reserved
133
- if ((PMP_GRANULARITY < 2) ||
134
- ((csr_value.pmp41cfg & 0x18) != 0x10)) {
135
- # NA4 is not allowed when PMP granularity is larger than 4 bytes
136
- return csr_value.pmp41cfg;
119
+ if (NUM_USABLE_PMP_ENTRIES > 41 && (CSR[pmpcfg10].pmp41cfg & 0x80) == 0) {
120
+ # entry is usable and not locked
121
+ Bits<8> new_cfg = csr_value.pmp41cfg;
122
+ Bits<2> a_mode = (new_cfg & 0x18) >> 3;
123
+ if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
124
+ # not R = 0, W = 1, which is reserved
125
+ if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
126
+ ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
127
+ ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
128
+ # unsupported address matching mode; keep old value
129
+ return CSR[pmpcfg10].pmp41cfg;
137
130
  }
131
+ return new_cfg;
138
132
  }
139
133
  }
140
134
  # fall through: keep old value
@@ -153,21 +147,13 @@ fields:
153
147
  h! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
154
148
  h! MT ! 22:21 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
155
149
  h! A ! 20:19
156
- a! Address matching mode. One of:
150
+ a! Address matching mode. Encodings:
157
151
 
158
- [when="PMP_GRANULARITY < 2"]
159
152
  * *OFF* (0) - Null region (disabled)
160
153
  * *TOR* (1) - Top of range
161
154
  * *NA4* (2) - Naturally aligned four-byte region
162
155
  * *NAPOT* (3) - Naturally aligned power of two
163
156
 
164
- [when="PMP_GRANULARITY >= 2"]
165
- * *OFF* (0) - Null region (disabled)
166
- * *TOR* (1) - Top of range
167
- * *NAPOT* (3) - Naturally aligned power of two
168
-
169
- [when="PMP_GRANULARITY >= 2"]
170
- Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
171
157
 
172
158
  h! X ! 18 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
173
159
  h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -176,23 +162,28 @@ fields:
176
162
 
177
163
  The combination of R = 0, W = 1 is reserved.
178
164
  type(): |
179
- if (NUM_PMP_ENTRIES > 42) {
165
+ if (NUM_USABLE_PMP_ENTRIES > 42) {
180
166
  return CsrFieldType::RWR;
181
167
  } else {
168
+ # entry is either not implemented or implemented as read-only zero
182
169
  return CsrFieldType::RO;
183
170
  }
184
171
  reset_value(): |
185
172
  return 0;
186
173
  sw_write(csr_value): |
187
- if ((CSR[pmpcfg10].pmp42cfg & 0x80) == 0) {
188
- # entry is not locked
189
- if (!(((csr_value.pmp42cfg & 0x1) == 0) && ((csr_value.pmp42cfg & 0x2) == 0x2))) {
190
- # not R = 0, W =1, which is reserved
191
- if ((PMP_GRANULARITY < 2) ||
192
- ((csr_value.pmp42cfg & 0x18) != 0x10)) {
193
- # NA4 is not allowed when PMP granularity is larger than 4 bytes
194
- return csr_value.pmp42cfg;
174
+ if (NUM_USABLE_PMP_ENTRIES > 42 && (CSR[pmpcfg10].pmp42cfg & 0x80) == 0) {
175
+ # entry is usable and not locked
176
+ Bits<8> new_cfg = csr_value.pmp42cfg;
177
+ Bits<2> a_mode = (new_cfg & 0x18) >> 3;
178
+ if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
179
+ # not R = 0, W = 1, which is reserved
180
+ if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
181
+ ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
182
+ ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
183
+ # unsupported address matching mode; keep old value
184
+ return CSR[pmpcfg10].pmp42cfg;
195
185
  }
186
+ return new_cfg;
196
187
  }
197
188
  }
198
189
  # fall through: keep old value
@@ -211,21 +202,13 @@ fields:
211
202
  h! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
212
203
  h! MT ! 30:29 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
213
204
  h! A ! 28:27
214
- a! Address matching mode. One of:
205
+ a! Address matching mode. Encodings:
215
206
 
216
- [when="PMP_GRANULARITY < 2"]
217
207
  * *OFF* (0) - Null region (disabled)
218
208
  * *TOR* (1) - Top of range
219
209
  * *NA4* (2) - Naturally aligned four-byte region
220
210
  * *NAPOT* (3) - Naturally aligned power of two
221
211
 
222
- [when="PMP_GRANULARITY >= 2"]
223
- * *OFF* (0) - Null region (disabled)
224
- * *TOR* (1) - Top of range
225
- * *NAPOT* (3) - Naturally aligned power of two
226
-
227
- [when="PMP_GRANULARITY >= 2"]
228
- Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
229
212
 
230
213
  h! X ! 26 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
231
214
  h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -234,23 +217,28 @@ fields:
234
217
 
235
218
  The combination of R = 0, W = 1 is reserved.
236
219
  type(): |
237
- if (NUM_PMP_ENTRIES > 43) {
220
+ if (NUM_USABLE_PMP_ENTRIES > 43) {
238
221
  return CsrFieldType::RWR;
239
222
  } else {
223
+ # entry is either not implemented or implemented as read-only zero
240
224
  return CsrFieldType::RO;
241
225
  }
242
226
  reset_value(): |
243
227
  return 0;
244
228
  sw_write(csr_value): |
245
- if ((CSR[pmpcfg10].pmp43cfg & 0x80) == 0) {
246
- # entry is not locked
247
- if (!(((csr_value.pmp43cfg & 0x1) == 0) && ((csr_value.pmp43cfg & 0x2) == 0x2))) {
248
- # not R = 0, W =1, which is reserved
249
- if ((PMP_GRANULARITY < 2) ||
250
- ((csr_value.pmp43cfg & 0x18) != 0x10)) {
251
- # NA4 is not allowed when PMP granularity is larger than 4 bytes
252
- return csr_value.pmp43cfg;
229
+ if (NUM_USABLE_PMP_ENTRIES > 43 && (CSR[pmpcfg10].pmp43cfg & 0x80) == 0) {
230
+ # entry is usable and not locked
231
+ Bits<8> new_cfg = csr_value.pmp43cfg;
232
+ Bits<2> a_mode = (new_cfg & 0x18) >> 3;
233
+ if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
234
+ # not R = 0, W = 1, which is reserved
235
+ if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
236
+ ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
237
+ ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
238
+ # unsupported address matching mode; keep old value
239
+ return CSR[pmpcfg10].pmp43cfg;
253
240
  }
241
+ return new_cfg;
254
242
  }
255
243
  }
256
244
  # fall through: keep old value
@@ -271,21 +259,13 @@ fields:
271
259
  h! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
272
260
  h! MT ! 38:37 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
273
261
  h! A ! 36:35
274
- a! Address matching mode. One of:
262
+ a! Address matching mode. Encodings:
275
263
 
276
- [when="PMP_GRANULARITY < 2"]
277
264
  * *OFF* (0) - Null region (disabled)
278
265
  * *TOR* (1) - Top of range
279
266
  * *NA4* (2) - Naturally aligned four-byte region
280
267
  * *NAPOT* (3) - Naturally aligned power of two
281
268
 
282
- [when="PMP_GRANULARITY >= 2"]
283
- * *OFF* (0) - Null region (disabled)
284
- * *TOR* (1) - Top of range
285
- * *NAPOT* (3) - Naturally aligned power of two
286
-
287
- [when="PMP_GRANULARITY >= 2"]
288
- Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
289
269
 
290
270
  h! X ! 34 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
291
271
  h! W ! 33 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -294,23 +274,28 @@ fields:
294
274
 
295
275
  The combination of R = 0, W = 1 is reserved.
296
276
  type(): |
297
- if (NUM_PMP_ENTRIES > 44) {
277
+ if (NUM_USABLE_PMP_ENTRIES > 44) {
298
278
  return CsrFieldType::RWR;
299
279
  } else {
280
+ # entry is either not implemented or implemented as read-only zero
300
281
  return CsrFieldType::RO;
301
282
  }
302
283
  reset_value(): |
303
284
  return 0;
304
285
  sw_write(csr_value): |
305
- if ((CSR[pmpcfg10].pmp44cfg & 0x80) == 0) {
306
- # entry is not locked
307
- if (!(((csr_value.pmp44cfg & 0x1) == 0) && ((csr_value.pmp44cfg & 0x2) == 0x2))) {
308
- # not R = 0, W =1, which is reserved
309
- if ((PMP_GRANULARITY < 2) ||
310
- ((csr_value.pmp44cfg & 0x18) != 0x10)) {
311
- # NA4 is not allowed when PMP granularity is larger than 4 bytes
312
- return csr_value.pmp44cfg;
286
+ if (NUM_USABLE_PMP_ENTRIES > 44 && (CSR[pmpcfg10].pmp44cfg & 0x80) == 0) {
287
+ # entry is usable and not locked
288
+ Bits<8> new_cfg = csr_value.pmp44cfg;
289
+ Bits<2> a_mode = (new_cfg & 0x18) >> 3;
290
+ if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
291
+ # not R = 0, W = 1, which is reserved
292
+ if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
293
+ ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
294
+ ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
295
+ # unsupported address matching mode; keep old value
296
+ return CSR[pmpcfg10].pmp44cfg;
313
297
  }
298
+ return new_cfg;
314
299
  }
315
300
  }
316
301
  # fall through: keep old value
@@ -331,21 +316,13 @@ fields:
331
316
  h! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
332
317
  h! MT ! 46:45 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
333
318
  h! A ! 44:43
334
- a! Address matching mode. One of:
319
+ a! Address matching mode. Encodings:
335
320
 
336
- [when="PMP_GRANULARITY < 2"]
337
321
  * *OFF* (0) - Null region (disabled)
338
322
  * *TOR* (1) - Top of range
339
323
  * *NA4* (2) - Naturally aligned four-byte region
340
324
  * *NAPOT* (3) - Naturally aligned power of two
341
325
 
342
- [when="PMP_GRANULARITY >= 2"]
343
- * *OFF* (0) - Null region (disabled)
344
- * *TOR* (1) - Top of range
345
- * *NAPOT* (3) - Naturally aligned power of two
346
-
347
- [when="PMP_GRANULARITY >= 2"]
348
- Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
349
326
 
350
327
  h! X ! 42 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
351
328
  h! W ! 41 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -354,23 +331,28 @@ fields:
354
331
 
355
332
  The combination of R = 0, W = 1 is reserved.
356
333
  type(): |
357
- if (NUM_PMP_ENTRIES > 45) {
334
+ if (NUM_USABLE_PMP_ENTRIES > 45) {
358
335
  return CsrFieldType::RWR;
359
336
  } else {
337
+ # entry is either not implemented or implemented as read-only zero
360
338
  return CsrFieldType::RO;
361
339
  }
362
340
  reset_value(): |
363
341
  return 0;
364
342
  sw_write(csr_value): |
365
- if ((xlen() == 64) && (CSR[pmpcfg10].pmp45cfg & 0x80) == 0) {
366
- # entry is not locked
367
- if (!(((csr_value.pmp45cfg & 0x1) == 0) && ((csr_value.pmp45cfg & 0x2) == 0x2))) {
368
- # not R = 0, W =1, which is reserved
369
- if ((PMP_GRANULARITY < 2) ||
370
- ((csr_value.pmp45cfg & 0x18) != 0x10)) {
371
- # NA4 is not allowed when PMP granularity is larger than 4 bytes
372
- return csr_value.pmp45cfg;
343
+ if ((xlen() == 64) && NUM_USABLE_PMP_ENTRIES > 45 && (CSR[pmpcfg10].pmp45cfg & 0x80) == 0) {
344
+ # entry is usable and not locked
345
+ Bits<8> new_cfg = csr_value.pmp45cfg;
346
+ Bits<2> a_mode = (new_cfg & 0x18) >> 3;
347
+ if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
348
+ # not R = 0, W = 1, which is reserved
349
+ if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
350
+ ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
351
+ ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
352
+ # unsupported address matching mode; keep old value
353
+ return CSR[pmpcfg10].pmp45cfg;
373
354
  }
355
+ return new_cfg;
374
356
  }
375
357
  }
376
358
  # fall through: keep old value
@@ -391,21 +373,13 @@ fields:
391
373
  h! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
392
374
  h! MT ! 54:53 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
393
375
  h! A ! 52:51
394
- a! Address matching mode. One of:
376
+ a! Address matching mode. Encodings:
395
377
 
396
- [when="PMP_GRANULARITY < 2"]
397
378
  * *OFF* (0) - Null region (disabled)
398
379
  * *TOR* (1) - Top of range
399
380
  * *NA4* (2) - Naturally aligned four-byte region
400
381
  * *NAPOT* (3) - Naturally aligned power of two
401
382
 
402
- [when="PMP_GRANULARITY >= 2"]
403
- * *OFF* (0) - Null region (disabled)
404
- * *TOR* (1) - Top of range
405
- * *NAPOT* (3) - Naturally aligned power of two
406
-
407
- [when="PMP_GRANULARITY >= 2"]
408
- Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
409
383
 
410
384
  h! X ! 50 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
411
385
  h! W ! 49 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -414,23 +388,28 @@ fields:
414
388
 
415
389
  The combination of R = 0, W = 1 is reserved.
416
390
  type(): |
417
- if (NUM_PMP_ENTRIES > 46) {
391
+ if (NUM_USABLE_PMP_ENTRIES > 46) {
418
392
  return CsrFieldType::RWR;
419
393
  } else {
394
+ # entry is either not implemented or implemented as read-only zero
420
395
  return CsrFieldType::RO;
421
396
  }
422
397
  reset_value(): |
423
398
  return 0;
424
399
  sw_write(csr_value): |
425
- if ((xlen() == 64) && (CSR[pmpcfg10].pmp46cfg & 0x80) == 0) {
426
- # entry is not locked
427
- if (!(((csr_value.pmp46cfg & 0x1) == 0) && ((csr_value.pmp46cfg & 0x2) == 0x2))) {
428
- # not R = 0, W =1, which is reserved
429
- if ((PMP_GRANULARITY < 2) ||
430
- ((csr_value.pmp46cfg & 0x18) != 0x10)) {
431
- # NA4 is not allowed when PMP granularity is larger than 4 bytes
432
- return csr_value.pmp46cfg;
400
+ if ((xlen() == 64) && NUM_USABLE_PMP_ENTRIES > 46 && (CSR[pmpcfg10].pmp46cfg & 0x80) == 0) {
401
+ # entry is usable and not locked
402
+ Bits<8> new_cfg = csr_value.pmp46cfg;
403
+ Bits<2> a_mode = (new_cfg & 0x18) >> 3;
404
+ if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
405
+ # not R = 0, W = 1, which is reserved
406
+ if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
407
+ ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
408
+ ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
409
+ # unsupported address matching mode; keep old value
410
+ return CSR[pmpcfg10].pmp46cfg;
433
411
  }
412
+ return new_cfg;
434
413
  }
435
414
  }
436
415
  # fall through: keep old value
@@ -451,21 +430,13 @@ fields:
451
430
  h! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
452
431
  h! MT ! 62:61 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry. See the `Smpmpmt` extension definition for encodings. When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
453
432
  h! A ! 60:59
454
- a! Address matching mode. One of:
433
+ a! Address matching mode. Encodings:
455
434
 
456
- [when="PMP_GRANULARITY < 2"]
457
435
  * *OFF* (0) - Null region (disabled)
458
436
  * *TOR* (1) - Top of range
459
437
  * *NA4* (2) - Naturally aligned four-byte region
460
438
  * *NAPOT* (3) - Naturally aligned power of two
461
439
 
462
- [when="PMP_GRANULARITY >= 2"]
463
- * *OFF* (0) - Null region (disabled)
464
- * *TOR* (1) - Top of range
465
- * *NAPOT* (3) - Naturally aligned power of two
466
-
467
- [when="PMP_GRANULARITY >= 2"]
468
- Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
469
440
 
470
441
  h! X ! 58 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
471
442
  h! W ! 57 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -474,23 +445,28 @@ fields:
474
445
 
475
446
  The combination of R = 0, W = 1 is reserved.
476
447
  type(): |
477
- if (NUM_PMP_ENTRIES > 47) {
448
+ if (NUM_USABLE_PMP_ENTRIES > 47) {
478
449
  return CsrFieldType::RWR;
479
450
  } else {
451
+ # entry is either not implemented or implemented as read-only zero
480
452
  return CsrFieldType::RO;
481
453
  }
482
454
  reset_value(): |
483
455
  return 0;
484
456
  sw_write(csr_value): |
485
- if ((xlen() == 64) && (CSR[pmpcfg10].pmp47cfg & 0x80) == 0) {
486
- # entry is not locked
487
- if (!(((csr_value.pmp47cfg & 0x1) == 0) && ((csr_value.pmp47cfg & 0x2) == 0x2))) {
488
- # not R = 0, W =1, which is reserved
489
- if ((PMP_GRANULARITY < 2) ||
490
- ((csr_value.pmp47cfg & 0x18) != 0x10)) {
491
- # NA4 is not allowed when PMP granularity is larger than 4 bytes
492
- return csr_value.pmp47cfg;
457
+ if ((xlen() == 64) && NUM_USABLE_PMP_ENTRIES > 47 && (CSR[pmpcfg10].pmp47cfg & 0x80) == 0) {
458
+ # entry is usable and not locked
459
+ Bits<8> new_cfg = csr_value.pmp47cfg;
460
+ Bits<2> a_mode = (new_cfg & 0x18) >> 3;
461
+ if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
462
+ # not R = 0, W = 1, which is reserved
463
+ if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
464
+ ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
465
+ ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
466
+ # unsupported address matching mode; keep old value
467
+ return CSR[pmpcfg10].pmp47cfg;
493
468
  }
469
+ return new_cfg;
494
470
  }
495
471
  }
496
472
  # fall through: keep old value