udb 0.1.13 → 0.1.14

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (189) hide show
  1. checksums.yaml +4 -4
  2. data/.data/cfgs/example_rv64_with_overlay.yaml +15 -18
  3. data/.data/cfgs/qc_iu.yaml +5 -1
  4. data/.data/cfgs/rv32-riscv-tests.yaml +4 -1
  5. data/.data/cfgs/rv32-vector.yaml +4 -1
  6. data/.data/cfgs/rv64-riscv-tests.yaml +4 -1
  7. data/.data/cfgs/rv64-vector.yaml +4 -1
  8. data/.data/spec/custom/isa/qc_iu/ext/Xqccmi.yaml +107 -36
  9. data/.data/spec/custom/isa/qc_iu/inst/Xqccmi/qc.cm.ilut.yaml +52 -69
  10. data/.data/spec/custom/isa/qc_iu/isa/globals.isa +27 -5
  11. data/.data/spec/schemas/config_schema.json +1 -1
  12. data/.data/spec/schemas/mmr_schema.json +3 -3
  13. data/.data/spec/schemas/schema_defs.json +5 -0
  14. data/.data/spec/std/isa/csr/H/henvcfg.yaml +25 -0
  15. data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +6 -4
  16. data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +6 -4
  17. data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +6 -4
  18. data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +6 -4
  19. data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +6 -4
  20. data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +6 -4
  21. data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +6 -4
  22. data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +6 -4
  23. data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +6 -4
  24. data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +6 -4
  25. data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +6 -4
  26. data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +6 -4
  27. data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +6 -4
  28. data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +6 -4
  29. data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +6 -4
  30. data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +6 -4
  31. data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +6 -4
  32. data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +6 -4
  33. data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +6 -4
  34. data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +6 -4
  35. data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +6 -4
  36. data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +6 -4
  37. data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +6 -4
  38. data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +6 -4
  39. data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +6 -4
  40. data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +6 -4
  41. data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +6 -4
  42. data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +6 -4
  43. data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +6 -4
  44. data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +6 -4
  45. data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +6 -4
  46. data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +6 -4
  47. data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +6 -4
  48. data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +6 -4
  49. data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +6 -4
  50. data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +6 -4
  51. data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +6 -4
  52. data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +6 -4
  53. data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +6 -4
  54. data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +6 -4
  55. data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +6 -4
  56. data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +6 -4
  57. data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +6 -4
  58. data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +6 -4
  59. data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +6 -4
  60. data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +6 -4
  61. data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +6 -4
  62. data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +6 -4
  63. data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +6 -4
  64. data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +6 -4
  65. data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +6 -4
  66. data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +6 -4
  67. data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +6 -4
  68. data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +6 -4
  69. data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +6 -4
  70. data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +6 -4
  71. data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +6 -4
  72. data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +6 -4
  73. data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +6 -4
  74. data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +6 -4
  75. data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +6 -4
  76. data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +6 -4
  77. data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +6 -4
  78. data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +6 -4
  79. data/.data/spec/std/isa/csr/I/pmpaddrN.layout +6 -4
  80. data/.data/spec/std/isa/csr/I/pmpcfg0.yaml +120 -144
  81. data/.data/spec/std/isa/csr/I/pmpcfg1.yaml +60 -72
  82. data/.data/spec/std/isa/csr/I/pmpcfg10.yaml +120 -144
  83. data/.data/spec/std/isa/csr/I/pmpcfg11.yaml +60 -72
  84. data/.data/spec/std/isa/csr/I/pmpcfg12.yaml +120 -144
  85. data/.data/spec/std/isa/csr/I/pmpcfg13.yaml +60 -72
  86. data/.data/spec/std/isa/csr/I/pmpcfg14.yaml +120 -144
  87. data/.data/spec/std/isa/csr/I/pmpcfg15.yaml +60 -72
  88. data/.data/spec/std/isa/csr/I/pmpcfg2.yaml +120 -144
  89. data/.data/spec/std/isa/csr/I/pmpcfg3.yaml +60 -72
  90. data/.data/spec/std/isa/csr/I/pmpcfg4.yaml +120 -144
  91. data/.data/spec/std/isa/csr/I/pmpcfg5.yaml +60 -72
  92. data/.data/spec/std/isa/csr/I/pmpcfg6.yaml +120 -144
  93. data/.data/spec/std/isa/csr/I/pmpcfg7.yaml +60 -72
  94. data/.data/spec/std/isa/csr/I/pmpcfg8.yaml +120 -144
  95. data/.data/spec/std/isa/csr/I/pmpcfg9.yaml +60 -72
  96. data/.data/spec/std/isa/csr/I/pmpcfgN.layout +15 -18
  97. data/.data/spec/std/isa/csr/jvt.yaml +1 -0
  98. data/.data/spec/std/isa/csr/menvcfg.yaml +20 -0
  99. data/.data/spec/std/isa/csr/mstatus.yaml +8 -6
  100. data/.data/spec/std/isa/csr/senvcfg.yaml +26 -0
  101. data/.data/spec/std/isa/inst/B/andn.yaml +10 -12
  102. data/.data/spec/std/isa/inst/B/clmul.yaml +9 -11
  103. data/.data/spec/std/isa/inst/B/clmulh.yaml +9 -11
  104. data/.data/spec/std/isa/inst/B/orn.yaml +9 -11
  105. data/.data/spec/std/isa/inst/B/rev8.yaml +1 -1
  106. data/.data/spec/std/isa/inst/B/rol.yaml +9 -11
  107. data/.data/spec/std/isa/inst/B/rolw.yaml +9 -11
  108. data/.data/spec/std/isa/inst/B/ror.yaml +9 -11
  109. data/.data/spec/std/isa/inst/B/rorw.yaml +9 -11
  110. data/.data/spec/std/isa/inst/B/xnor.yaml +9 -11
  111. data/.data/spec/std/isa/inst/C/c.ldsp.yaml +3 -3
  112. data/.data/spec/std/isa/inst/I/addi.yaml +1 -0
  113. data/.data/spec/std/isa/inst/I/addiw.yaml +1 -0
  114. data/.data/spec/std/isa/inst/I/andi.yaml +1 -0
  115. data/.data/spec/std/isa/inst/I/auipc.yaml +1 -0
  116. data/.data/spec/std/isa/inst/I/lb.yaml +1 -0
  117. data/.data/spec/std/isa/inst/I/lbu.yaml +1 -0
  118. data/.data/spec/std/isa/inst/I/ld.yaml +2 -0
  119. data/.data/spec/std/isa/inst/I/lh.yaml +1 -0
  120. data/.data/spec/std/isa/inst/I/lhu.yaml +1 -0
  121. data/.data/spec/std/isa/inst/I/lui.yaml +1 -0
  122. data/.data/spec/std/isa/inst/I/lw.yaml +1 -0
  123. data/.data/spec/std/isa/inst/I/lwu.yaml +1 -0
  124. data/.data/spec/std/isa/inst/I/ori.yaml +1 -0
  125. data/.data/spec/std/isa/inst/I/sb.yaml +1 -0
  126. data/.data/spec/std/isa/inst/I/sd.yaml +1 -0
  127. data/.data/spec/std/isa/inst/I/sh.yaml +1 -0
  128. data/.data/spec/std/isa/inst/I/slti.yaml +1 -0
  129. data/.data/spec/std/isa/inst/I/sltiu.yaml +1 -0
  130. data/.data/spec/std/isa/inst/I/sw.yaml +1 -0
  131. data/.data/spec/std/isa/inst/I/xori.yaml +1 -0
  132. data/.data/spec/std/isa/inst/V/vadc.vim.yaml +1 -0
  133. data/.data/spec/std/isa/inst/V/vadd.vi.yaml +1 -0
  134. data/.data/spec/std/isa/inst/V/vand.vi.yaml +1 -0
  135. data/.data/spec/std/isa/inst/V/vle8.v.yaml +1 -0
  136. data/.data/spec/std/isa/inst/V/vmadc.vi.yaml +1 -0
  137. data/.data/spec/std/isa/inst/V/vmadc.vim.yaml +1 -0
  138. data/.data/spec/std/isa/inst/V/vmerge.vim.yaml +1 -0
  139. data/.data/spec/std/isa/inst/V/vmseq.vi.yaml +1 -0
  140. data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml +1 -0
  141. data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml +1 -0
  142. data/.data/spec/std/isa/inst/V/vmsle.vi.yaml +1 -0
  143. data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml +1 -0
  144. data/.data/spec/std/isa/inst/V/vmsne.vi.yaml +1 -0
  145. data/.data/spec/std/isa/inst/V/vor.vi.yaml +1 -0
  146. data/.data/spec/std/isa/inst/V/vrsub.vi.yaml +1 -0
  147. data/.data/spec/std/isa/inst/V/vsadd.vi.yaml +1 -0
  148. data/.data/spec/std/isa/inst/V/vsaddu.vi.yaml +1 -0
  149. data/.data/spec/std/isa/inst/V/vse8.v.yaml +1 -0
  150. data/.data/spec/std/isa/inst/Zawrs/wrs.nto.yaml +4 -2
  151. data/.data/spec/std/isa/inst/Zba/add.uw.yaml +9 -11
  152. data/.data/spec/std/isa/inst/Zbb/orc.b.yaml +1 -1
  153. data/.data/spec/std/isa/inst/Zbkb/brev8.yaml +3 -3
  154. data/.data/spec/std/isa/inst/Zbkb/unzip.yaml +2 -2
  155. data/.data/spec/std/isa/inst/Zbkb/zip.yaml +2 -2
  156. data/.data/spec/std/isa/inst/Zbkx/xperm4.yaml +2 -2
  157. data/.data/spec/std/isa/inst/Zbkx/xperm8.yaml +2 -2
  158. data/.data/spec/std/isa/inst/Zicbop/prefetch.i.yaml +2 -0
  159. data/.data/spec/std/isa/inst/Zicbop/prefetch.r.yaml +2 -0
  160. data/.data/spec/std/isa/inst/Zicbop/prefetch.w.yaml +2 -0
  161. data/.data/spec/std/isa/inst/Zks/sm3p0.yaml +1 -1
  162. data/.data/spec/std/isa/inst/Zks/sm3p1.yaml +1 -1
  163. data/.data/spec/std/isa/inst/Zks/sm4ed.yaml +1 -1
  164. data/.data/spec/std/isa/inst/Zks/sm4ks.yaml +1 -1
  165. data/.data/spec/std/isa/isa/builtin_functions.idl +1 -0
  166. data/.data/spec/std/isa/isa/globals.isa +27 -7
  167. data/.data/spec/std/isa/isa/interrupts.idl +1 -0
  168. data/.data/spec/std/isa/param/HSTATEEN_CONTEXT_TYPE.yaml +1 -0
  169. data/.data/spec/std/isa/param/MSTATEEN_CONTEXT_TYPE.yaml +1 -0
  170. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml +1 -0
  171. data/.data/spec/std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml +1 -0
  172. data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +11 -22
  173. data/.data/spec/std/isa/param/NUM_USABLE_PMP_ENTRIES.yaml +35 -0
  174. data/.data/spec/std/isa/param/PMP_NA4_SUPPORTED.yaml +23 -0
  175. data/.data/spec/std/isa/param/PMP_NAPOT_SUPPORTED.yaml +19 -0
  176. data/.data/spec/std/isa/param/{MSTATUS_TVM_IMPLEMENTED.yaml → PMP_TOR_SUPPORTED.yaml} +6 -6
  177. data/.data/spec/std/isa/param/PRECISE_SYNCHRONOUS_EXCEPTIONS.yaml +1 -0
  178. data/.data/spec/std/isa/param/TRAP_ON_EBREAK.yaml +1 -0
  179. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_M.yaml +1 -0
  180. data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -0
  181. data/.data/spec/std/isa/param/ZAWRS_NTO_IS_NOP.yaml +19 -0
  182. data/lib/udb/ESPRESSO_VERSION +1 -1
  183. data/lib/udb/config.rb +14 -2
  184. data/lib/udb/doc_link.rb +3 -4
  185. data/lib/udb/obj/instruction.rb +1 -1
  186. data/lib/udb/obj/non_isa_specification.rb +22 -100
  187. data/lib/udb/version.rb +1 -1
  188. data/lib/udb/z3.rb +2 -2
  189. metadata +7 -3
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 54
31
31
  (or, if `pmp55cfg.A` == TOR, for PMP entry 55).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 54) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 54) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 54) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 54) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 55
31
31
  (or, if `pmp56cfg.A` == TOR, for PMP entry 56).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 55) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 55) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 55) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 55) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 56
31
31
  (or, if `pmp57cfg.A` == TOR, for PMP entry 57).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 56) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 56) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 56) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 56) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 57
31
31
  (or, if `pmp58cfg.A` == TOR, for PMP entry 58).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 57) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 57) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 57) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 57) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 58
31
31
  (or, if `pmp59cfg.A` == TOR, for PMP entry 59).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 58) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 58) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 58) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 58) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 59
31
31
  (or, if `pmp60cfg.A` == TOR, for PMP entry 60).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 59) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 59) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 59) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 59) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 6
31
31
  (or, if `pmp7cfg.A` == TOR, for PMP entry 7).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 6) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 6) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 6) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 6) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 60
31
31
  (or, if `pmp61cfg.A` == TOR, for PMP entry 61).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 60) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 60) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 60) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 60) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 61
31
31
  (or, if `pmp62cfg.A` == TOR, for PMP entry 62).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 61) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 61) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 61) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 61) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 62
31
31
  (or, if `pmp63cfg.A` == TOR, for PMP entry 63).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 62) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 62) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 62) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 62) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 63
31
31
  (or, if `pmp64cfg.A` == TOR, for PMP entry 64).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 63) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 63) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 63) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 63) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 7
31
31
  (or, if `pmp8cfg.A` == TOR, for PMP entry 8).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 7) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 7) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 7) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 7) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 8
31
31
  (or, if `pmp9cfg.A` == TOR, for PMP entry 9).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 8) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 8) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 8) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 8) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -30,17 +30,19 @@ fields:
30
30
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 9
31
31
  (or, if `pmp10cfg.A` == TOR, for PMP entry 10).
32
32
  type(): |
33
- if (NUM_PMP_ENTRIES > 9) {
33
+ if (NUM_USABLE_PMP_ENTRIES > 9) {
34
34
  return CsrFieldType::RW;
35
35
  } else {
36
+ # entry is either not implemented or implemented as read-only zero
36
37
  return CsrFieldType::RO;
37
38
  }
38
39
  reset_value(): |
39
40
  return 0;
40
41
  sw_write(csr_value): |
41
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
42
- return UNDEFINED_LEGAL_DETERMINISTIC;
43
- } else if (NUM_PMP_ENTRIES <= 9) {
42
+ if (NUM_USABLE_PMP_ENTRIES <= 9) {
43
+ # entry is not usable (not implemented or read-only zero)
44
+ return 0;
45
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
46
  return UNDEFINED_LEGAL_DETERMINISTIC;
45
47
  } else {
46
48
  return csr_value.ADDR;
@@ -32,17 +32,19 @@ fields:
32
32
  Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry <%= pmpaddr_num %>
33
33
  (or, if `pmp<%= pmpaddr_num+1 %>cfg.A` == TOR, for PMP entry <%= pmpaddr_num + 1 %>).
34
34
  type(): |
35
- if (NUM_PMP_ENTRIES > <%= pmpaddr_num %>) {
35
+ if (NUM_USABLE_PMP_ENTRIES > <%= pmpaddr_num %>) {
36
36
  return CsrFieldType::RW;
37
37
  } else {
38
+ # entry is either not implemented or implemented as read-only zero
38
39
  return CsrFieldType::RO;
39
40
  }
40
41
  reset_value(): |
41
42
  return 0;
42
43
  sw_write(csr_value): |
43
- if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
44
- return UNDEFINED_LEGAL_DETERMINISTIC;
45
- } else if (NUM_PMP_ENTRIES <= <%= pmpaddr_num %>) {
44
+ if (NUM_USABLE_PMP_ENTRIES <= <%= pmpaddr_num %>) {
45
+ # entry is not usable (not implemented or read-only zero)
46
+ return 0;
47
+ } else if (csr_value.ADDR >= ((1 `<< (PHYS_ADDR_WIDTH - 2)) - 1)) {
46
48
  return UNDEFINED_LEGAL_DETERMINISTIC;
47
49
  } else {
48
50
  return csr_value.ADDR;