udb 0.1.13 → 0.1.14

data/.data/spec/std/isa/inst/B/xnor.yaml

@@ -15,17 +15,15 @@ definedBy:
       - name: Zbb
       - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: XNOR
-      value: 0b0100000
-    funct3:
-      display_name: XNOR
-      value: 0b100
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0100000----------100-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/C/c.ldsp.yaml

@@ -57,8 +57,8 @@ operation(): |
   Bits<64> value = read_memory(64, virtual_address, $encoding);
 
   if (xlen()== 64) {
-    X[creg2reg(xd)] = value;
+    X[xd] = value;
   } else if (xlen() == 32) {
-    X[creg2reg(xd)]     = value[31:0];
-    X[creg2reg(xd) + 1] = value[63:32];
+    X[xd]     = value[31:0];
+    X[xd + 1] = value[63:32];
   }

data/.data/spec/std/isa/inst/I/addi.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/addiw.yaml

@@ -21,6 +21,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/andi.yaml

@@ -17,6 +17,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/auipc.yaml

@@ -18,6 +18,7 @@ encoding:
     - name: imm
       location: 31-12
       left_shift: 12
+      sign_extend: true
     - name: xd
       location: 11-7
 hints:

data/.data/spec/std/isa/inst/I/lb.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/lbu.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/ld.yaml

@@ -29,6 +29,7 @@ encoding:
     variables:
       - name: imm
         location: 31-20
+        sign_extend: true
       - name: xs1
         location: 19-15
       - name: xd
@@ -39,6 +40,7 @@ encoding:
     variables:
       - name: imm
         location: 31-20
+        sign_extend: true
       - name: xs1
         location: 19-15
       - name: xd

data/.data/spec/std/isa/inst/I/lh.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/lhu.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/lui.yaml

@@ -18,6 +18,7 @@ encoding:
     - name: imm
       location: 31-12
       left_shift: 12
+      sign_extend: true
     - name: xd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/I/lw.yaml

@@ -20,6 +20,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/lwu.yaml

@@ -22,6 +22,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/ori.yaml

@@ -17,6 +17,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/sb.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: xs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/I/sd.yaml

@@ -25,6 +25,7 @@ encoding:
     variables:
       - name: imm
         location: 31-25|11-7
+        sign_extend: true
       - name: xs2
         not: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
         location: 24-20

data/.data/spec/std/isa/inst/I/sh.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: xs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/I/slti.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/sltiu.yaml

@@ -23,6 +23,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/I/sw.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-25|11-7
+      sign_extend: true
     - name: xs2
       location: 24-20
     - name: xs1

data/.data/spec/std/isa/inst/I/xori.yaml

@@ -19,6 +19,7 @@ encoding:
   variables:
     - name: imm
       location: 31-20
+      sign_extend: true
     - name: xs1
       location: 19-15
     - name: xd

data/.data/spec/std/isa/inst/V/vadc.vim.yaml

@@ -20,6 +20,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vadd.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vand.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vle8.v.yaml

@@ -36,3 +36,4 @@ operation(): |
     U32 end_bit_pos = start_bit_pos + 7;
     V[vd][end_bit_pos:start_bit_pos] = read_memory(8, virtual_address + i, $encoding)[7:0];
   }
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/V/vmadc.vi.yaml

@@ -20,6 +20,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmadc.vim.yaml

@@ -20,6 +20,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmerge.vim.yaml

@@ -20,6 +20,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmseq.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmsgt.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmsgtu.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmsle.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vmsne.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vor.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vrsub.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vsadd.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vsaddu.vi.yaml

@@ -22,6 +22,7 @@ encoding:
       location: 24-20
     - name: imm
       location: 19-15
+      sign_extend: true
     - name: vd
       location: 11-7
 access:

data/.data/spec/std/isa/inst/V/vse8.v.yaml

@@ -36,3 +36,4 @@ operation(): |
     U32 end_bit_pos = start_bit_pos + 7;
     write_memory(8, virtual_address + i, V[vs3][end_bit_pos:start_bit_pos], $encoding);
   }
+  CSR[vstart].VALUE = 0;

data/.data/spec/std/isa/inst/Zawrs/wrs.nto.yaml

@@ -73,5 +73,7 @@ operation(): |
     }
   }
 
-  # stall while the reservation set is valid and no interrupt is pending
-  wrs_nto();
+  if (!ZAWRS_NTO_IS_NOP) {
+    # stall while the reservation set is valid and no interrupt is pending
+    wrs_nto();
+  }

data/.data/spec/std/isa/inst/Zba/add.uw.yaml

@@ -16,17 +16,15 @@ definedBy:
     - extension:
         name: Zba
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ADD.UW
-      value: 0b0000100
-    funct3:
-      display_name: ADD.UW
-      value: 0b000
-    opcode: { $inherits: inst_opcode/OP-32.yaml#/data }
+encoding:
+  match: 0000100----------000-----0111011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/Zbb/orc.b.yaml

@@ -35,7 +35,7 @@ operation(): |
   XReg input = X[xs1];
   XReg output = 0;
 
-  for (U32 i=0; i<(xlen() - 8); i = i+8) {
+  for (U32 i=0; i < xlen(); i = i+8) {
     output[(i+7):i] = (input[(i+7):i] == 0) ? 8'd0 : ~8'd0;
   }
 

data/.data/spec/std/isa/inst/Zbkb/brev8.yaml

@@ -25,14 +25,14 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   XReg input = X[xs1];
   XReg output = 0;
 
-  for(U32 i=0; i<(xlen()-8); i = i+8) {
+  for(U32 i=0; i < xlen(); i = i+8) {
     for(U32 j=0; j<8; j = j+1) {
-      output[(i*8)+(7-j)] = input[(i*8)+j];
+      output[i+(7-j)] = input[i+j];
     }
   }
 

data/.data/spec/std/isa/inst/Zbkb/unzip.yaml

@@ -29,12 +29,12 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   XReg input = X[xs1];
   XReg output = 0;
 
-  for(U32 i=0; i<(xlen()/2-1); i = i+1) {
+  for(U32 i=0; i < (xlen()/2); i = i+1) {
     output[i] = input[2*i];
     output[i+xlen()/2] = input[2*i+1];
   }

data/.data/spec/std/isa/inst/Zbkb/zip.yaml

@@ -29,12 +29,12 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   XReg input = X[xs1];
   XReg output = 0;
 
-  for(U32 i=0; i<(xlen()/2-1); i = i+1){
+  for(U32 i=0; i < (xlen()/2); i = i+1){
     output[2*i] = input[i];
     output[2*i+1] = input[i+xlen()/2];
   }

data/.data/spec/std/isa/inst/Zbkx/xperm4.yaml

@@ -29,13 +29,13 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   XReg input1 = X[xs1];
   XReg input2 = X[xs2];
   XReg output = 0;
 
-  for(U32 i=0; i<(xlen()-4); i = i+4) {
+  for(U32 i=0; i < xlen(); i = i+4) {
     XReg index = input2[i+3:i];
     if(4*index < xlen()) {
       output[i+3:i] = input1[4*index+3:4*index];

data/.data/spec/std/isa/inst/Zbkx/xperm8.yaml

@@ -29,13 +29,13 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |
   XReg input1 = X[xs1];
   XReg input2 = X[xs2];
   XReg output = 0;
 
-  for(U32 i=0; i<(xlen()-8); i = i+8) {
+  for(U32 i=0; i < xlen(); i = i+8) {
     XReg index = input2[i+7:i];
     if(8*index < xlen()) {
       output[i+7:i] = input1[8*index+7:8*index];

data/.data/spec/std/isa/inst/Zicbop/prefetch.i.yaml

@@ -21,6 +21,8 @@ encoding:
   variables:
     - name: imm
       location: 31-25
+      left_shift: 5
+      sign_extend: true
     - name: xs1
       location: 19-15
 access:

data/.data/spec/std/isa/inst/Zicbop/prefetch.r.yaml

@@ -21,6 +21,8 @@ encoding:
   variables:
     - name: imm
       location: 31-25
+      left_shift: 5
+      sign_extend: true
     - name: xs1
       location: 19-15
 access:

data/.data/spec/std/isa/inst/Zicbop/prefetch.w.yaml

@@ -21,6 +21,8 @@ encoding:
   variables:
     - name: imm
       location: 31-25
+      left_shift: 5
+      sign_extend: true
     - name: xs1
       location: 19-15
 access:

data/.data/spec/std/isa/inst/Zks/sm3p0.yaml

@@ -25,5 +25,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |

data/.data/spec/std/isa/inst/Zks/sm3p1.yaml

@@ -25,5 +25,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |

data/.data/spec/std/isa/inst/Zks/sm4ed.yaml

@@ -29,5 +29,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |

data/.data/spec/std/isa/inst/Zks/sm4ks.yaml

@@ -29,5 +29,5 @@ access:
   u: always
   vs: always
   vu: always
-data_independent_timing: false
+data_independent_timing: true
 operation(): |

data/.data/spec/std/isa/isa/builtin_functions.idl

@@ -439,6 +439,7 @@ function read_physical_memory {
       return read_physical_memory_64(paddr);
     } else {
       assert(false, "Invalid len");
+      return 0;
     }
   }
 }