udb 0.1.13 → 0.1.14

data/.data/spec/std/isa/csr/I/pmpcfg9.yaml

@@ -38,21 +38,13 @@ fields:
       h! L ! 7   ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
       h! MT ! 6:5 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry.  See the `Smpmpmt` extension definition for encodings.  When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
       h! A ! 4:3
-      a! Address matching mode. One of:
+      a! Address matching mode. Encodings:
 
-          [when="PMP_GRANULARITY < 2"]
           * *OFF* (0) - Null region (disabled)
           * *TOR* (1) - Top of range
           * *NA4* (2) - Naturally aligned four-byte region
           * *NAPOT* (3) - Naturally aligned power of two
 
-          [when="PMP_GRANULARITY >= 2"]
-          * *OFF* (0) - Null region (disabled)
-          * *TOR* (1) - Top of range
-          * *NAPOT* (3) - Naturally aligned power of two
-
-      [when="PMP_GRANULARITY >= 2"]
-      Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
 
       h! X ! 2 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
       h! W ! 1 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -61,23 +53,28 @@ fields:
 
       The combination of R = 0, W = 1 is reserved.
     type(): |
-      if (NUM_PMP_ENTRIES > 36) {
+      if (NUM_USABLE_PMP_ENTRIES > 36) {
         return CsrFieldType::RWR;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if ((CSR[pmpcfg9].pmp36cfg & 0x80) == 0) {
-        # entry is not locked
-        if (!(((csr_value.pmp36cfg & 0x1) == 0) && ((csr_value.pmp36cfg & 0x2) == 0x2))) {
-          # not R = 0, W =1, which is reserved
-          if ((PMP_GRANULARITY < 2) ||
-              ((csr_value.pmp36cfg & 0x18) != 0x10)) {
-            # NA4 is not allowed when PMP granularity is larger than 4 bytes
-            return csr_value.pmp36cfg;
+      if (NUM_USABLE_PMP_ENTRIES > 36 && (CSR[pmpcfg9].pmp36cfg & 0x80) == 0) {
+        # entry is usable and not locked
+        Bits<8> new_cfg = csr_value.pmp36cfg;
+        Bits<2> a_mode = (new_cfg & 0x18) >> 3;
+        if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
+          # not R = 0, W = 1, which is reserved
+          if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
+              ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
+              ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
+            # unsupported address matching mode; keep old value
+            return CSR[pmpcfg9].pmp36cfg;
           }
+          return new_cfg;
         }
       }
       # fall through: keep old value
@@ -96,21 +93,13 @@ fields:
       h! L ! 15   ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
       h! MT ! 14:13 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry.  See the `Smpmpmt` extension definition for encodings.  When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
       h! A ! 12:11
-      a! Address matching mode. One of:
+      a! Address matching mode. Encodings:
 
-          [when="PMP_GRANULARITY < 2"]
           * *OFF* (0) - Null region (disabled)
           * *TOR* (1) - Top of range
           * *NA4* (2) - Naturally aligned four-byte region
           * *NAPOT* (3) - Naturally aligned power of two
 
-          [when="PMP_GRANULARITY >= 2"]
-          * *OFF* (0) - Null region (disabled)
-          * *TOR* (1) - Top of range
-          * *NAPOT* (3) - Naturally aligned power of two
-
-      [when="PMP_GRANULARITY >= 2"]
-      Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
 
       h! X ! 10 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
       h! W ! 9 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -119,23 +108,28 @@ fields:
 
       The combination of R = 0, W = 1 is reserved.
     type(): |
-      if (NUM_PMP_ENTRIES > 37) {
+      if (NUM_USABLE_PMP_ENTRIES > 37) {
         return CsrFieldType::RWR;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if ((CSR[pmpcfg9].pmp37cfg & 0x80) == 0) {
-        # entry is not locked
-        if (!(((csr_value.pmp37cfg & 0x1) == 0) && ((csr_value.pmp37cfg & 0x2) == 0x2))) {
-          # not R = 0, W =1, which is reserved
-          if ((PMP_GRANULARITY < 2) ||
-              ((csr_value.pmp37cfg & 0x18) != 0x10)) {
-            # NA4 is not allowed when PMP granularity is larger than 4 bytes
-            return csr_value.pmp37cfg;
+      if (NUM_USABLE_PMP_ENTRIES > 37 && (CSR[pmpcfg9].pmp37cfg & 0x80) == 0) {
+        # entry is usable and not locked
+        Bits<8> new_cfg = csr_value.pmp37cfg;
+        Bits<2> a_mode = (new_cfg & 0x18) >> 3;
+        if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
+          # not R = 0, W = 1, which is reserved
+          if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
+              ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
+              ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
+            # unsupported address matching mode; keep old value
+            return CSR[pmpcfg9].pmp37cfg;
           }
+          return new_cfg;
         }
       }
       # fall through: keep old value
@@ -154,21 +148,13 @@ fields:
       h! L ! 23   ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
       h! MT ! 22:21 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry.  See the `Smpmpmt` extension definition for encodings.  When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
       h! A ! 20:19
-      a! Address matching mode. One of:
+      a! Address matching mode. Encodings:
 
-          [when="PMP_GRANULARITY < 2"]
           * *OFF* (0) - Null region (disabled)
           * *TOR* (1) - Top of range
           * *NA4* (2) - Naturally aligned four-byte region
           * *NAPOT* (3) - Naturally aligned power of two
 
-          [when="PMP_GRANULARITY >= 2"]
-          * *OFF* (0) - Null region (disabled)
-          * *TOR* (1) - Top of range
-          * *NAPOT* (3) - Naturally aligned power of two
-
-      [when="PMP_GRANULARITY >= 2"]
-      Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
 
       h! X ! 18 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
       h! W ! 17 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -177,23 +163,28 @@ fields:
 
       The combination of R = 0, W = 1 is reserved.
     type(): |
-      if (NUM_PMP_ENTRIES > 38) {
+      if (NUM_USABLE_PMP_ENTRIES > 38) {
         return CsrFieldType::RWR;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if ((CSR[pmpcfg9].pmp38cfg & 0x80) == 0) {
-        # entry is not locked
-        if (!(((csr_value.pmp38cfg & 0x1) == 0) && ((csr_value.pmp38cfg & 0x2) == 0x2))) {
-          # not R = 0, W =1, which is reserved
-          if ((PMP_GRANULARITY < 2) ||
-              ((csr_value.pmp38cfg & 0x18) != 0x10)) {
-            # NA4 is not allowed when PMP granularity is larger than 4 bytes
-            return csr_value.pmp38cfg;
+      if (NUM_USABLE_PMP_ENTRIES > 38 && (CSR[pmpcfg9].pmp38cfg & 0x80) == 0) {
+        # entry is usable and not locked
+        Bits<8> new_cfg = csr_value.pmp38cfg;
+        Bits<2> a_mode = (new_cfg & 0x18) >> 3;
+        if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
+          # not R = 0, W = 1, which is reserved
+          if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
+              ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
+              ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
+            # unsupported address matching mode; keep old value
+            return CSR[pmpcfg9].pmp38cfg;
           }
+          return new_cfg;
         }
       }
       # fall through: keep old value
@@ -212,21 +203,13 @@ fields:
       h! L ! 31   ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
       h! MT ! 30:29 ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry.  See the `Smpmpmt` extension definition for encodings.  When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
       h! A ! 28:27
-      a! Address matching mode. One of:
+      a! Address matching mode. Encodings:
 
-          [when="PMP_GRANULARITY < 2"]
           * *OFF* (0) - Null region (disabled)
           * *TOR* (1) - Top of range
           * *NA4* (2) - Naturally aligned four-byte region
           * *NAPOT* (3) - Naturally aligned power of two
 
-          [when="PMP_GRANULARITY >= 2"]
-          * *OFF* (0) - Null region (disabled)
-          * *TOR* (1) - Top of range
-          * *NAPOT* (3) - Naturally aligned power of two
-
-      [when="PMP_GRANULARITY >= 2"]
-      Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
 
       h! X ! 26 ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
       h! W ! 25 ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -235,23 +218,28 @@ fields:
 
       The combination of R = 0, W = 1 is reserved.
     type(): |
-      if (NUM_PMP_ENTRIES > 39) {
+      if (NUM_USABLE_PMP_ENTRIES > 39) {
         return CsrFieldType::RWR;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if ((CSR[pmpcfg9].pmp39cfg & 0x80) == 0) {
-        # entry is not locked
-        if (!(((csr_value.pmp39cfg & 0x1) == 0) && ((csr_value.pmp39cfg & 0x2) == 0x2))) {
-          # not R = 0, W =1, which is reserved
-          if ((PMP_GRANULARITY < 2) ||
-              ((csr_value.pmp39cfg & 0x18) != 0x10)) {
-            # NA4 is not allowed when PMP granularity is larger than 4 bytes
-            return csr_value.pmp39cfg;
+      if (NUM_USABLE_PMP_ENTRIES > 39 && (CSR[pmpcfg9].pmp39cfg & 0x80) == 0) {
+        # entry is usable and not locked
+        Bits<8> new_cfg = csr_value.pmp39cfg;
+        Bits<2> a_mode = (new_cfg & 0x18) >> 3;
+        if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
+          # not R = 0, W = 1, which is reserved
+          if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
+              ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
+              ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
+            # unsupported address matching mode; keep old value
+            return CSR[pmpcfg9].pmp39cfg;
           }
+          return new_cfg;
         }
       }
       # fall through: keep old value

data/.data/spec/std/isa/csr/I/pmpcfgN.layout

@@ -50,21 +50,13 @@ fields:
       h! L ! <%= ((i+1)*8)-1 %>   ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.
       h! MT ! <%= ((i+1)*8)-2 %>:<%= ((i+1)*8)-3 %> ! When the `Smpmpmt` extension is implemented, MT (Memory Type) is a WARL field that overrides the memory type for accesses that match this PMP entry.  See the `Smpmpmt` extension definition for encodings.  When the `Smpmpmt` extension is not implemented, MT is _Reserved_ Writes shall be ignored.
       h! A ! <%= ((i+1)*8)-4 %>:<%= ((i+1)*8)-5 %>
-      a! Address matching mode. One of:
+      a! Address matching mode. Encodings:
 
-          [when="PMP_GRANULARITY < 2"]
           * *OFF* (0) - Null region (disabled)
           * *TOR* (1) - Top of range
           * *NA4* (2) - Naturally aligned four-byte region
           * *NAPOT* (3) - Naturally aligned power of two
 
-          [when="PMP_GRANULARITY >= 2"]
-          * *OFF* (0) - Null region (disabled)
-          * *TOR* (1) - Top of range
-          * *NAPOT* (3) - Naturally aligned power of two
-
-      [when="PMP_GRANULARITY >= 2"]
-      Naturally aligned four-byte region, *NA4* (2), is not valid (not needed when the PMP granularity is larger than 4 bytes).
 
       h! X ! <%= ((i)*8)+2 %> ! When clear, instruction fetches cause an `Access Fault` for the matching region and privilege mode.
       h! W ! <%= ((i)*8)+1 %> ! When clear, stores and AMOs cause an `Access Fault` for the matching region and privilege mode.
@@ -73,23 +65,28 @@ fields:
 
       The combination of R = 0, W = 1 is reserved.
     type(): |
-      if (NUM_PMP_ENTRIES > <%= pmpcfg_num*4 + i %>) {
+      if (NUM_USABLE_PMP_ENTRIES > <%= pmpcfg_num*4 + i %>) {
         return CsrFieldType::RWR;
       } else {
+        # entry is either not implemented or implemented as read-only zero
         return CsrFieldType::RO;
       }
     reset_value(): |
       return 0;
     sw_write(csr_value): |
-      if (<%- if i > 4 -%>(xlen() == 64) && <%- end -%>(CSR[<%= "pmpcfg#{pmpcfg_num}" %>].pmp<%= pmpcfg_num*4 + i %>cfg & 0x80) == 0) {
-        # entry is not locked
-        if (!(((csr_value.pmp<%= pmpcfg_num*4 + i %>cfg & 0x1) == 0) && ((csr_value.pmp<%= pmpcfg_num*4 + i %>cfg & 0x2) == 0x2))) {
-          # not R = 0, W =1, which is reserved
-          if ((PMP_GRANULARITY < 2) ||
-              ((csr_value.pmp<%= pmpcfg_num*4 + i %>cfg & 0x18) != 0x10)) {
-            # NA4 is not allowed when PMP granularity is larger than 4 bytes
-            return csr_value.pmp<%= pmpcfg_num*4 + i %>cfg;
+      if (<%- if i > 4 -%>(xlen() == 64) && <%- end -%>NUM_USABLE_PMP_ENTRIES > <%= pmpcfg_num*4 + i %> && (CSR[<%= "pmpcfg#{pmpcfg_num}" %>].pmp<%= pmpcfg_num*4 + i %>cfg & 0x80) == 0) {
+        # entry is usable and not locked
+        Bits<8> new_cfg = csr_value.pmp<%= pmpcfg_num*4 + i %>cfg;
+        Bits<2> a_mode = (new_cfg & 0x18) >> 3;
+        if (!(((new_cfg & 0x1) == 0) && ((new_cfg & 0x2) == 0x2))) {
+          # not R = 0, W = 1, which is reserved
+          if (((a_mode == 0x1) && !PMP_TOR_SUPPORTED) ||
+              ((a_mode == 0x2) && !PMP_NA4_SUPPORTED) ||
+              ((a_mode == 0x3) && !PMP_NAPOT_SUPPORTED)) {
+            # unsupported address matching mode; keep old value
+            return CSR[<%= "pmpcfg#{pmpcfg_num}" %>].pmp<%= pmpcfg_num*4 + i %>cfg;
           }
+          return new_cfg;
         }
       }
       # fall through: keep old value

data/.data/spec/std/isa/csr/jvt.yaml

@@ -56,6 +56,7 @@ fields:
             && (CSR[sstateen0].JVT == 1'b0 || CSR[hstateen0].JVT == 1'b0) )) {
 
         unimplemented_csr($encoding);
+        return 0;
       }
       else {
         if (JVT_BASE_TYPE == "custom") {

data/.data/spec/std/isa/csr/menvcfg.yaml

@@ -296,6 +296,26 @@ fields:
         name: Zicfiss
     type: RW
     reset_value: UNDEFINED_LEGAL
+  LPE:
+    location: 2
+    description: |
+      *Landing Pad Enable*
+
+      When the LPE field is set to 1 and S-mode is implemented, the Zicfilp
+      extension is enabled in S-mode. If the LPE field is set to 1 and S-mode
+      is not implemented, the Zicfilp extension is enabled in U-mode. When the
+      LPE field is 0, the Zicfilp extension is not enabled in S-mode (or U-mode
+      if S-mode is not implemented), and the following rules apply:
+
+        * The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`.
+        * The `LPAD` instruction operates as a no-op.
+
+      When `menvcfg.LPE` is 0, `henvcfg.LPE` and `senvcfg.LPE` are read-only zero.
+    definedBy:
+      extension:
+        name: Zicfilp
+    type: RW
+    reset_value: UNDEFINED_LEGAL
   FIOM:
     location: 0
     description: |

data/.data/spec/std/isa/csr/mstatus.yaml

@@ -328,6 +328,8 @@ fields:
     type(): |
       if (CSR[misa].S == 1'b0) {
         return CsrFieldType::RO;
+      } else if (!(implemented?(ExtensionName::Sv32) || implemented?(ExtensionName::Sv39) || implemented?(ExtensionName::Sv48) || implemented?(ExtensionName::Sv57))) {
+        return CsrFieldType::RO;
       } else {
         return CsrFieldType::RW;
       }
@@ -337,18 +339,18 @@ fields:
     reset_value(): |
       if (CSR[misa].S == 1'b0) {
         return 0;
-      } else if (MSTATUS_TVM_IMPLEMENTED) {
-        return UNDEFINED_LEGAL;
-      } else {
+      } else if (!(implemented?(ExtensionName::Sv32) || implemented?(ExtensionName::Sv39) || implemented?(ExtensionName::Sv48) || implemented?(ExtensionName::Sv57))) {
         return 0;
+      } else {
+        return UNDEFINED_LEGAL;
       }
     sw_write(csr_value): |
       if (CSR[misa].S == 1'b0) {
         return 0;
-      } else if (MSTATUS_TVM_IMPLEMENTED) {
-        return csr_value.TVM;
-      } else {
+      } else if (!(implemented?(ExtensionName::Sv32) || implemented?(ExtensionName::Sv39) || implemented?(ExtensionName::Sv48) || implemented?(ExtensionName::Sv57))) {
         return 0;
+      } else {
+        return csr_value.TVM;
       }
   MXR:
     location: 19

data/.data/spec/std/isa/csr/senvcfg.yaml

@@ -165,6 +165,28 @@ fields:
         return 0;
       }
       return csr_value.SSE;
+  LPE:
+    location: 2
+    description: |
+      *Landing Pad Enable*
+
+      When the LPE field is set to 1 and `menvcfg.LPE` is 1, the Zicfilp extension
+      is enabled in U/VU-mode. Read-only zero when `menvcfg.LPE` is 0. When the LPE
+      field is 0, the Zicfilp extension is not enabled in U/VU-mode and the following
+      rules apply:
+
+        * The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`.
+        * The `LPAD` instruction operates as a no-op.
+    definedBy:
+      extension:
+        name: Zicfilp
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[menvcfg].LPE == 0) {
+        return 0;
+      }
+      return csr_value.LPE;
   FIOM:
     location: 0
     description: |
@@ -202,4 +224,8 @@ sw_read(): |
     # senvcfg.SSE must read-as-zero
     value = value & ~(1 `<< 3);
   }
+  if (implemented?(ExtensionName::Zicfilp) && CSR[menvcfg].LPE == 0) {
+    # senvcfg.LPE must read-as-zero when menvcfg.LPE is 0
+    value = value & ~(1 `<< 2);
+  }
   return value;

data/.data/spec/std/isa/inst/B/andn.yaml

@@ -16,17 +16,15 @@ definedBy:
       - name: Zbb
       - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ANDN
-      value: 0b0100000
-    funct3:
-      display_name: ANDN
-      value: 0b111
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0100000----------111-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always
@@ -38,4 +36,4 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  X[xd] = X[xs2] & ~X[xs1];
+  X[xd] = X[xs1] & ~X[xs2];

data/.data/spec/std/isa/inst/B/clmul.yaml

@@ -15,17 +15,15 @@ definedBy:
       - name: Zbc
       - name: Zbkc
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: CLMUL
-      value: 0b0000101
-    funct3:
-      display_name: CLMUL
-      value: 0b001
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0000101----------001-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/clmulh.yaml

@@ -15,17 +15,15 @@ definedBy:
       - name: Zbc
       - name: Zbkc
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: CLMUL
-      value: 0b0000101
-    funct3:
-      display_name: CLMULH
-      value: 0b011
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0000101----------011-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/orn.yaml

@@ -15,17 +15,15 @@ definedBy:
       - name: Zbb
       - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ORN
-      value: 0b0100000
-    funct3:
-      display_name: ORN
-      value: 0b110
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0100000----------110-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/rev8.yaml

@@ -54,7 +54,7 @@ operation(): |
 
   XReg j = xlen() - 1;
 
-  for (U32 i=0; i<(xlen()-8); i = i+8) {
+  for (U32 i=0; i < xlen(); i = i+8) {
     output[(i+7):i] = input[j:(j-7)];
     j = j - 8;
   }

data/.data/spec/std/isa/inst/B/rol.yaml

@@ -15,17 +15,15 @@ definedBy:
       - name: Zbb
       - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ROL
-      value: 0b0110000
-    funct3:
-      display_name: ROL
-      value: 0b001
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0110000----------001-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/rolw.yaml

@@ -18,17 +18,15 @@ definedBy:
           - name: Zbb
           - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ROLW
-      value: 0b0110000
-    funct3:
-      display_name: ROLW
-      value: 0b001
-    opcode: { $inherits: inst_opcode/OP-32.yaml#/data }
+encoding:
+  match: 0110000----------001-----0111011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/ror.yaml

@@ -15,17 +15,15 @@ definedBy:
       - name: Zbb
       - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: ROR
-      value: 0b0110000
-    funct3:
-      display_name: ROR
-      value: 0b101
-    opcode: { $inherits: inst_opcode/OP.yaml#/data }
+encoding:
+  match: 0110000----------101-----0110011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always

data/.data/spec/std/isa/inst/B/rorw.yaml

@@ -19,17 +19,15 @@ definedBy:
           - name: Zbb
           - name: Zbkb
 assembly: xd, xs1, xs2
-format:
-  $inherits:
-    - inst_subtype/R/R-x.yaml#/data
-  opcodes:
-    funct7:
-      display_name: RORW
-      value: 0b0110000
-    funct3:
-      display_name: RORW
-      value: 0b101
-    opcode: { $inherits: inst_opcode/OP-32.yaml#/data }
+encoding:
+  match: 0110000----------101-----0111011
+  variables:
+    - name: xs2
+      location: 24-20
+    - name: xs1
+      location: 19-15
+    - name: xd
+      location: 11-7
 access:
   s: always
   u: always