ruby-vpi 7.0.0

data/samp/pipelined_alu/Hw5UnitModel.rb

@@ -0,0 +1,134 @@
+=begin
+  Copyright 2006 Suraj N. Kurapati
+
+  This file is part of Ruby-VPI.
+
+  Ruby-VPI is free software; you can redistribute it and/or
+  modify it under the terms of the GNU General Public License
+  as published by the Free Software Foundation; either version 2
+  of the License, or (at your option) any later version.
+
+  Ruby-VPI is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with Ruby-VPI; if not, write to the Free Software Foundation,
+  Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+=end
+
+# Behavioral model of the hw5_unit Verilog module.
+class Hw5UnitModel
+
+  # Represents an ALU operation.
+  class Operation
+    attr_accessor :type, :tag, :arg1, :arg2, :stage, :result
+
+    def initialize(type, tag, arg1 = 0, arg2 = 0)
+      raise ArgumentError unless OPERATIONS.include? type
+
+      @type = type
+      @tag = tag
+      @arg1 = arg1
+      @arg2 = arg2
+
+      @stage = 0
+    end
+
+    # Computes the result of this operation.
+    def compute
+      case @type
+        when :add
+          @arg1 + @arg2
+
+        when :sub
+          @arg1 - @arg2
+
+        when :mul
+          @arg1 * @arg2
+
+        when :nop
+          nil
+
+        else
+          raise
+      end
+    end
+
+    def compute!
+      @result = compute
+    end
+  end
+
+
+  # Supported types of ALU operations.
+  OPERATIONS = [ :add, :sub, :mul, :nop ]
+
+  # Number of cycles each operation uses.
+  OPERATION_LATENCIES = {
+    :add => 3, #1,
+    :sub => 3, #2,
+    :mul => 3, #3,
+    :nop => 3, #1,
+  }
+
+  # The famous no-operation.
+  NOP = Hw5UnitModel::Operation.new(:nop, nil)
+
+
+  def reset
+    @aluQueues = {}
+    @outputQueue = []
+
+    # create a separate pipeline for each operation
+    OPERATIONS.each do |op|
+      @aluQueues[op] = []
+    end
+  end
+
+  alias_method :initialize, :reset
+
+
+  # Starts the given operation during the present cycle.
+  def startOperation(op)
+    @aluQueues[op.type] << op
+
+    p "started operation:", op  if $DEBUG
+  end
+
+  # Performs the behavior for the present cycle.
+  def cycle
+    # perform ALU operations
+    @aluQueues.each_pair do |alu, pipeline|
+      finished = []
+
+      pipeline.each do |op|
+        # when the operation has finished all pipeline stages, compute the result and output it
+        if op.stage >= OPERATION_LATENCIES[op.type]
+          op.compute!
+          finished << op
+          @outputQueue << op
+        end
+
+
+        # perform the next stage of the operation
+        op.stage += 1
+      end
+
+
+      # remove finished operations from pipeline
+      @aluQueues[alu] = pipeline - finished
+    end
+  end
+
+  # Returns the output for the present cycle.
+  def output
+    unless @outputQueue.empty?
+      @outputQueue.shift
+    else
+      NOP
+    end
+  end
+
+end

data/samp/pipelined_alu/InputGenerator.rb

@@ -0,0 +1,94 @@
+=begin
+  Copyright 2006 Suraj N. Kurapati
+
+  This file is part of Ruby-VPI.
+
+  Ruby-VPI is free software; you can redistribute it and/or
+  modify it under the terms of the GNU General Public License
+  as published by the Free Software Foundation; either version 2
+  of the License, or (at your option) any later version.
+
+  Ruby-VPI is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with Ruby-VPI; if not, write to the Free Software Foundation,
+  Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+=end
+
+# Generates random input sequences of configurable length.
+class InputGenerator
+
+  # the first 1000 prime numbers, gotten from <http://en.wikipedia.org/wiki/List_of_prime_numbers#The_first_1000_prime_numbers>
+  PrimeNums = [
+    2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103, 107, 109, 113, 127, 131, 137, 139, 149, 151, 157, 163, 167, 173, 179, 181, 191, 193, 197, 199, 211, 223, 227, 229, 233, 239, 241, 251, 257, 263, 269, 271, 277, 281, 283, 293, 307, 311, 313, 317, 331, 337, 347, 349, 353, 359, 367, 373, 379, 383, 389, 397, 401, 409, 419, 421, 431, 433, 439, 443, 449, 457, 461, 463, 467, 479, 487, 491, 499, 503, 509, 521, 523, 541, 547, 557, 563, 569, 571, 577, 587, 593, 599, 601, 607, 613, 617, 619, 631, 641, 643, 647, 653, 659, 661, 673, 677, 683, 691, 701, 709, 719, 727, 733, 739, 743, 751, 757, 761, 769, 773, 787, 797, 809, 811, 821, 823, 827, 829, 839, 853, 857, 859, 863, 877, 881, 883, 887, 907, 911, 919, 929, 937, 941, 947, 953, 967, 971, 977, 983, 991, 997, 1009, 1013, 1019, 1021, 1031, 1033, 1039, 1049, 1051, 1061, 1063, 1069, 1087, 1091, 1093, 1097, 1103, 1109, 1117, 1123, 1129, 1151, 1153, 1163, 1171, 1181, 1187, 1193, 1201, 1213, 1217, 1223, 1229, 1231, 1237, 1249, 1259, 1277, 1279, 1283, 1289, 1291, 1297, 1301, 1303, 1307, 1319, 1321, 1327, 1361, 1367, 1373, 1381, 1399, 1409, 1423, 1427, 1429, 1433, 1439, 1447, 1451, 1453, 1459, 1471, 1481, 1483, 1487, 1489, 1493, 1499, 1511, 1523, 1531, 1543, 1549, 1553, 1559, 1567, 1571, 1579, 1583, 1597, 1601, 1607, 1609, 1613, 1619, 1621, 1627, 1637, 1657, 1663, 1667, 1669, 1693, 1697, 1699, 1709, 1721, 1723, 1733, 1741, 1747, 1753, 1759, 1777, 1783, 1787, 1789, 1801, 1811, 1823, 1831, 1847, 1861, 1867, 1871, 1873, 1877, 1879, 1889, 1901, 1907, 1913, 1931, 1933, 1949, 1951, 1973, 1979, 1987, 1993, 1997, 1999, 2003, 2011, 2017, 2027, 2029, 2039, 2053, 2063, 2069, 2081, 2083, 2087, 2089, 2099, 2111, 2113, 2129, 2131, 2137, 2141, 2143, 2153, 2161, 2179, 2203, 2207, 2213, 2221, 2237, 2239, 2243, 2251, 2267, 2269, 2273, 2281, 2287, 2293, 2297, 2309, 2311, 2333, 2339, 2341, 2347, 2351, 2357, 2371, 2377, 2381, 2383, 2389, 2393, 2399, 2411, 2417, 2423, 2437, 2441, 2447, 2459, 2467, 2473, 2477, 2503, 2521, 2531, 2539, 2543, 2549, 2551, 2557, 2579, 2591, 2593, 2609, 2617, 2621, 2633, 2647, 2657, 2659, 2663, 2671, 2677, 2683, 2687, 2689, 2693, 2699, 2707, 2711, 2713, 2719, 2729, 2731, 2741, 2749, 2753, 2767, 2777, 2789, 2791, 2797, 2801, 2803, 2819, 2833, 2837, 2843, 2851, 2857, 2861, 2879, 2887, 2897, 2903, 2909, 2917, 2927, 2939, 2953, 2957, 2963, 2969, 2971, 2999, 3001, 3011, 3019, 3023, 3037, 3041, 3049, 3061, 3067, 3079, 3083, 3089, 3109, 3119, 3121, 3137, 3163, 3167, 3169, 3181, 3187, 3191, 3203, 3209, 3217, 3221, 3229, 3251, 3253, 3257, 3259, 3271, 3299, 3301, 3307, 3313, 3319, 3323, 3329, 3331, 3343, 3347, 3359, 3361, 3371, 3373, 3389, 3391, 3407, 3413, 3433, 3449, 3457, 3461, 3463, 3467, 3469, 3491, 3499, 3511, 3517, 3527, 3529, 3533, 3539, 3541, 3547, 3557, 3559, 3571, 3581, 3583, 3593, 3607, 3613, 3617, 3623, 3631, 3637, 3643, 3659, 3671, 3673, 3677, 3691, 3697, 3701, 3709, 3719, 3727, 3733, 3739, 3761, 3767, 3769, 3779, 3793, 3797, 3803, 3821, 3823, 3833, 3847, 3851, 3853, 3863, 3877, 3881, 3889, 3907, 3911, 3917, 3919, 3923, 3929, 3931, 3943, 3947, 3967, 3989, 4001, 4003, 4007, 4013, 4019, 4021, 4027, 4049, 4051, 4057, 4073, 4079, 4091, 4093, 4099, 4111, 4127, 4129, 4133, 4139, 4153, 4157, 4159, 4177, 4201, 4211, 4217, 4219, 4229, 4231, 4241, 4243, 4253, 4259, 4261, 4271, 4273, 4283, 4289, 4297, 4327, 4337, 4339, 4349, 4357, 4363, 4373, 4391, 4397, 4409, 4421, 4423, 4441, 4447, 4451, 4457, 4463, 4481, 4483, 4493, 4507, 4513, 4517, 4519, 4523, 4547, 4549, 4561, 4567, 4583, 4591, 4597, 4603, 4621, 4637, 4639, 4643, 4649, 4651, 4657, 4663, 4673, 4679, 4691, 4703, 4721, 4723, 4729, 4733, 4751, 4759, 4783, 4787, 4789, 4793, 4799, 4801, 4813, 4817, 4831, 4861, 4871, 4877, 4889, 4903, 4909, 4919, 4931, 4933, 4937, 4943, 4951, 4957, 4967, 4969, 4973, 4987, 4993, 4999, 5003, 5009, 5011, 5021, 5023, 5039, 5051, 5059, 5077, 5081, 5087, 5099, 5101, 5107, 5113, 5119, 5147, 5153, 5167, 5171, 5179, 5189, 5197, 5209, 5227, 5231, 5233, 5237, 5261, 5273, 5279, 5281, 5297, 5303, 5309, 5323, 5333, 5347, 5351, 5381, 5387, 5393, 5399, 5407, 5413, 5417, 5419, 5431, 5437, 5441, 5443, 5449, 5471, 5477, 5479, 5483, 5501, 5503, 5507, 5519, 5521, 5527, 5531, 5557, 5563, 5569, 5573, 5581, 5591, 5623, 5639, 5641, 5647, 5651, 5653, 5657, 5659, 5669, 5683, 5689, 5693, 5701, 5711, 5717, 5737, 5741, 5743, 5749, 5779, 5783, 5791, 5801, 5807, 5813, 5821, 5827, 5839, 5843, 5849, 5851, 5857, 5861, 5867, 5869, 5879, 5881, 5897, 5903, 5923, 5927, 5939, 5953, 5981, 5987, 6007, 6011, 6029, 6037, 6043, 6047, 6053, 6067, 6073, 6079, 6089, 6091, 6101, 6113, 6121, 6131, 6133, 6143, 6151, 6163, 6173, 6197, 6199, 6203, 6211, 6217, 6221, 6229, 6247, 6257, 6263, 6269, 6271, 6277, 6287, 6299, 6301, 6311, 6317, 6323, 6329, 6337, 6343, 6353, 6359, 6361, 6367, 6373, 6379, 6389, 6397, 6421, 6427, 6449, 6451, 6469, 6473, 6481, 6491, 6521, 6529, 6547, 6551, 6553, 6563, 6569, 6571, 6577, 6581, 6599, 6607, 6619, 6637, 6653, 6659, 6661, 6673, 6679, 6689, 6691, 6701, 6703, 6709, 6719, 6733, 6737, 6761, 6763, 6779, 6781, 6791, 6793, 6803, 6823, 6827, 6829, 6833, 6841, 6857, 6863, 6869, 6871, 6883, 6899, 6907, 6911, 6917, 6947, 6949, 6959, 6961, 6967, 6971, 6977, 6983, 6991, 6997, 7001, 7013, 7019, 7027, 7039, 7043, 7057, 7069, 7079, 7103, 7109, 7121, 7127, 7129, 7151, 7159, 7177, 7187, 7193, 7207, 7211, 7213, 7219, 7229, 7237, 7243, 7247, 7253, 7283, 7297, 7307, 7309, 7321, 7331, 7333, 7349, 7351, 7369, 7393, 7411, 7417, 7433, 7451, 7457, 7459, 7477, 7481, 7487, 7489, 7499, 7507, 7517, 7523, 7529, 7537, 7541, 7547, 7549, 7559, 7561, 7573, 7577, 7583, 7589, 7591, 7603, 7607, 7621, 7639, 7643, 7649, 7669, 7673, 7681, 7687, 7691, 7699, 7703, 7717, 7723, 7727, 7741, 7753, 7757, 7759, 7789, 7793, 7817, 7823, 7829, 7841, 7853, 7867, 7873, 7877, 7879, 7883, 7901, 7907, 7919
+  ]
+
+
+
+  # @param	bits	Number of bits that can be used to represent a generated input sequence
+  def initialize(bits)
+    self.bits = bits
+  end
+
+
+
+  # gets the number of bits that can be used to represent a generated input sequence
+  def bits
+    @inputBits
+  end
+
+
+
+  # sets the number of bits that can be used to represent a generated input sequence
+  def bits=(num)
+    @inputBits = num
+    @inputLimit = 2 ** @inputBits
+  end
+
+
+
+  # generates a random input sequence
+  def gen
+    # randomly select a specific kind of integer to generate
+    # @note param to rand() is number of situations in this 'case' block
+    case rand(6)
+      when 0 # positive numbers
+        rand(@inputLimit)
+
+      when 1 # negative numbers
+        -rand(@inputLimit)
+
+      when 2 # zero
+        0
+
+      when 3 # one
+        1
+
+      when 4 # prime numbers
+        genPrime
+
+      when 5 # power-of-two numbers
+        genPowerOfTwo
+    end
+  end
+
+
+
+  # generates a random prime number
+  def genPrime
+    prime = PrimeNums[rand(PrimeNums.size)]
+    prime < @inputLimit ? prime : 2
+  end
+
+
+
+  # generates a random power-of-two number
+  def genPowerOfTwo
+    power = rand(@inputBits) + 1
+    (2 ** power) - 1
+  end
+
+end

data/samp/pipelined_alu/README

@@ -0,0 +1,127 @@
+PIPELINED ALU
+
+  This example is my solution to a homework assignment for an Advanced Logic Design class I had taken during the Winter of 2006 at University of California, Santa Cruz. Relevant portions of the problem have been revised and reproduced here with permission from the instructor: professor Jose Renau.
+
+
+
+PROBLEM
+
+  Implement the functionality for hw5 unit, a pipelined ALU:
+
+  `define  WIDTH      32
+  `define  DATABITS   7
+  `define  OP_NOP     0
+  `define  OP_ADD     1
+  `define  OP_SUB     2
+  `define  OP_MULT    3
+
+  module hw5_unit(
+      input                           clk
+      ,input                          reset
+
+      // inputs
+      ,input     [`DATABITS-1:0]      in_databits
+      ,input     [`WIDTH-1:0]         a
+      ,input     [`WIDTH-1:0]         b
+      ,input     [1:0]                in_op
+
+      // outputs
+      ,output reg [`WIDTH-1:0]        res
+      ,output reg [`DATABITS-1:0]     out_databits
+      ,output reg [1:0]               out_op
+  );
+
+
+  MAJOR POINTS
+
+  1. in_op selects the operation to perform (OP_NOP means no operation).
+
+  2. A new operation may be started every cycle.
+
+  3. OP_ADD must have 1 cycle latency.
+
+  4. OP_SUB must have 2 cycles latency.
+
+  5. OP_MULT must have 3 cycles latency.
+
+  6. There is only one result (res). Since three operations can finish every cycle, you need to buffer the other two. Note that since at most one operation starts per cycle, a 3-entry buffer should be enough.
+
+  7. Each operation has an associated tag (in_databits) which you must pass back with the result (out_databits). For example, if a OP_MULT operation is started with parameters a=2, b=4, in_databits=3; then after the multiplication finishes three cycles later, the outputs should be res=8, out_databits=3, out_op=OP_MULT.
+
+  8. The testbench used to verify this module must:
+
+    a. Test random combinations of positive, zero, one, prime numbers, power-of-two values from powers 1 to 32, and random numbers.
+
+    b. Execute random combinations of add, subtract, and multiply operations.
+
+    c. Perform tests for 4000 ALU operations.
+
+
+
+DESIGN
+
+  From the start, my approach was to use a single queue to solve the resource conflict (only one ALU can give an output per cycle). After drawing some sketches and understanding the problem, I wrote the following algorithm to solve the resource conflict:
+
+    def queue_results(a, b, c)
+      output a
+      enqueue b, c
+    end
+
+
+  We cannot perform all the operations in the queue_results method using only one cycle. However, if the queue_results method is not implemented as shown, then the design will not work---it will be chaotic and produce incoherent results.
+
+  The trick is to satisfy the post-conditions of the queue_results method (one result is outputted and the other two have been queued) using multiple clock cycles:
+
+    1. enqueue b
+    (remember a and c)
+
+    2. enqueue c
+    (remember a)
+
+    3. output a
+
+    or
+
+    1. enqueue b
+    (remember a and c)
+
+    2. enqueue c; output a
+    (nothing to remember)
+
+  Note that we cannot output the 'a' result during the first cycle because that would violate the post-conditions.
+
+
+  After gaining this understanding, I realized that a separate queue was wholly unnecessary. Instead, I could simply use pipeline registers to remember values until they were needed (i.e. the 'a' result is output only in the last cycle).
+
+  This approach uses exactly the same number of pipeline registers (three in this case) as the size of the queue suggested by the Professor. Also, this approach uses less storage than the three-queues (one for each ALU output; therefore 9 registers) approach suggested by the Professor.
+
+
+  Finally, I wrote a behavioral model (see MODEL section) of the RTL using Ruby and verified both my initial approach (magical single-cycle queueing of multiple items) and its later improvement (the pipeline-register approach).
+
+
+
+MODEL
+
+  $ cd tests
+  $ ruby -w TestHw5UnitModel.rb		# use the "-d" option for details
+
+
+  The model is written in Ruby and comes with a unit test which is similar to the Ruby-VPI test bench I wrote for the RTL implementation.
+
+
+
+TEST BENCH
+
+  $ ulimit -s unlimited
+  $ make VERILOG=$VCS_HOME VCS_FLAGS="-cc gcc32 -ld gcc32" vcs
+
+  ... lots of output here ...
+
+  hw5_unit_tb.rb passed successfully!
+  CPU time: .120 seconds to compile + .268 seconds to link +
+  30.042 seconds in simulation
+
+
+
+  The test bench structure was ported from my unit test for the behavioral model of hw5_unit.
+

data/samp/pipelined_alu/Rakefile

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+load '../../tpl/launcher.rake'

data/samp/pipelined_alu/TestHw5UnitModel.rb

@@ -0,0 +1,88 @@
+=begin
+  Copyright 2006 Suraj N. Kurapati
+
+  This file is part of Ruby-VPI.
+
+  Ruby-VPI is free software; you can redistribute it and/or
+  modify it under the terms of the GNU General Public License
+  as published by the Free Software Foundation; either version 2
+  of the License, or (at your option) any later version.
+
+  Ruby-VPI is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with Ruby-VPI; if not, write to the Free Software Foundation,
+  Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+=end
+
+require 'InputGenerator'
+require 'Hw5UnitModel'
+require 'test/unit'
+require 'pp'
+
+class TestHw5UnitModel < Test::Unit::TestCase
+  NUM_VECTORS = 4000
+
+  def setup
+    @model = Hw5UnitModel.new
+    @ingen = InputGenerator.new 32
+  end
+
+  def test_reset
+    @model.reset
+    assert_same Hw5UnitModel::NOP, @model.output
+  end
+
+  def testModel
+    # generate input for module
+    inputQueue = []
+
+    NUM_VECTORS.times do |i|
+      inputQueue << Hw5UnitModel::Operation.new(Hw5UnitModel::OPERATIONS[rand(Hw5UnitModel::OPERATIONS.size)], i, @ingen.gen.abs, @ingen.gen.abs)
+    end
+
+
+    # test the module
+    outputQueue = []
+    cycle = 0
+
+    until inputQueue.length == outputQueue.length
+      if $DEBUG
+        print "\n" * 3
+        p ">> cycle #{cycle}"
+      end
+
+
+      # start a new operation
+      if cycle < inputQueue.length
+        @model.startOperation inputQueue[cycle]
+        cycle += 1
+      end
+
+
+      # simulate a clock cycle
+      @model.cycle
+
+
+      # verify the output
+      output = @model.output
+      p "output:", output if $DEBUG
+
+      unless output == Hw5UnitModel::NOP
+        assert_not_nil inputQueue.find {|op| op.tag == output.tag }, "unknown tag on result: #{output.tag}"
+        assert_equal output.compute, output.result, "incorrect result"
+
+        outputQueue << output
+      end
+
+
+      if $DEBUG
+        puts
+        pp @model
+      end
+    end
+  end
+end

data/samp/pipelined_alu/hw5_unit.v

@@ -0,0 +1,186 @@
+/*
+  Copyright 2006 Suraj N. Kurapati
+
+  This file is part of Ruby-VPI.
+
+  Ruby-VPI is free software; you can redistribute it and/or
+  modify it under the terms of the GNU General Public License
+  as published by the Free Software Foundation; either version 2
+  of the License, or (at your option) any later version.
+
+  Ruby-VPI is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with Ruby-VPI; if not, write to the Free Software Foundation,
+  Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+*/
+
+`define WIDTH 32
+`define DATABITS 7
+`define OP_NOP	0
+`define OP_ADD 1
+`define OP_SUB	2
+`define OP_MULT 3
+
+module hw5_unit(
+  input clk
+  , input reset
+
+  // inputs
+  , input [`DATABITS-1:0] in_databits
+  , input [`WIDTH-1:0] a
+  , input [`WIDTH-1:0] b
+  , input [1:0] in_op
+
+  // outputs
+  , output reg [`WIDTH-1:0] res
+  , output reg [`DATABITS-1:0] out_databits
+  , output reg [1:0] out_op
+);
+
+
+  //-------------------------------------
+  // PHASE 0: perform the ALU operations
+
+    // operation ID
+    reg [`DATABITS-1:0] in_databits_phase0;
+    reg [1:0] in_op_phase0;
+
+    always @(*) begin
+      in_databits_phase0	= in_databits;
+      in_op_phase0 = in_op;
+    end
+
+
+    // addition
+    reg [`WIDTH-1:0] add_result_phase0;
+
+    always @(*) begin
+      add_result_phase0 = a + b;
+    end
+
+
+    // subtraction
+    reg [`WIDTH-1:0] sub_result_phase0;
+
+    always @(*) begin
+      sub_result_phase0 = a - b;
+    end
+
+
+    // multiplication
+    reg [`WIDTH-1:0] mul_result_phase0;
+
+    always @(*) begin
+      mul_result_phase0 = a * b;
+    end
+
+
+    // always @(posedge clk) begin
+    // 	$display("in_databits_phase0 => %d", in_databits_phase0);
+    // 	$display("in_op_phase0 => %d", in_op_phase0);
+    // 	$display("add_result_phase0 => %d", add_result_phase0);
+    // 	$display("sub_result_phase0 => %d", sub_result_phase0);
+    // 	$display("mul_result_phase0 => %d", mul_result_phase0);
+    // end
+
+
+  //-------------------------------------
+  // PHASE 1: delay the ALU results
+
+    reg [`DATABITS-1:0] in_databits_phase1;
+    reg [1:0] in_op_phase1;
+
+    reg [`WIDTH-1:0] add_result_phase1;
+    reg [`WIDTH-1:0] sub_result_phase1;
+    reg [`WIDTH-1:0] mul_result_phase1;
+
+    always @(posedge clk) begin
+      in_databits_phase1 <= in_databits_phase0;
+      in_op_phase1 <= in_op_phase0;
+
+      add_result_phase1 <= add_result_phase0;
+      sub_result_phase1 <= sub_result_phase0;
+      mul_result_phase1 <= mul_result_phase0;
+    end
+
+    // always @(posedge clk) begin
+    // 	$display("in_databits_phase1 => %d", in_databits_phase1);
+    // 	$display("in_op_phase1 => %d", in_op_phase1);
+    // 	$display("add_result_phase1 => %d", add_result_phase1);
+    // 	$display("sub_result_phase1 => %d", sub_result_phase1);
+    // 	$display("mul_result_phase1 => %d", mul_result_phase1);
+    // end
+
+
+  //-------------------------------------
+  // PHASE 2: delay the ALU results
+
+    reg [`DATABITS-1:0] in_databits_phase2;
+    reg [1:0] in_op_phase2;
+
+    reg [`WIDTH-1:0] add_result_phase2;
+    reg [`WIDTH-1:0] sub_result_phase2;
+    reg [`WIDTH-1:0] mul_result_phase2;
+
+    always @(posedge clk) begin
+      in_databits_phase2 <= in_databits_phase1;
+      in_op_phase2 <= in_op_phase1;
+
+      add_result_phase2 <= add_result_phase1;
+      sub_result_phase2 <= sub_result_phase1;
+      mul_result_phase2 <= mul_result_phase1;
+    end
+
+    // always @(posedge clk) begin
+    // 	$display("in_databits_phase2 => %d", in_databits_phase2);
+    // 	$display("in_op_phase2 => %d", in_op_phase2);
+    // 	$display("add_result_phase2 => %d", add_result_phase2);
+    // 	$display("sub_result_phase2 => %d", sub_result_phase2);
+    // 	$display("mul_result_phase2 => %d", mul_result_phase2);
+    // end
+
+
+  //-------------------------------------
+  // PHASE 3: produce the outputs
+
+    reg [`DATABITS-1:0] out_databits_next;
+    reg [1:0] out_op_next;
+    reg [`WIDTH-1:0] res_next;
+
+    always @(*) begin
+      if (reset) begin
+        out_op_next = `OP_NOP;
+      end else begin
+        out_op_next = in_op_phase2;
+      end
+
+      out_databits_next = in_databits_phase2;
+
+      // determine res_next
+      case (in_op_phase2)
+        `OP_NOP:
+          res_next = 0;
+
+        `OP_ADD:
+          res_next = add_result_phase2;
+
+        `OP_SUB:
+          res_next = sub_result_phase2;
+
+        `OP_MULT:
+          res_next = mul_result_phase2;
+      endcase
+    end
+
+    always @(posedge clk) begin
+      res <= res_next;
+      out_op <= out_op_next;
+      out_databits <= out_databits_next;
+    end
+
+endmodule
+

data/samp/pipelined_alu/hw5_unit_bench.rb

@@ -0,0 +1,8 @@
+
+    require 'hw5_unit_spec.rb'
+
+    # service the $ruby_init() callback
+    Vpi::relay_verilog
+
+    # service the $ruby_relay() callback
+    # UnitTest will take control from here.

data/samp/pipelined_alu/hw5_unit_bench.v

@@ -0,0 +1,45 @@
+`define WIDTH 32
+`define DATABITS 7
+`define OP_NOP 0
+`define OP_ADD 1
+`define OP_SUB 2
+`define OP_MULT 3
+
+    module hw5_unit_bench;
+
+      // configuration for the design under test
+
+
+      // accessors for the design under test
+      reg clk	;
+reg reset		;
+reg [`DATABITS-1:0] in_databits	;
+reg [`WIDTH-1:0] a	;
+reg [`WIDTH-1:0] b	;
+reg [1:0] in_op		;
+wire  [`WIDTH-1:0] res	;
+wire  [`DATABITS-1:0] out_databits	;
+wire  [1:0] out_op;
+
+
+      // instantiate the design under test
+      hw5_unit  hw5_unit_bench_design (.clk(clk), .reset(reset), .in_databits(in_databits), .a(a), .b(b), .in_op(in_op), .res(res), .out_databits(out_databits), .out_op(out_op));
+
+
+      // interface to Ruby-VPI
+      initial begin
+        clk = 0;
+        $ruby_init("ruby", "-w", "-I", "../../lib", "hw5_unit_bench.rb");
+      end
+
+      // generate a 50% duty-cycle clock for the design under test
+      always begin
+        #5 clk = ~clk;
+      end
+
+      // transfer control to Ruby-VPI every clock cycle
+      always @(posedge clk) begin
+        #1 $ruby_relay();
+      end
+
+    endmodule