ruby-vpi 7.0.0
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<base target="docwin" />
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19
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<body>
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<h1 class="section-bar">Methods</h1>
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<div id="index-entries">
|
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+
<a href="classes/SWIG/TYPE_p_unsigned_int.html#M000045">[] (SWIG::TYPE_p_unsigned_int)</a><br />
|
|
24
|
+
<a href="classes/InputGenerator.html#M000028">bits (InputGenerator)</a><br />
|
|
25
|
+
<a href="classes/InputGenerator.html#M000029">bits= (InputGenerator)</a><br />
|
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26
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+
<a href="classes/FileUtils.html#M000048">collect_args (FileUtils)</a><br />
|
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27
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+
<a href="classes/Hw5UnitModel/Operation.html#M000012">compute (Hw5UnitModel::Operation)</a><br />
|
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28
|
+
<a href="classes/Hw5UnitModel/Operation.html#M000013">compute! (Hw5UnitModel::Operation)</a><br />
|
|
29
|
+
<a href="classes/Hw5UnitModel.html#M000009">cycle (Hw5UnitModel)</a><br />
|
|
30
|
+
<a href="classes/SWIG/TYPE_p_unsigned_int.html#M000046">each (SWIG::TYPE_p_unsigned_int)</a><br />
|
|
31
|
+
<a href="classes/InputGenerator.html#M000030">gen (InputGenerator)</a><br />
|
|
32
|
+
<a href="classes/InputGenerator.html#M000032">genPowerOfTwo (InputGenerator)</a><br />
|
|
33
|
+
<a href="classes/InputGenerator.html#M000031">genPrime (InputGenerator)</a><br />
|
|
34
|
+
<a href="classes/SWIG/TYPE_p_unsigned_int.html#M000042">get_value (SWIG::TYPE_p_unsigned_int)</a><br />
|
|
35
|
+
<a href="classes/SWIG/TYPE_p_unsigned_int.html#M000041">get_value_wrapper (SWIG::TYPE_p_unsigned_int)</a><br />
|
|
36
|
+
<a href="classes/RubyVPI.html#M000050">init_bench (RubyVPI)</a><br />
|
|
37
|
+
<a href="classes/Hw5UnitModel.html#M000007">initialize (Hw5UnitModel)</a><br />
|
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38
|
+
<a href="classes/RubyVPI.html#M000049">load_runner_template (RubyVPI)</a><br />
|
|
39
|
+
<a href="classes/SWIG/TYPE_p_unsigned_int.html#M000044">method_missing (SWIG::TYPE_p_unsigned_int)</a><br />
|
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40
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<a href="classes/Hw5UnitModel/Operation.html#M000011">new (Hw5UnitModel::Operation)</a><br />
|
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41
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+
<a href="classes/Counter.html#M000039">new (Counter)</a><br />
|
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42
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<a href="classes/ModuleInfo.html#M000018">new (ModuleInfo)</a><br />
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<a href="classes/OutputInfo.html#M000017">new (OutputInfo)</a><br />
|
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44
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<a href="classes/ERB.html#M000034">new (ERB)</a><br />
|
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45
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+
<a href="classes/Hw5_unit.html#M000003">new (Hw5_unit)</a><br />
|
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46
|
+
<a href="classes/InputGenerator.html#M000027">new (InputGenerator)</a><br />
|
|
47
|
+
<a href="classes/Counter.html#M000037">new (Counter)</a><br />
|
|
48
|
+
<a href="classes/Template.html#M000026">new (Template)</a><br />
|
|
49
|
+
<a href="classes/Hw5UnitModel.html#M000010">output (Hw5UnitModel)</a><br />
|
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50
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+
<a href="classes/ModuleInfo.html#M000019">parse_declarations (ModuleInfo)</a><br />
|
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51
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+
<a href="classes/SWIG/TYPE_p_unsigned_int.html#M000043">put_value (SWIG::TYPE_p_unsigned_int)</a><br />
|
|
52
|
+
<a href="classes/Hw5UnitModel.html#M000006">reset (Hw5UnitModel)</a><br />
|
|
53
|
+
<a href="classes/Hw5_unit_spec.html#M000024">reset (Hw5_unit_spec)</a><br />
|
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54
|
+
<a href="classes/Counter.html#M000040">reset! (Counter)</a><br />
|
|
55
|
+
<a href="classes/Counter.html#M000038">reset! (Counter)</a><br />
|
|
56
|
+
<a href="classes/ResettedCounterValue.html#M000014">setup (ResettedCounterValue)</a><br />
|
|
57
|
+
<a href="classes/MaximumCounterValue.html#M000035">setup (MaximumCounterValue)</a><br />
|
|
58
|
+
<a href="files/bin/generate_test_tpl/spec_rb.html#M000002">setup (bin/generate_test_tpl/spec.rb)</a><br />
|
|
59
|
+
<a href="classes/TestHw5UnitModel.html#M000020">setup (TestHw5UnitModel)</a><br />
|
|
60
|
+
<a href="classes/Hw5_unit_spec.html#M000023">setup (Hw5_unit_spec)</a><br />
|
|
61
|
+
<a href="classes/FileUtils.html#M000047">sh (FileUtils)</a><br />
|
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62
|
+
<a href="classes/CounterProto.html#M000004">simulate! (CounterProto)</a><br />
|
|
63
|
+
<a href="classes/CounterProto.html#M000005">simulate! (CounterProto)</a><br />
|
|
64
|
+
<a href="classes/Hw5UnitModel.html#M000008">startOperation (Hw5UnitModel)</a><br />
|
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65
|
+
<a href="classes/TestHw5UnitModel.html#M000022">testModel (TestHw5UnitModel)</a><br />
|
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66
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+
<a href="classes/ResettedCounterValue.html#M000016">test_increment (ResettedCounterValue)</a><br />
|
|
67
|
+
<a href="classes/MaximumCounterValue.html#M000036">test_overflow (MaximumCounterValue)</a><br />
|
|
68
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<a href="classes/Hw5_unit_spec.html#M000025">test_pipeline (Hw5_unit_spec)</a><br />
|
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69
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+
<a href="classes/TestHw5UnitModel.html#M000021">test_reset (TestHw5UnitModel)</a><br />
|
|
70
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+
<a href="classes/ResettedCounterValue.html#M000015">test_zero (ResettedCounterValue)</a><br />
|
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71
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<a href="classes/String.html#M000033">to_ruby (String)</a><br />
|
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72
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<a href="classes/RDoc.html#M000051">usage_from_file (RDoc)</a><br />
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<a href="files/bin/generate_test_rb.html#M000001">write_file (bin/generate_test.rb)</a><br />
|
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</div>
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</body>
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|
data/ref/ruby/index.html
ADDED
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<?xml version="1.0" encoding="utf-8"?>
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<!DOCTYPE html
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PUBLIC "-//W3C//DTD XHTML 1.0 Frameset//EN"
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"http://www.w3.org/TR/xhtml1/DTD/xhtml1-frameset.dtd">
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|
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<!--
|
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Ruby-VPI: Ruby interface to Verilog VPI.
|
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+
-->
|
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+
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
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<head>
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<title>Ruby-VPI: Ruby interface to Verilog VPI.</title>
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
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<frameset cols="25%,35%,45%">
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<frame src="fr_file_index.html" title="Files" name="Files" />
|
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<frame src="fr_class_index.html" name="Classes" />
|
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+
<frame src="fr_method_index.html" name="Methods" />
|
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</frameset>
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<frame src="files/gem_extconf_rb.html" name="docwin" />
|
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+
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+
</html>
|
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@@ -0,0 +1,208 @@
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body {
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font-family: Verdana,Arial,Helvetica,sans-serif;
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+
font-size: 90%;
|
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+
margin: 0;
|
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margin-left: 40px;
|
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|
+
padding: 0;
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+
background: white;
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9
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+
}
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h1,h2,h3,h4 { margin: 0; color: #efefef; background: transparent; }
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h1 { font-size: 150%; }
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h2,h3,h4 { margin-top: 1em; }
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a { background: #eef; color: #039; text-decoration: none; }
|
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16
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a:hover { background: #039; color: #eef; }
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/* Override the base stylesheet's Anchor inside a table cell */
|
|
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td > a {
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+
background: transparent;
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+
color: #039;
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text-decoration: none;
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}
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|
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25
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/* and inside a section title */
|
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.section-title > a {
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background: transparent;
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+
color: #eee;
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text-decoration: none;
|
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|
+
}
|
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|
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|
+
/* === Structural elements =================================== */
|
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|
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div#index {
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margin: 0;
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margin-left: -40px;
|
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|
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|
+
}
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div#index a {
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+
}
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|
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div#index .section-bar {
|
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+
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padding-left: 0.7em;
|
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}
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div#classHeader, div#fileHeader {
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width: auto;
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color: white;
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padding: 0.5em 1.5em 0.5em 1.5em;
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background: #057;
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}
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div#classHeader {
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}
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|
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.class-name-in-header {
|
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font-size: 180%;
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|
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|
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}
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|
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|
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|
+
}
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|
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div#description {
|
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|
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}
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|
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|
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}
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|
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}
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}
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|
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/* === Classes =================================== */
|
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|
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table.header-table {
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color: white;
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}
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}
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padding: 3px;
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}
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.section-bar {
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margin-left: -20px;
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}
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.section-title {
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background: #79a;
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color: #eee;
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padding: 3px;
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margin-top: 2em;
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border: 1px solid #999;
|
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}
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|
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.top-aligned-row { vertical-align: top }
|
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.bottom-aligned-row { vertical-align: bottom }
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+
|
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/* --- Context section classes ----------------------- */
|
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|
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.context-row { }
|
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.context-item-name { font-family: monospace; font-weight: bold; color: black; }
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.context-item-value { font-size: small; color: #448; }
|
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.context-item-desc { color: #333; padding-left: 2em; }
|
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/* --- Method classes -------------------------- */
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.method-detail {
|
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background: #efefef;
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padding: 0;
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margin-top: 0.5em;
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}
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.method-heading {
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background: #ccc;
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}
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|
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/* --- Source code sections -------------------- */
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|
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a.source-toggle { font-size: 90%; }
|
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div.method-source-code {
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margin: 1em;
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|
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|
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}
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div.method-source-code pre { color: #ffdead; overflow: hidden; }
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/* --- Ruby keyword styles --------------------- */
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.standalone-code { background: #221111; color: #ffdead; overflow: hidden; }
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|
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|
|
@@ -0,0 +1 @@
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1
|
+
load '../../tpl/launcher.rake'
|
|
@@ -0,0 +1,20 @@
|
|
|
1
|
+
/**
|
|
2
|
+
A simple up-counter with synchronous reset.
|
|
3
|
+
|
|
4
|
+
@param Size Number of bits used to represent the counter's value.
|
|
5
|
+
@param clock Increments the counter's value upon each positive edge.
|
|
6
|
+
@param reset Zeroes the counter's value when asserted.
|
|
7
|
+
@param count The counter's value.
|
|
8
|
+
*/
|
|
9
|
+
module counter #(parameter Size = 5) (
|
|
10
|
+
input clock,
|
|
11
|
+
input reset,
|
|
12
|
+
output reg [Size - 1 : 0] count
|
|
13
|
+
);
|
|
14
|
+
always @(posedge clock) begin
|
|
15
|
+
if (reset)
|
|
16
|
+
count <= 0;
|
|
17
|
+
else
|
|
18
|
+
count <= count + 1;
|
|
19
|
+
end
|
|
20
|
+
endmodule
|
|
@@ -0,0 +1,28 @@
|
|
|
1
|
+
/* This is the Verilog side of the bench. */
|
|
2
|
+
|
|
3
|
+
module counter_rspecTest_bench;
|
|
4
|
+
|
|
5
|
+
// instantiate the design under test
|
|
6
|
+
parameter Size = 5;
|
|
7
|
+
|
|
8
|
+
reg clock;
|
|
9
|
+
reg reset;
|
|
10
|
+
wire [Size - 1 : 0] count;
|
|
11
|
+
|
|
12
|
+
counter#(.Size(Size))counter_rspecTest_bench_rspecTest_design(.clock(clock), .reset(reset), .count(count));
|
|
13
|
+
|
|
14
|
+
// connect to the Ruby side of this bench
|
|
15
|
+
initial begin
|
|
16
|
+
clock = 0;
|
|
17
|
+
$ruby_init("ruby", "-w", "-rubygems", "counter_rspecTest_bench.rb", "-f", "s");
|
|
18
|
+
end
|
|
19
|
+
|
|
20
|
+
always begin
|
|
21
|
+
#5 clock = ~clock;
|
|
22
|
+
end
|
|
23
|
+
|
|
24
|
+
always @(posedge clock) begin
|
|
25
|
+
#1 $ruby_relay;
|
|
26
|
+
end
|
|
27
|
+
|
|
28
|
+
endmodule
|
|
@@ -0,0 +1,22 @@
|
|
|
1
|
+
# An interface to the design under test.
|
|
2
|
+
class Counter
|
|
3
|
+
include Vpi
|
|
4
|
+
|
|
5
|
+
Size = 5
|
|
6
|
+
|
|
7
|
+
attr_reader :clock, :reset, :count
|
|
8
|
+
|
|
9
|
+
def initialize
|
|
10
|
+
@clock = vpi_handle_by_name("counter_rspecTest_bench.clock", nil)
|
|
11
|
+
@reset = vpi_handle_by_name("counter_rspecTest_bench.reset", nil)
|
|
12
|
+
@count = vpi_handle_by_name("counter_rspecTest_bench.count", nil)
|
|
13
|
+
end
|
|
14
|
+
|
|
15
|
+
def reset!
|
|
16
|
+
@reset.hexStrVal = 'x'
|
|
17
|
+
|
|
18
|
+
@reset.intVal = 1
|
|
19
|
+
relay_verilog
|
|
20
|
+
@reset.intVal = 0
|
|
21
|
+
end
|
|
22
|
+
end
|
|
@@ -0,0 +1,28 @@
|
|
|
1
|
+
## This file builds and runs the test.
|
|
2
|
+
|
|
3
|
+
# These are source files that are to be simulated.
|
|
4
|
+
SIMULATOR_SOURCES = [
|
|
5
|
+
'counter_rspecTest_bench.v',
|
|
6
|
+
'counter.v',
|
|
7
|
+
]
|
|
8
|
+
|
|
9
|
+
# This specifies the "top module" that is to be simulated.
|
|
10
|
+
SIMULATOR_TARGET = 'counter_rspecTest_bench'
|
|
11
|
+
|
|
12
|
+
# These are command-line arguments for the simulator.
|
|
13
|
+
# They can be specified as a string or an array of strings.
|
|
14
|
+
SIMULATOR_ARGS = {
|
|
15
|
+
# GPL Cver
|
|
16
|
+
:cver => '',
|
|
17
|
+
|
|
18
|
+
# Icarus Verilog
|
|
19
|
+
:ivl => '',
|
|
20
|
+
|
|
21
|
+
# Synopsys VCS
|
|
22
|
+
:vcs => '',
|
|
23
|
+
|
|
24
|
+
# Mentor Modelsim
|
|
25
|
+
:vsim => '',
|
|
26
|
+
}
|
|
27
|
+
|
|
28
|
+
require 'ruby-vpi/runner'
|
|
@@ -0,0 +1,47 @@
|
|
|
1
|
+
## This specification verifies the design under test.
|
|
2
|
+
|
|
3
|
+
# lowest upper bound of counter's value
|
|
4
|
+
LIMIT = 2 ** Counter::Size
|
|
5
|
+
|
|
6
|
+
# maximum allowed value for a counter
|
|
7
|
+
MAX = LIMIT - 1
|
|
8
|
+
|
|
9
|
+
include Vpi
|
|
10
|
+
|
|
11
|
+
context "A resetted counter's value" do
|
|
12
|
+
setup do
|
|
13
|
+
@design = Counter.new
|
|
14
|
+
@design.reset!
|
|
15
|
+
end
|
|
16
|
+
|
|
17
|
+
specify "should be zero" do
|
|
18
|
+
@design.count.intVal.should_equal 0
|
|
19
|
+
end
|
|
20
|
+
|
|
21
|
+
specify "should increment by one count upon each rising clock edge" do
|
|
22
|
+
LIMIT.times do |i|
|
|
23
|
+
@design.count.intVal.should_equal i
|
|
24
|
+
|
|
25
|
+
# advance the clock
|
|
26
|
+
relay_verilog
|
|
27
|
+
end
|
|
28
|
+
end
|
|
29
|
+
end
|
|
30
|
+
|
|
31
|
+
context "A counter with the maximum value" do
|
|
32
|
+
setup do
|
|
33
|
+
@design = Counter.new
|
|
34
|
+
@design.reset!
|
|
35
|
+
|
|
36
|
+
# increment the counter to maximum value
|
|
37
|
+
MAX.times do relay_verilog end
|
|
38
|
+
@design.count.intVal.should_equal MAX
|
|
39
|
+
end
|
|
40
|
+
|
|
41
|
+
specify "should overflow upon increment" do
|
|
42
|
+
# increment the counter
|
|
43
|
+
relay_verilog
|
|
44
|
+
|
|
45
|
+
@design.count.intVal.should_equal 0
|
|
46
|
+
end
|
|
47
|
+
end
|
|
@@ -0,0 +1,28 @@
|
|
|
1
|
+
/* This is the Verilog side of the bench. */
|
|
2
|
+
|
|
3
|
+
module counter_unitTest_bench;
|
|
4
|
+
|
|
5
|
+
// instantiate the design under test
|
|
6
|
+
parameter Size = 5;
|
|
7
|
+
|
|
8
|
+
reg clock;
|
|
9
|
+
reg reset;
|
|
10
|
+
wire [Size - 1 : 0] count;
|
|
11
|
+
|
|
12
|
+
counter#(.Size(Size))counter_unitTest_bench_unitTest_design(.clock(clock), .reset(reset), .count(count));
|
|
13
|
+
|
|
14
|
+
// connect to the Ruby side of this bench
|
|
15
|
+
initial begin
|
|
16
|
+
clock = 0;
|
|
17
|
+
$ruby_init("ruby", "-w", "-rubygems", "counter_unitTest_bench.rb");
|
|
18
|
+
end
|
|
19
|
+
|
|
20
|
+
always begin
|
|
21
|
+
#5 clock = ~clock;
|
|
22
|
+
end
|
|
23
|
+
|
|
24
|
+
always @(posedge clock) begin
|
|
25
|
+
#1 $ruby_relay;
|
|
26
|
+
end
|
|
27
|
+
|
|
28
|
+
endmodule
|
|
@@ -0,0 +1,22 @@
|
|
|
1
|
+
# An interface to the design under test.
|
|
2
|
+
class Counter
|
|
3
|
+
include Vpi
|
|
4
|
+
|
|
5
|
+
Size = 5
|
|
6
|
+
|
|
7
|
+
attr_reader :clock, :reset, :count
|
|
8
|
+
|
|
9
|
+
def initialize
|
|
10
|
+
@clock = vpi_handle_by_name("counter_unitTest_bench.clock", nil)
|
|
11
|
+
@reset = vpi_handle_by_name("counter_unitTest_bench.reset", nil)
|
|
12
|
+
@count = vpi_handle_by_name("counter_unitTest_bench.count", nil)
|
|
13
|
+
end
|
|
14
|
+
|
|
15
|
+
def reset!
|
|
16
|
+
@reset.hexStrVal = 'x'
|
|
17
|
+
|
|
18
|
+
@reset.intVal = 1
|
|
19
|
+
relay_verilog
|
|
20
|
+
@reset.intVal = 0
|
|
21
|
+
end
|
|
22
|
+
end
|
|
@@ -0,0 +1,28 @@
|
|
|
1
|
+
## This file builds and runs the test.
|
|
2
|
+
|
|
3
|
+
# These are source files that are to be simulated.
|
|
4
|
+
SIMULATOR_SOURCES = [
|
|
5
|
+
'counter_unitTest_bench.v',
|
|
6
|
+
'counter.v',
|
|
7
|
+
]
|
|
8
|
+
|
|
9
|
+
# This specifies the "top module" that is to be simulated.
|
|
10
|
+
SIMULATOR_TARGET = 'counter_unitTest_bench'
|
|
11
|
+
|
|
12
|
+
# These are command-line arguments for the simulator.
|
|
13
|
+
# They can be specified as a string or an array of strings.
|
|
14
|
+
SIMULATOR_ARGS = {
|
|
15
|
+
# GPL Cver
|
|
16
|
+
:cver => '',
|
|
17
|
+
|
|
18
|
+
# Icarus Verilog
|
|
19
|
+
:ivl => '',
|
|
20
|
+
|
|
21
|
+
# Synopsys VCS
|
|
22
|
+
:vcs => '',
|
|
23
|
+
|
|
24
|
+
# Mentor Modelsim
|
|
25
|
+
:vsim => '',
|
|
26
|
+
}
|
|
27
|
+
|
|
28
|
+
require 'ruby-vpi/runner'
|
|
@@ -0,0 +1,49 @@
|
|
|
1
|
+
## This specification verifies the design under test.
|
|
2
|
+
|
|
3
|
+
# lowest upper bound of counter's value
|
|
4
|
+
LIMIT = 2 ** Counter::Size
|
|
5
|
+
|
|
6
|
+
# maximum allowed value for a counter
|
|
7
|
+
MAX = LIMIT - 1
|
|
8
|
+
|
|
9
|
+
class ResettedCounterValue < Test::Unit::TestCase
|
|
10
|
+
include Vpi
|
|
11
|
+
|
|
12
|
+
def setup
|
|
13
|
+
@design = Counter.new
|
|
14
|
+
@design.reset!
|
|
15
|
+
end
|
|
16
|
+
|
|
17
|
+
def test_zero
|
|
18
|
+
assert_equal 0, @design.count.intVal
|
|
19
|
+
end
|
|
20
|
+
|
|
21
|
+
def test_increment
|
|
22
|
+
LIMIT.times do |i|
|
|
23
|
+
assert_equal i, @design.count.intVal
|
|
24
|
+
|
|
25
|
+
# advance the clock
|
|
26
|
+
relay_verilog
|
|
27
|
+
end
|
|
28
|
+
end
|
|
29
|
+
end
|
|
30
|
+
|
|
31
|
+
class MaximumCounterValue < Test::Unit::TestCase
|
|
32
|
+
include Vpi
|
|
33
|
+
|
|
34
|
+
def setup
|
|
35
|
+
@design = Counter.new
|
|
36
|
+
@design.reset!
|
|
37
|
+
|
|
38
|
+
# increment the counter to maximum value
|
|
39
|
+
MAX.times do relay_verilog end
|
|
40
|
+
assert_equal MAX, @design.count.intVal
|
|
41
|
+
end
|
|
42
|
+
|
|
43
|
+
def test_overflow
|
|
44
|
+
# increment the counter
|
|
45
|
+
relay_verilog
|
|
46
|
+
|
|
47
|
+
assert_equal 0, @design.count.intVal
|
|
48
|
+
end
|
|
49
|
+
end
|