rggen 0.4.4 → 0.5.1

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE.txt

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2015 Taichi Ishitani
+Copyright (c) 2015-2017 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -3,12 +3,13 @@
 [![Dependency Status](https://dependencyci.com/github/taichi-ishitani/rggen/badge)](https://dependencyci.com/github/taichi-ishitani/rggen)
 [![Code Climate](https://codeclimate.com/github/taichi-ishitani/rggen/badges/gpa.svg)](https://codeclimate.com/github/taichi-ishitani/rggen)
 [![Test Coverage](https://codeclimate.com/github/taichi-ishitani/rggen/badges/coverage.svg)](https://codeclimate.com/github/taichi-ishitani/rggen/coverage)
+[![Coverity Scan](https://scan.coverity.com/projects/10804/badge.svg)](https://scan.coverity.com/projects/taichi-ishitani-rggen)
 [![Join the chat at https://gitter.im/taichi-ishitani/rggen](https://badges.gitter.im/taichi-ishitani/rggen.svg)](https://gitter.im/taichi-ishitani/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
 
 # RgGen
 
 RgGen is a code generation tool for SoC designers.
-It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
+It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, C header file, from its register map document.
 Also RgGen is customizable so you can build your specific generate tool.
 
 ## Ruby
@@ -54,5 +55,5 @@ Bug reports and pull requests are welcome on GitHub at https://github.com/taichi
 
 ## License
 
-Copyright © 2015-2016 Taichi Ishitani.
+Copyright © 2015-2017 Taichi Ishitani.
 RgGen is available as open source under the terms of [the MIT License](LICENSE.txt).

data/c/rggen.h

@@ -0,0 +1,17 @@
+#ifndef RGGEN_H
+#define RGGEN_H
+
+#include <stdint.h>
+
+typedef uint8_t   rggen_uint8;
+typedef uint16_t  rggen_uint16;
+typedef uint32_t  rggen_uint32;
+typedef uint64_t  rggen_uint64;
+
+#define RGGEN_EXTERNAL_REGISTERS(SIZE, TYPE) \
+union { \
+  rggen_uint8 array[SIZE]; \
+  TYPE        body; \
+}
+
+#endif

data/lib/rggen.rb

@@ -1,12 +1,12 @@
 module RgGen
-  RGGEN_HOME  = File.realpath(File.join(__dir__, '..'))
-
   require 'forwardable'
-  require 'baby_erubis'
-  require 'fileutils'
+  require 'singleton'
+  require 'pathname'
   require 'optparse'
+  require 'baby_erubis'
 
   require_relative 'rggen/version'
+  require_relative 'rggen/rggen_home'
 
   require_relative 'rggen/exceptions'
 
@@ -31,18 +31,9 @@ module RgGen
   require_relative 'rggen/input_base/component_factory'
   require_relative 'rggen/input_base/item_factory'
 
-  require_relative 'rggen/output_base/line'
-  require_relative 'rggen/output_base/code_block'
-  require_relative 'rggen/output_base/code_utility'
-  require_relative 'rggen/output_base/template_utility'
-  require_relative 'rggen/output_base/verilog_utility/identifier'
-  require_relative 'rggen/output_base/verilog_utility/declaration'
-  require_relative 'rggen/output_base/verilog_utility/structure_definition'
-  require_relative 'rggen/output_base/verilog_utility/module_definition'
-  require_relative 'rggen/output_base/verilog_utility/package_definition'
-  require_relative 'rggen/output_base/verilog_utility/class_definition'
-  require_relative 'rggen/output_base/verilog_utility/subroutine_definition'
-  require_relative 'rggen/output_base/verilog_utility'
+  require_relative 'rggen/output_base/code_generator'
+  require_relative 'rggen/output_base/template_engine'
+  require_relative 'rggen/output_base/file_writer'
   require_relative 'rggen/output_base/component'
   require_relative 'rggen/output_base/item'
   require_relative 'rggen/output_base/component_factory'

data/lib/rggen/base/item_factory.rb

@@ -1,6 +1,8 @@
 module RgGen
   module Base
     class ItemFactory
+      extend InternalStruct
+
       attr_writer :target_items
       attr_writer :target_item
 

data/lib/rggen/builtins.rb

@@ -13,39 +13,41 @@ require_relative 'builtins/bit_field/initial_value'
 require_relative 'builtins/bit_field/name'
 require_relative 'builtins/bit_field/reference'
 require_relative 'builtins/bit_field/type'
-require_relative 'builtins/bit_field/rw'
-require_relative 'builtins/bit_field/rwl_rwe'
-require_relative 'builtins/bit_field/ro'
-require_relative 'builtins/bit_field/w0c_w1c'
-require_relative 'builtins/bit_field/w0s_w1s'
-require_relative 'builtins/bit_field/wo'
-require_relative 'builtins/bit_field/reserved'
+require_relative 'builtins/bit_field/types/rw'
+require_relative 'builtins/bit_field/types/rwl_rwe'
+require_relative 'builtins/bit_field/types/ro'
+require_relative 'builtins/bit_field/types/w0c_w1c'
+require_relative 'builtins/bit_field/types/w0s_w1s'
+require_relative 'builtins/bit_field/types/wo'
+require_relative 'builtins/bit_field/types/reserved'
 
-require_relative 'builtins/register/accessibility'
 require_relative 'builtins/register/address_decoder'
 require_relative 'builtins/register/array'
 require_relative 'builtins/register/bus_exporter'
 require_relative 'builtins/register/constructor'
-require_relative 'builtins/register/external'
 require_relative 'builtins/register/field_model_creator'
+require_relative 'builtins/register/indirect_index_configurator'
 require_relative 'builtins/register/offset_address'
 require_relative 'builtins/register/name'
 require_relative 'builtins/register/read_data'
 require_relative 'builtins/register/reg_model'
-require_relative 'builtins/register/shadow'
-require_relative 'builtins/register/shadow_index_configurator'
 require_relative 'builtins/register/sub_block_model'
+require_relative 'builtins/register/type'
+require_relative 'builtins/register/types/external'
+require_relative 'builtins/register/types/indirect'
 require_relative 'builtins/register/uniqueness_validator'
 
+require_relative 'builtins/register_block/address_struct'
 require_relative 'builtins/register_block/base_address'
 require_relative 'builtins/register_block/block_model'
 require_relative 'builtins/register_block/byte_size'
+require_relative 'builtins/register_block/c_header_file'
 require_relative 'builtins/register_block/clock_reset'
 require_relative 'builtins/register_block/constructor'
 require_relative 'builtins/register_block/default_map_creator'
 require_relative 'builtins/register_block/host_if'
-require_relative 'builtins/register_block/apb'
-require_relative 'builtins/register_block/axi4lite'
+require_relative 'builtins/register_block/host_ifs/apb'
+require_relative 'builtins/register_block/host_ifs/axi4lite'
 require_relative 'builtins/register_block/irq_controller'
 require_relative 'builtins/register_block/name'
 require_relative 'builtins/register_block/ral_package'

data/lib/rggen/builtins/register/address_decoder.erb

@@ -1,12 +1,12 @@
 rggen_address_decoder #(
-  .ADDRESS_WIDTH      (<%= local_address_width - address_lsb %>),
-  .START_ADDRESS      (<%= start_address%>),
-  .END_ADDRESS        (<%= end_address %>),
-  .USE_SHADOW_INDEX   (<%= use_shadow_index %>),
-  .SHADOW_INDEX_WIDTH (<%= shadow_index_width %>),
-  .SHADOW_INDEX_VALUE (<%= shadow_index_value %>)
+  .ADDRESS_WIDTH        (<%= local_address_width - address_lsb %>),
+  .START_ADDRESS        (<%= start_address%>),
+  .END_ADDRESS          (<%= end_address %>),
+  .INDIRECT_REGISTER    (<%= indirect_register %>),
+  .INDIRECT_INDEX_WIDTH (<%= indirect_index_width %>),
+  .INDIRECT_INDEX_VALUE (<%= indirect_index_value %>)
 ) u_<%= register.name%>_address_decoder (
-  .i_address      (<%= register_block.host_if.address[local_address_width - 1, address_lsb] %>),
-  .i_shadow_index (<%= (shadow? && shadow_index[loop_variables]) || shadow_index_value %>),
-  .o_select       (<%= register_block.register_select[register.index] %>)
+  .i_address        (<%= register_block.host_if.address[local_address_width - 1, address_lsb] %>),
+  .i_indirect_index (<%= (type?(:indirect) && indirect_index[loop_variables]) || indirect_index_value %>),
+  .o_select         (<%= register_block.register_select[register.index] %>)
 );

data/lib/rggen/builtins/register/address_decoder.rb

@@ -1,21 +1,21 @@
 simple_item :register, :address_decoder do
   rtl do
     build do
-      next unless register.shadow?
-      logic :shadow_index,
-            name:       "#{register.name}_shadow_index",
-            width:      shadow_index_width,
+      next unless type?(:indirect)
+      logic :indirect_index,
+            name:       "#{register.name}_indirect_index",
+            width:      indirect_index_width,
             dimensions: register.dimensions
     end
 
     generate_code :module_item do |buffer|
-      buffer << shadow_index_assignment << nl if shadow?
+      buffer << indirect_index_assignment << nl if type?(:indirect)
       buffer << process_template
     end
 
     delegate [:local_address_width] => :register_block
-    delegate [:array?, :shadow?, :multiple?] => :register
-    delegate [:shadow_indexes, :loop_variables] => :register
+    delegate [:array?, :type?, :multiple?] => :register
+    delegate [:indexes, :loop_variables] => :register
 
     def address_lsb
       Math.clog2(configuration.byte_width)
@@ -40,41 +40,41 @@ simple_item :register, :address_decoder do
       (array? && multiple? && "#{base} + #{register.local_index}") || base
     end
 
-    def shadow_index_assignment
+    def indirect_index_assignment
       assign(
-        shadow_index[register.loop_variables],
-        concat(shadow_index_fields.map(&:value))
+        indirect_index[register.loop_variables],
+        concat(indirect_index_fields.map(&:value))
       )
     end
 
-    def use_shadow_index
-      (shadow? && 1) || 0
+    def indirect_register
+      (type?(:indirect) && 1) || 0
     end
 
-    def shadow_index_width
-      return 1 unless shadow?
-      shadow_index_fields.sum(0, &:width)
+    def indirect_index_width
+      return 1 unless type?(:indirect)
+      indirect_index_fields.sum(0, &:width)
     end
 
-    def shadow_index_value
-      return hex(0, 1) unless shadow?
-      concat(shadow_index_values)
+    def indirect_index_value
+      return hex(0, 1) unless type?(:indirect)
+      concat(indirect_index_values)
     end
 
-    def shadow_index_fields
-      @shadow_index_fields ||= shadow_indexes.map do |index|
+    def indirect_index_fields
+      @indirect_index_fields ||= indexes.map do |index|
         register_block.bit_fields.find_by(name: index.name)
       end
     end
 
-    def shadow_index_values
+    def indirect_index_values
       variables = loop_variables
-      shadow_indexes.map.with_index do |index, i|
+      indexes.map.with_index do |index, i|
         if index.value
-          hex(index.value, shadow_index_fields[i].width)
+          hex(index.value, indirect_index_fields[i].width)
         else
           loop_variable = variables.shift
-          loop_variable[shadow_index_fields[i].width - 1, 0]
+          loop_variable[indirect_index_fields[i].width - 1, 0]
         end
       end
     end

data/lib/rggen/builtins/register/array.rb

@@ -16,16 +16,6 @@ simple_item :register, :array do
       end
     end
 
-    validate do
-      case
-      when multi_dimensions_array_with_real_register?
-        error 'not use multi dimensions array with real register'
-      when mismatch_with_own_byte_size?
-        error "mismatches with own byte size(#{register.byte_size}):" \
-              " #{dimensions}"
-      end
-    end
-
     def parse_array_dimensions(cell)
       case
       when cell.nil? || cell.empty?
@@ -36,18 +26,6 @@ simple_item :register, :array do
         error "invalid value for array dimension: #{cell.inspect}"
       end
     end
-
-    def multi_dimensions_array_with_real_register?
-      return false unless array?
-      return false if register.shadow?
-      register.multiple? && dimensions.size > 1
-    end
-
-    def mismatch_with_own_byte_size?
-      return false unless array?
-      return false if register.shadow?
-      register.byte_size != dimensions.first * configuration.byte_width
-    end
   end
 
   rtl do

data/lib/rggen/builtins/register/bus_exporter.rb

@@ -4,10 +4,10 @@ simple_item :register, :bus_exporter do
       :data_width, :byte_width
     ] => :configuration
     delegate [
-      :name, :byte_size, :external?, :index, :external_index
+      :name, :byte_size, :index, :external_index
     ] => :register
 
-    available? { external? }
+    available? { register.type?(:external) }
 
     build do
       output :valid     , name: "o_#{name}_valid"     , width: 1
@@ -40,5 +40,13 @@ simple_item :register, :bus_exporter do
     def start_address
       hex(register.start_address, register_block.local_address_width)
     end
+
+    def external_index
+      external_registers.index(&register.method(:equal?))
+    end
+
+    def external_registers
+      register_block.registers.select { |r| r.type?(:external) }
+    end
   end
 end

data/lib/rggen/builtins/register/indirect_index_configurator.rb

@@ -0,0 +1,54 @@
+simple_item :register, :indirect_index_configurator do
+  ral do
+    available? { register.type?(:indirect) }
+
+    generate_code :reg_model_item do
+      function_definition :configure_indirect_indexes do |f|
+        f.return_type :void
+        f.body { |code| function_body(code) }
+      end
+    end
+
+    def function_body(code)
+      register.indexes.each do |index|
+        code << subroutine_call(:set_indirect_index, arguments(index))
+        code << semicolon
+        code << nl
+      end
+    end
+
+    def arguments(indirect_index)
+      [
+        parent_name(indirect_index),
+        index_name(indirect_index),
+        index_value(indirect_index)
+      ]
+    end
+
+    def parent_name(indirect_index)
+      parent_register = fild_parent_register(indirect_index.name)
+      string(parent_register.name)
+    end
+
+    def fild_parent_register(index_name)
+      register_block.bit_fields.find_by(name: index_name).register
+    end
+
+    def index_name(indirect_index)
+      string(indirect_index.name)
+    end
+
+    def index_value(indirect_index)
+      if indirect_index.value
+        indirect_index.value
+      else
+        "indexes[#{array_index}]"
+      end
+    end
+
+    def array_index
+      @array_index  ||= -1
+      @array_index  += 1
+    end
+  end
+end

data/lib/rggen/builtins/register/offset_address.rb

@@ -16,16 +16,9 @@ simple_item :register, :offset_address do
 
     build do |cell|
       @start_address, @end_address  = parse_address(cell)
-      case
-      when @start_address >= @end_address
-        error "start address is equal to or greater than end address: #{cell}"
-      when unaligned_address?
-        error 'not aligned with data width' \
-              "(#{configuration.data_width}): #{cell}"
-      when @end_address > max_address
-        error 'exceeds the maximum offset address' \
-              "(0x#{max_address.to_s(16)}): #{cell}"
-      end
+      check_start_end_adderss_relation(cell)
+      check_address_align(cell)
+      check_address_range(cell)
     end
 
     def parse_address(cell)
@@ -41,11 +34,24 @@ simple_item :register, :offset_address do
       end
     end
 
-    def unaligned_address?
-      byte_width  = configuration.byte_width
-      return true unless (@start_address + 0).multiple?(byte_width)
-      return true unless (@end_address   + 1).multiple?(byte_width)
-      false
+    def check_start_end_adderss_relation(cell)
+      return if start_address < end_address
+      return if [configuration.byte_width, byte_size].all? { |v| v == 1}
+      error "start address is equal to or greater than end address: #{cell}"
+    end
+
+    def check_address_align(cell)
+      return if [start_address, end_address + 1].all? do |a|
+        a.multiple?(configuration.byte_width)
+      end
+      error 'not aligned with data width' \
+            "(#{configuration.data_width}): #{cell}"
+    end
+
+    def check_address_range(cell)
+      return if end_address <= max_address
+      error 'exceeds the maximum offset address' \
+            "(0x#{max_address.to_s(16)}): #{cell}"
     end
 
     def max_address