rggen 0.4.4 → 0.5.1
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- checksums.yaml +4 -4
- data/LICENSE.txt +1 -1
- data/README.md +3 -2
- data/c/rggen.h +17 -0
- data/lib/rggen.rb +7 -16
- data/lib/rggen/base/item_factory.rb +2 -0
- data/lib/rggen/builtins.rb +15 -13
- data/lib/rggen/builtins/bit_field/{reserved.rb → types/reserved.rb} +0 -0
- data/lib/rggen/builtins/bit_field/{ro.erb → types/ro.erb} +0 -0
- data/lib/rggen/builtins/bit_field/{ro.rb → types/ro.rb} +0 -0
- data/lib/rggen/builtins/bit_field/{rw.erb → types/rw.erb} +0 -0
- data/lib/rggen/builtins/bit_field/{rw.rb → types/rw.rb} +0 -0
- data/lib/rggen/builtins/bit_field/{rwl_rwe.erb → types/rwl_rwe.erb} +0 -0
- data/lib/rggen/builtins/bit_field/{rwl_rwe.rb → types/rwl_rwe.rb} +0 -0
- data/lib/rggen/builtins/bit_field/{w0c_w1c.erb → types/w0c_w1c.erb} +0 -0
- data/lib/rggen/builtins/bit_field/{w0c_w1c.rb → types/w0c_w1c.rb} +0 -0
- data/lib/rggen/builtins/bit_field/{w0s_w1s.erb → types/w0s_w1s.erb} +0 -0
- data/lib/rggen/builtins/bit_field/{w0s_w1s.rb → types/w0s_w1s.rb} +0 -0
- data/lib/rggen/builtins/bit_field/{wo.rb → types/wo.rb} +0 -0
- data/lib/rggen/builtins/register/address_decoder.erb +9 -9
- data/lib/rggen/builtins/register/address_decoder.rb +24 -24
- data/lib/rggen/builtins/register/array.rb +0 -22
- data/lib/rggen/builtins/register/bus_exporter.rb +10 -2
- data/lib/rggen/builtins/register/indirect_index_configurator.rb +54 -0
- data/lib/rggen/builtins/register/offset_address.rb +21 -15
- data/lib/rggen/builtins/register/read_data.rb +1 -1
- data/lib/rggen/builtins/register/reg_model.rb +5 -5
- data/lib/rggen/builtins/register/sub_block_model.rb +1 -1
- data/lib/rggen/builtins/register/type.rb +207 -0
- data/lib/rggen/builtins/register/types/external.rb +15 -0
- data/lib/rggen/builtins/register/types/indirect.rb +134 -0
- data/lib/rggen/builtins/register/uniqueness_validator.rb +10 -7
- data/lib/rggen/builtins/register_block/address_struct.rb +56 -0
- data/lib/rggen/builtins/register_block/c_header_file.rb +15 -0
- data/lib/rggen/builtins/register_block/{apb.erb → host_ifs/apb.erb} +0 -0
- data/lib/rggen/builtins/register_block/{apb.rb → host_ifs/apb.rb} +0 -0
- data/lib/rggen/builtins/register_block/{axi4lite.erb → host_ifs/axi4lite.erb} +0 -0
- data/lib/rggen/builtins/register_block/{axi4lite.rb → host_ifs/axi4lite.rb} +0 -0
- data/lib/rggen/builtins/register_block/ral_package.rb +6 -1
- data/lib/rggen/builtins/register_block/response_mux.rb +2 -2
- data/lib/rggen/builtins/register_block/top_module.rb +5 -1
- data/lib/rggen/core_components.rb +25 -0
- data/lib/rggen/core_components/c_header/item.rb +8 -0
- data/lib/rggen/core_components/c_header/setup.rb +19 -0
- data/lib/rggen/core_components/c_utility.rb +19 -0
- data/lib/rggen/core_components/c_utility/data_structure_definition.rb +62 -0
- data/lib/rggen/core_components/c_utility/source_file.rb +10 -0
- data/lib/rggen/core_components/c_utility/variable_declaration.rb +35 -0
- data/lib/rggen/core_components/code_utility.rb +56 -0
- data/lib/rggen/{output_base → core_components/code_utility}/code_block.rb +1 -1
- data/lib/rggen/{output_base → core_components/code_utility}/line.rb +1 -1
- data/lib/rggen/core_components/code_utility/source_file.rb +97 -0
- data/lib/rggen/core_components/erb_engine.rb +15 -0
- data/lib/rggen/core_components/ral/item.rb +2 -1
- data/lib/rggen/core_components/register_map/generic_map.rb +3 -1
- data/lib/rggen/core_components/rtl/item.rb +2 -1
- data/lib/rggen/core_components/verilog_utility.rb +69 -0
- data/lib/rggen/core_components/verilog_utility/class_definition.rb +56 -0
- data/lib/rggen/core_components/verilog_utility/declaration.rb +66 -0
- data/lib/rggen/core_components/verilog_utility/identifier.rb +27 -0
- data/lib/rggen/core_components/verilog_utility/module_definition.rb +71 -0
- data/lib/rggen/core_components/verilog_utility/package_definition.rb +65 -0
- data/lib/rggen/core_components/verilog_utility/source_file.rb +10 -0
- data/lib/rggen/core_components/verilog_utility/structure_definition.rb +50 -0
- data/lib/rggen/core_components/verilog_utility/subroutine_definition.rb +41 -0
- data/lib/rggen/core_extensions/facets.rb +5 -0
- data/lib/rggen/generator.rb +19 -5
- data/lib/rggen/input_base/item.rb +6 -6
- data/lib/rggen/output_base/code_generator.rb +36 -0
- data/lib/rggen/output_base/component.rb +27 -41
- data/lib/rggen/output_base/file_writer.rb +36 -0
- data/lib/rggen/output_base/item.rb +34 -100
- data/lib/rggen/output_base/template_engine.rb +24 -0
- data/lib/rggen/rggen_home.rb +3 -0
- data/lib/rggen/version.rb +2 -2
- data/ral/rggen_ral_block.svh +1 -1
- data/ral/rggen_ral_indirect_reg.svh +193 -0
- data/ral/rggen_ral_map.svh +20 -20
- data/ral/rggen_ral_pkg.sv +1 -1
- data/rtl/register/rggen_address_decoder.sv +14 -14
- data/sample/sample.csv +21 -22
- data/sample/sample.xls +0 -0
- data/sample/sample.xlsx +0 -0
- data/sample/sample_0.h +17 -0
- data/sample/sample_0.sv +92 -92
- data/sample/sample_0_ral_pkg.sv +8 -5
- data/sample/sample_1.h +9 -0
- data/sample/sample_1.sv +27 -27
- data/sample/sample_1_ral_pkg.sv +3 -0
- data/sample/sample_setup.rb +4 -2
- data/setup/default.rb +4 -2
- metadata +53 -36
- data/lib/rggen/builtins/register/accessibility.rb +0 -23
- data/lib/rggen/builtins/register/external.rb +0 -42
- data/lib/rggen/builtins/register/shadow.rb +0 -130
- data/lib/rggen/builtins/register/shadow_index_configurator.rb +0 -56
- data/lib/rggen/output_base/code_utility.rb +0 -50
- data/lib/rggen/output_base/template_utility.rb +0 -29
- data/lib/rggen/output_base/verilog_utility.rb +0 -69
- data/lib/rggen/output_base/verilog_utility/class_definition.rb +0 -58
- data/lib/rggen/output_base/verilog_utility/declaration.rb +0 -68
- data/lib/rggen/output_base/verilog_utility/identifier.rb +0 -29
- data/lib/rggen/output_base/verilog_utility/module_definition.rb +0 -73
- data/lib/rggen/output_base/verilog_utility/package_definition.rb +0 -67
- data/lib/rggen/output_base/verilog_utility/structure_definition.rb +0 -52
- data/lib/rggen/output_base/verilog_utility/subroutine_definition.rb +0 -43
- data/ral/rggen_ral_shadow_reg.svh +0 -193
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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1
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---
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SHA1:
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-
metadata.gz:
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-
data.tar.gz:
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3
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+
metadata.gz: b5ce1005a53b9e917a5b5e00783ac95122b51d9c
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4
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+
data.tar.gz: 2cd68011eb9acbf244743a660311cd973a249b53
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5
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SHA512:
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-
metadata.gz:
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-
data.tar.gz:
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+
metadata.gz: b16b2bcae8107eadff8fe24ac66c335eaeae10c514233e25e6756da8629879bc7bc1088658cd612ddd8c77f6b4a91d06ec27dadb126e63461f489a4be59dd1f2
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7
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+
data.tar.gz: b37b9f7952ba07addf76a5cff942e75353d883a58c8a754e0d09134ebe91aa2ecd5982ab51a571a23865583a1f1d34205185e9fa43dd8a7b173873db55bc36a7
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data/LICENSE.txt
CHANGED
data/README.md
CHANGED
@@ -3,12 +3,13 @@
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[![Dependency Status](https://dependencyci.com/github/taichi-ishitani/rggen/badge)](https://dependencyci.com/github/taichi-ishitani/rggen)
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[![Code Climate](https://codeclimate.com/github/taichi-ishitani/rggen/badges/gpa.svg)](https://codeclimate.com/github/taichi-ishitani/rggen)
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[![Test Coverage](https://codeclimate.com/github/taichi-ishitani/rggen/badges/coverage.svg)](https://codeclimate.com/github/taichi-ishitani/rggen/coverage)
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+
[![Coverity Scan](https://scan.coverity.com/projects/10804/badge.svg)](https://scan.coverity.com/projects/taichi-ishitani-rggen)
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[![Join the chat at https://gitter.im/taichi-ishitani/rggen](https://badges.gitter.im/taichi-ishitani/rggen.svg)](https://gitter.im/taichi-ishitani/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
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# RgGen
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RgGen is a code generation tool for SoC designers.
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-
It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
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It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, C header file, from its register map document.
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Also RgGen is customizable so you can build your specific generate tool.
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## Ruby
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@@ -54,5 +55,5 @@ Bug reports and pull requests are welcome on GitHub at https://github.com/taichi
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## License
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Copyright © 2015-
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+
Copyright © 2015-2017 Taichi Ishitani.
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RgGen is available as open source under the terms of [the MIT License](LICENSE.txt).
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data/c/rggen.h
ADDED
@@ -0,0 +1,17 @@
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1
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+
#ifndef RGGEN_H
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#define RGGEN_H
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+
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#include <stdint.h>
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+
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typedef uint8_t rggen_uint8;
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7
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+
typedef uint16_t rggen_uint16;
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8
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+
typedef uint32_t rggen_uint32;
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9
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+
typedef uint64_t rggen_uint64;
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+
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#define RGGEN_EXTERNAL_REGISTERS(SIZE, TYPE) \
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union { \
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rggen_uint8 array[SIZE]; \
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TYPE body; \
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}
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+
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#endif
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data/lib/rggen.rb
CHANGED
@@ -1,12 +1,12 @@
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1
1
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module RgGen
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-
RGGEN_HOME = File.realpath(File.join(__dir__, '..'))
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-
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require 'forwardable'
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require '
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require '
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+
require 'singleton'
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require 'pathname'
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require 'optparse'
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require 'baby_erubis'
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7
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require_relative 'rggen/version'
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9
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+
require_relative 'rggen/rggen_home'
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require_relative 'rggen/exceptions'
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12
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@@ -31,18 +31,9 @@ module RgGen
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require_relative 'rggen/input_base/component_factory'
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require_relative 'rggen/input_base/item_factory'
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-
require_relative 'rggen/output_base/
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require_relative 'rggen/output_base/
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require_relative 'rggen/output_base/
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require_relative 'rggen/output_base/template_utility'
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-
require_relative 'rggen/output_base/verilog_utility/identifier'
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-
require_relative 'rggen/output_base/verilog_utility/declaration'
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require_relative 'rggen/output_base/verilog_utility/structure_definition'
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require_relative 'rggen/output_base/verilog_utility/module_definition'
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require_relative 'rggen/output_base/verilog_utility/package_definition'
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require_relative 'rggen/output_base/verilog_utility/class_definition'
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require_relative 'rggen/output_base/verilog_utility/subroutine_definition'
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-
require_relative 'rggen/output_base/verilog_utility'
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require_relative 'rggen/output_base/code_generator'
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require_relative 'rggen/output_base/template_engine'
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require_relative 'rggen/output_base/file_writer'
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require_relative 'rggen/output_base/component'
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require_relative 'rggen/output_base/item'
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require_relative 'rggen/output_base/component_factory'
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data/lib/rggen/builtins.rb
CHANGED
@@ -13,39 +13,41 @@ require_relative 'builtins/bit_field/initial_value'
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require_relative 'builtins/bit_field/name'
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require_relative 'builtins/bit_field/reference'
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require_relative 'builtins/bit_field/type'
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require_relative 'builtins/bit_field/rw'
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require_relative 'builtins/bit_field/rwl_rwe'
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require_relative 'builtins/bit_field/ro'
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require_relative 'builtins/bit_field/w0c_w1c'
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require_relative 'builtins/bit_field/w0s_w1s'
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require_relative 'builtins/bit_field/wo'
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require_relative 'builtins/bit_field/reserved'
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require_relative 'builtins/bit_field/types/rw'
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require_relative 'builtins/bit_field/types/rwl_rwe'
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require_relative 'builtins/bit_field/types/ro'
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require_relative 'builtins/bit_field/types/w0c_w1c'
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require_relative 'builtins/bit_field/types/w0s_w1s'
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require_relative 'builtins/bit_field/types/wo'
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require_relative 'builtins/bit_field/types/reserved'
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require_relative 'builtins/register/accessibility'
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require_relative 'builtins/register/address_decoder'
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require_relative 'builtins/register/array'
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require_relative 'builtins/register/bus_exporter'
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require_relative 'builtins/register/constructor'
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-
require_relative 'builtins/register/external'
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require_relative 'builtins/register/field_model_creator'
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require_relative 'builtins/register/indirect_index_configurator'
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require_relative 'builtins/register/offset_address'
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require_relative 'builtins/register/name'
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require_relative 'builtins/register/read_data'
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require_relative 'builtins/register/reg_model'
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require_relative 'builtins/register/shadow'
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require_relative 'builtins/register/shadow_index_configurator'
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require_relative 'builtins/register/sub_block_model'
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+
require_relative 'builtins/register/type'
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require_relative 'builtins/register/types/external'
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require_relative 'builtins/register/types/indirect'
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require_relative 'builtins/register/uniqueness_validator'
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require_relative 'builtins/register_block/address_struct'
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require_relative 'builtins/register_block/base_address'
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require_relative 'builtins/register_block/block_model'
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require_relative 'builtins/register_block/byte_size'
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+
require_relative 'builtins/register_block/c_header_file'
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require_relative 'builtins/register_block/clock_reset'
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require_relative 'builtins/register_block/constructor'
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require_relative 'builtins/register_block/default_map_creator'
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require_relative 'builtins/register_block/host_if'
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require_relative 'builtins/register_block/apb'
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-
require_relative 'builtins/register_block/axi4lite'
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+
require_relative 'builtins/register_block/host_ifs/apb'
|
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require_relative 'builtins/register_block/host_ifs/axi4lite'
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require_relative 'builtins/register_block/irq_controller'
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require_relative 'builtins/register_block/name'
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require_relative 'builtins/register_block/ral_package'
|
File without changes
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File without changes
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File without changes
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File without changes
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File without changes
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File without changes
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File without changes
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File without changes
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File without changes
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File without changes
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File without changes
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File without changes
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@@ -1,12 +1,12 @@
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rggen_address_decoder #(
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-
.ADDRESS_WIDTH
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.START_ADDRESS
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.END_ADDRESS
|
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.
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.
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.
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2
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.ADDRESS_WIDTH (<%= local_address_width - address_lsb %>),
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.START_ADDRESS (<%= start_address%>),
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.END_ADDRESS (<%= end_address %>),
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.INDIRECT_REGISTER (<%= indirect_register %>),
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.INDIRECT_INDEX_WIDTH (<%= indirect_index_width %>),
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.INDIRECT_INDEX_VALUE (<%= indirect_index_value %>)
|
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8
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) u_<%= register.name%>_address_decoder (
|
9
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.i_address
|
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.
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.o_select
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+
.i_address (<%= register_block.host_if.address[local_address_width - 1, address_lsb] %>),
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.i_indirect_index (<%= (type?(:indirect) && indirect_index[loop_variables]) || indirect_index_value %>),
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.o_select (<%= register_block.register_select[register.index] %>)
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);
|
@@ -1,21 +1,21 @@
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1
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simple_item :register, :address_decoder do
|
2
2
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rtl do
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3
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build do
|
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-
next unless
|
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-
logic :
|
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-
name: "#{register.name}
|
7
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width:
|
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next unless type?(:indirect)
|
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logic :indirect_index,
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name: "#{register.name}_indirect_index",
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width: indirect_index_width,
|
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dimensions: register.dimensions
|
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9
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end
|
10
10
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11
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generate_code :module_item do |buffer|
|
12
|
-
buffer <<
|
12
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+
buffer << indirect_index_assignment << nl if type?(:indirect)
|
13
13
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buffer << process_template
|
14
14
|
end
|
15
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delegate [:local_address_width] => :register_block
|
17
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-
delegate [:array?, :
|
18
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-
delegate [:
|
17
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+
delegate [:array?, :type?, :multiple?] => :register
|
18
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delegate [:indexes, :loop_variables] => :register
|
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19
|
|
20
20
|
def address_lsb
|
21
21
|
Math.clog2(configuration.byte_width)
|
@@ -40,41 +40,41 @@ simple_item :register, :address_decoder do
|
|
40
40
|
(array? && multiple? && "#{base} + #{register.local_index}") || base
|
41
41
|
end
|
42
42
|
|
43
|
-
def
|
43
|
+
def indirect_index_assignment
|
44
44
|
assign(
|
45
|
-
|
46
|
-
concat(
|
45
|
+
indirect_index[register.loop_variables],
|
46
|
+
concat(indirect_index_fields.map(&:value))
|
47
47
|
)
|
48
48
|
end
|
49
49
|
|
50
|
-
def
|
51
|
-
(
|
50
|
+
def indirect_register
|
51
|
+
(type?(:indirect) && 1) || 0
|
52
52
|
end
|
53
53
|
|
54
|
-
def
|
55
|
-
return 1 unless
|
56
|
-
|
54
|
+
def indirect_index_width
|
55
|
+
return 1 unless type?(:indirect)
|
56
|
+
indirect_index_fields.sum(0, &:width)
|
57
57
|
end
|
58
58
|
|
59
|
-
def
|
60
|
-
return hex(0, 1) unless
|
61
|
-
concat(
|
59
|
+
def indirect_index_value
|
60
|
+
return hex(0, 1) unless type?(:indirect)
|
61
|
+
concat(indirect_index_values)
|
62
62
|
end
|
63
63
|
|
64
|
-
def
|
65
|
-
@
|
64
|
+
def indirect_index_fields
|
65
|
+
@indirect_index_fields ||= indexes.map do |index|
|
66
66
|
register_block.bit_fields.find_by(name: index.name)
|
67
67
|
end
|
68
68
|
end
|
69
69
|
|
70
|
-
def
|
70
|
+
def indirect_index_values
|
71
71
|
variables = loop_variables
|
72
|
-
|
72
|
+
indexes.map.with_index do |index, i|
|
73
73
|
if index.value
|
74
|
-
hex(index.value,
|
74
|
+
hex(index.value, indirect_index_fields[i].width)
|
75
75
|
else
|
76
76
|
loop_variable = variables.shift
|
77
|
-
loop_variable[
|
77
|
+
loop_variable[indirect_index_fields[i].width - 1, 0]
|
78
78
|
end
|
79
79
|
end
|
80
80
|
end
|
@@ -16,16 +16,6 @@ simple_item :register, :array do
|
|
16
16
|
end
|
17
17
|
end
|
18
18
|
|
19
|
-
validate do
|
20
|
-
case
|
21
|
-
when multi_dimensions_array_with_real_register?
|
22
|
-
error 'not use multi dimensions array with real register'
|
23
|
-
when mismatch_with_own_byte_size?
|
24
|
-
error "mismatches with own byte size(#{register.byte_size}):" \
|
25
|
-
" #{dimensions}"
|
26
|
-
end
|
27
|
-
end
|
28
|
-
|
29
19
|
def parse_array_dimensions(cell)
|
30
20
|
case
|
31
21
|
when cell.nil? || cell.empty?
|
@@ -36,18 +26,6 @@ simple_item :register, :array do
|
|
36
26
|
error "invalid value for array dimension: #{cell.inspect}"
|
37
27
|
end
|
38
28
|
end
|
39
|
-
|
40
|
-
def multi_dimensions_array_with_real_register?
|
41
|
-
return false unless array?
|
42
|
-
return false if register.shadow?
|
43
|
-
register.multiple? && dimensions.size > 1
|
44
|
-
end
|
45
|
-
|
46
|
-
def mismatch_with_own_byte_size?
|
47
|
-
return false unless array?
|
48
|
-
return false if register.shadow?
|
49
|
-
register.byte_size != dimensions.first * configuration.byte_width
|
50
|
-
end
|
51
29
|
end
|
52
30
|
|
53
31
|
rtl do
|
@@ -4,10 +4,10 @@ simple_item :register, :bus_exporter do
|
|
4
4
|
:data_width, :byte_width
|
5
5
|
] => :configuration
|
6
6
|
delegate [
|
7
|
-
:name, :byte_size, :
|
7
|
+
:name, :byte_size, :index, :external_index
|
8
8
|
] => :register
|
9
9
|
|
10
|
-
available? { external
|
10
|
+
available? { register.type?(:external) }
|
11
11
|
|
12
12
|
build do
|
13
13
|
output :valid , name: "o_#{name}_valid" , width: 1
|
@@ -40,5 +40,13 @@ simple_item :register, :bus_exporter do
|
|
40
40
|
def start_address
|
41
41
|
hex(register.start_address, register_block.local_address_width)
|
42
42
|
end
|
43
|
+
|
44
|
+
def external_index
|
45
|
+
external_registers.index(®ister.method(:equal?))
|
46
|
+
end
|
47
|
+
|
48
|
+
def external_registers
|
49
|
+
register_block.registers.select { |r| r.type?(:external) }
|
50
|
+
end
|
43
51
|
end
|
44
52
|
end
|
@@ -0,0 +1,54 @@
|
|
1
|
+
simple_item :register, :indirect_index_configurator do
|
2
|
+
ral do
|
3
|
+
available? { register.type?(:indirect) }
|
4
|
+
|
5
|
+
generate_code :reg_model_item do
|
6
|
+
function_definition :configure_indirect_indexes do |f|
|
7
|
+
f.return_type :void
|
8
|
+
f.body { |code| function_body(code) }
|
9
|
+
end
|
10
|
+
end
|
11
|
+
|
12
|
+
def function_body(code)
|
13
|
+
register.indexes.each do |index|
|
14
|
+
code << subroutine_call(:set_indirect_index, arguments(index))
|
15
|
+
code << semicolon
|
16
|
+
code << nl
|
17
|
+
end
|
18
|
+
end
|
19
|
+
|
20
|
+
def arguments(indirect_index)
|
21
|
+
[
|
22
|
+
parent_name(indirect_index),
|
23
|
+
index_name(indirect_index),
|
24
|
+
index_value(indirect_index)
|
25
|
+
]
|
26
|
+
end
|
27
|
+
|
28
|
+
def parent_name(indirect_index)
|
29
|
+
parent_register = fild_parent_register(indirect_index.name)
|
30
|
+
string(parent_register.name)
|
31
|
+
end
|
32
|
+
|
33
|
+
def fild_parent_register(index_name)
|
34
|
+
register_block.bit_fields.find_by(name: index_name).register
|
35
|
+
end
|
36
|
+
|
37
|
+
def index_name(indirect_index)
|
38
|
+
string(indirect_index.name)
|
39
|
+
end
|
40
|
+
|
41
|
+
def index_value(indirect_index)
|
42
|
+
if indirect_index.value
|
43
|
+
indirect_index.value
|
44
|
+
else
|
45
|
+
"indexes[#{array_index}]"
|
46
|
+
end
|
47
|
+
end
|
48
|
+
|
49
|
+
def array_index
|
50
|
+
@array_index ||= -1
|
51
|
+
@array_index += 1
|
52
|
+
end
|
53
|
+
end
|
54
|
+
end
|
@@ -16,16 +16,9 @@ simple_item :register, :offset_address do
|
|
16
16
|
|
17
17
|
build do |cell|
|
18
18
|
@start_address, @end_address = parse_address(cell)
|
19
|
-
|
20
|
-
|
21
|
-
|
22
|
-
when unaligned_address?
|
23
|
-
error 'not aligned with data width' \
|
24
|
-
"(#{configuration.data_width}): #{cell}"
|
25
|
-
when @end_address > max_address
|
26
|
-
error 'exceeds the maximum offset address' \
|
27
|
-
"(0x#{max_address.to_s(16)}): #{cell}"
|
28
|
-
end
|
19
|
+
check_start_end_adderss_relation(cell)
|
20
|
+
check_address_align(cell)
|
21
|
+
check_address_range(cell)
|
29
22
|
end
|
30
23
|
|
31
24
|
def parse_address(cell)
|
@@ -41,11 +34,24 @@ simple_item :register, :offset_address do
|
|
41
34
|
end
|
42
35
|
end
|
43
36
|
|
44
|
-
def
|
45
|
-
|
46
|
-
return
|
47
|
-
|
48
|
-
|
37
|
+
def check_start_end_adderss_relation(cell)
|
38
|
+
return if start_address < end_address
|
39
|
+
return if [configuration.byte_width, byte_size].all? { |v| v == 1}
|
40
|
+
error "start address is equal to or greater than end address: #{cell}"
|
41
|
+
end
|
42
|
+
|
43
|
+
def check_address_align(cell)
|
44
|
+
return if [start_address, end_address + 1].all? do |a|
|
45
|
+
a.multiple?(configuration.byte_width)
|
46
|
+
end
|
47
|
+
error 'not aligned with data width' \
|
48
|
+
"(#{configuration.data_width}): #{cell}"
|
49
|
+
end
|
50
|
+
|
51
|
+
def check_address_range(cell)
|
52
|
+
return if end_address <= max_address
|
53
|
+
error 'exceeds the maximum offset address' \
|
54
|
+
"(0x#{max_address.to_s(16)}): #{cell}"
|
49
55
|
end
|
50
56
|
|
51
57
|
def max_address
|