rggen 0.4.4 → 0.5.1

data/lib/rggen/output_base/template_engine.rb

@@ -0,0 +1,24 @@
+module RgGen
+  module OutputBase
+    class TemplateEngine
+      include Singleton
+
+      def process_template(context, path = nil, call_info = nil)
+        path  ||= extract_template_path(call_info || caller[0])
+        render(context, templates[path])
+      end
+
+      private
+
+      def templates
+        @templates  ||= Hash.new do |t, p|
+          t[p]  = parse_template(p)
+        end
+      end
+
+      def extract_template_path(call_info)
+        File.ext(call_info[/^(.+?):\d/, 1], file_extension.to_s)
+      end
+    end
+  end
+end

data/lib/rggen/rggen_home.rb

@@ -0,0 +1,3 @@
+module RgGen
+  RGGEN_HOME  = File.realpath(File.join(__dir__, '../..'))
+end

data/lib/rggen/version.rb

@@ -1,6 +1,6 @@
 module RgGen
   MAJOR   = 0
-  MINOR   = 4
-  TEENY   = 4
+  MINOR   = 5
+  TEENY   = 1
   VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
 end

data/ral/rggen_ral_block.svh

@@ -65,7 +65,7 @@ function void rggen_ral_block::lock_model();
     foreach (maps[i]) begin
       rggen_ral_map rggen_map;
       if ($cast(rggen_map, maps[i])) begin
-        rggen_map.Xinit_shadow_reg_address_mapX();
+        rggen_map.Xinit_indirect_reg_address_mapX();
       end
     end
   end

data/ral/rggen_ral_indirect_reg.svh

@@ -0,0 +1,193 @@
+`ifndef __RGGEN_RAL_INDIRECT_REG_SVH__
+`define __RGGEN_RAL_INDIRECT_REG_SVH__
+typedef class rggen_ral_indirect_reg_index;
+typedef class rggen_ral_indirect_reg_ftdr_seq;
+
+class rggen_ral_indirect_reg extends rggen_ral_reg;
+  protected rggen_ral_indirect_reg_index  indirect_reg_indexes[$];
+
+  extern function new(string name, int unsigned n_bits, int has_coverage);
+
+  extern function void configure(
+    uvm_object    cfg,
+    uvm_reg_block blk_parent,
+    uvm_reg_file  regfile_parent,
+    int           indexes[$],
+    string        hdl_path = ""
+  );
+
+  extern virtual function uvm_reg_frontdoor create_frontdoor();
+  extern virtual function bit is_active();
+
+  extern protected virtual function void configure_indirect_indexes();
+  extern protected function void set_indirect_index(string reg_name, string field_name, uvm_reg_data_t value);
+endclass
+
+function rggen_ral_indirect_reg::new(string name, int unsigned n_bits, int has_coverage);
+  super.new(name, n_bits, has_coverage);
+endfunction
+
+function void rggen_ral_indirect_reg::configure(
+  uvm_object    cfg,
+  uvm_reg_block blk_parent,
+  uvm_reg_file  regfile_parent,
+  int           indexes[$],
+  string        hdl_path
+);
+  super.configure(cfg, blk_parent, regfile_parent, indexes, hdl_path);
+  configure_indirect_indexes();
+endfunction
+
+function uvm_reg_frontdoor rggen_ral_indirect_reg::create_frontdoor();
+  rggen_ral_indirect_reg_ftdr_seq fd  = new(indirect_reg_indexes);
+  return fd;
+endfunction
+
+function bit rggen_ral_indirect_reg::is_active();
+  foreach (indirect_reg_indexes[i]) begin
+    if (!indirect_reg_indexes[i].is_matched()) begin
+      return 0;
+    end
+  end
+  return 1;
+endfunction
+
+function void rggen_ral_indirect_reg::configure_indirect_indexes();
+endfunction
+
+function void rggen_ral_indirect_reg::set_indirect_index(string reg_name, string field_name, uvm_reg_data_t value);
+  rggen_ral_indirect_reg_index indirect_reg_index;
+  indirect_reg_index  = new(this, reg_name, field_name, value);
+  indirect_reg_indexes.push_back(indirect_reg_index);
+endfunction
+
+class rggen_ral_indirect_reg_index;
+  protected rggen_ral_indirect_reg  indirect_reg;
+  protected string                  reg_name;
+  protected string                  field_name;
+  protected uvm_reg_data_t          value;
+  protected uvm_reg                 index_reg;
+  protected uvm_reg_field           index_field;
+
+  extern function new(
+    rggen_ral_indirect_reg  indirect_reg,
+    string                  reg_name,
+    string                  field_name,
+    uvm_reg_data_t          value
+  );
+
+  extern virtual function bit is_matched();
+  extern virtual function void set(string fname = "", int lineno = 0);
+  extern virtual function uvm_reg get_index_reg();
+  extern virtual function uvm_reg_field get_index_field();
+endclass
+
+function rggen_ral_indirect_reg_index::new(
+  rggen_ral_indirect_reg  indirect_reg,
+  string                  reg_name,
+  string                  field_name,
+  uvm_reg_data_t          value
+);
+  this.indirect_reg = indirect_reg;
+  this.reg_name     = reg_name;
+  this.field_name   = field_name;
+  this.value        = value;
+endfunction
+
+function bit rggen_ral_indirect_reg_index::is_matched();
+  void'(get_index_field());
+  return (index_field.value == value) ? 1 : 0;
+endfunction
+
+function void rggen_ral_indirect_reg_index::set(string fname = "", int lineno = 0);
+  void'(get_index_field());
+  index_field.set(value, fname, lineno);
+endfunction
+
+function uvm_reg rggen_ral_indirect_reg_index::get_index_reg();
+  if (index_reg == null) begin
+    uvm_reg_block parent_block;
+    parent_block  = indirect_reg.get_parent();
+    index_reg     = parent_block.get_reg_by_name(reg_name);
+    if (index_reg == null) begin
+      `uvm_fatal("rggen_ral_indirect_reg_index", $sformatf("Unable to locate index register: %s", reg_name))
+      return null;
+    end
+  end
+  return index_reg;
+endfunction
+
+function uvm_reg_field rggen_ral_indirect_reg_index::get_index_field();
+  if (index_field == null) begin
+    void'(get_index_reg());
+    index_field = index_reg.get_field_by_name(field_name);
+    if (index_field == null) begin
+      `uvm_fatal("rggen_ral_indirect_reg_index", $sformatf("Unable to locate index field: %s", field_name))
+      return null;
+    end
+  end
+  return index_field;
+endfunction
+
+class rggen_ral_indirect_reg_ftdr_seq extends uvm_reg_frontdoor;
+  protected rggen_ral_indirect_reg_index  indirect_indexes[$];
+  protected bit                           index_regs[uvm_reg];
+
+  extern function new(ref rggen_ral_indirect_reg_index indirect_indexes[$]);
+
+  extern virtual task body();
+  extern task update_index_regs(ref uvm_status_e status);
+endclass
+
+function rggen_ral_indirect_reg_ftdr_seq::new(ref rggen_ral_indirect_reg_index indirect_indexes[$]);
+  super.new("rggen_ral_indirect_reg_ftdr_seq");
+  foreach (indirect_indexes[i]) begin
+    this.indirect_indexes.push_back(indirect_indexes[i]);
+  end
+endfunction
+
+task rggen_ral_indirect_reg_ftdr_seq::body();
+  uvm_status_e  status;
+  update_index_regs(status);
+  if (status == UVM_NOT_OK) begin
+    `uvm_warning("rggen_ral_indirect_reg_ftdr_seq", "Updating index registers failed")
+    rw_info.status  = status;
+    return;
+  end
+  if (rw_info.kind == UVM_WRITE) begin
+    rw_info.local_map.do_write(rw_info);
+  end
+  else begin
+    rw_info.local_map.do_read(rw_info);
+  end
+endtask
+
+task rggen_ral_indirect_reg_ftdr_seq::update_index_regs(ref uvm_status_e status);
+  if (index_regs.size() == 0) begin
+    foreach (indirect_indexes[i]) begin
+      uvm_reg index_reg = indirect_indexes[i].get_index_reg();
+      if (!index_regs.exists(index_reg)) begin
+        index_regs[index_reg] = 1;
+      end
+    end
+  end
+  foreach (indirect_indexes[i]) begin
+    indirect_indexes[i].set(rw_info.fname, rw_info.lineno);
+  end
+  foreach (index_regs[index_reg]) begin
+    index_reg.update(
+      status,
+      rw_info.path,
+      rw_info.map,
+      rw_info.parent,
+      rw_info.prior,
+      rw_info.extension,
+      rw_info.fname,
+      rw_info.lineno
+    );
+    if (status == UVM_NOT_OK) begin
+      return;
+    end
+  end
+endtask
+`endif

data/ral/rggen_ral_map.svh

@@ -1,7 +1,7 @@
 `ifndef __RGGEN_RAL_MAP_SVH__
 `define __RGGEN_RAL_MAP_SVH__
 class rggen_ral_map extends uvm_reg_map;
-  protected rggen_ral_shadow_reg m_shadow_regs_by_offset[uvm_reg_addr_t][$];
+  protected rggen_ral_indirect_reg  m_indirect_regs_by_offset[uvm_reg_addr_t][$];
 
   extern function new(string name = "rggen_ral_map");
 
@@ -17,7 +17,7 @@ class rggen_ral_map extends uvm_reg_map;
 
   extern virtual function uvm_reg get_reg_by_offset(uvm_reg_addr_t offset, bit read = 1);
 
-  extern function void Xinit_shadow_reg_address_mapX();
+  extern function void Xinit_indirect_reg_address_mapX();
 
   `uvm_object_utils(rggen_ral_map)
 endclass
@@ -33,13 +33,13 @@ function void rggen_ral_map::add_reg(
   bit               unmapped,
   uvm_reg_frontdoor frontdoor
 );
-  rggen_ral_reg        rggen_reg;
-  rggen_ral_shadow_reg rggen_shadow_reg;
+  rggen_ral_reg           rggen_reg;
+  rggen_ral_indirect_reg  rggen_indirect_reg;
 
   if ((frontdoor == null) && $cast(rggen_reg, rg)) begin
     frontdoor = rggen_reg.create_frontdoor();
   end
-  if ($cast(rggen_shadow_reg, rg)) begin
+  if ($cast(rggen_indirect_reg, rg)) begin
     unmapped  = 1;
   end
   super.add_reg(rg, offset, rights, unmapped, frontdoor);
@@ -51,7 +51,7 @@ function void rggen_ral_map::set_base_addr(uvm_reg_addr_t offset);
   bit           locked        = parent_block.is_locked();
   super.set_base_addr(offset);
   if ((parent_map == null) && locked) begin
-    Xinit_shadow_reg_address_mapX();
+    Xinit_indirect_reg_address_mapX();
   end
 endfunction
 
@@ -63,7 +63,7 @@ function void rggen_ral_map::set_submap_offset(uvm_reg_map submap, uvm_reg_addr_
     uvm_reg_map   root_map  = get_root_map();
     rggen_ral_map rggen_map;
     if ($cast(rggen_map, root_map)) begin
-      rggen_map.Xinit_shadow_reg_address_mapX();
+      rggen_map.Xinit_indirect_reg_address_mapX();
     end
   end
 endfunction
@@ -71,10 +71,10 @@ endfunction
 function uvm_reg rggen_ral_map::get_reg_by_offset(uvm_reg_addr_t offset, bit read);
   uvm_reg       rg      = super.get_reg_by_offset(offset, read);
   uvm_reg_block parent  = get_parent();
-  if ((rg == null) && parent.is_locked() && m_shadow_regs_by_offset.exists(offset)) begin
-    foreach (m_shadow_regs_by_offset[offset][i]) begin
-      if (m_shadow_regs_by_offset[offset][i].is_active()) begin
-        rg  = m_shadow_regs_by_offset[offset][i];
+  if ((rg == null) && parent.is_locked() && m_indirect_regs_by_offset.exists(offset)) begin
+    foreach (m_indirect_regs_by_offset[offset][i]) begin
+      if (m_indirect_regs_by_offset[offset][i].is_active()) begin
+        rg  = m_indirect_regs_by_offset[offset][i];
         break;
       end
     end
@@ -82,7 +82,7 @@ function uvm_reg rggen_ral_map::get_reg_by_offset(uvm_reg_addr_t offset, bit rea
   return rg;
 endfunction
 
-function void rggen_ral_map::Xinit_shadow_reg_address_mapX();
+function void rggen_ral_map::Xinit_indirect_reg_address_mapX();
   uvm_reg_map   top_map;
   rggen_ral_map top_rggen_map;
   uvm_reg_map   submaps[$];
@@ -90,7 +90,7 @@ function void rggen_ral_map::Xinit_shadow_reg_address_mapX();
 
   top_map = get_root_map();
   if (top_map == this) begin
-    m_shadow_regs_by_offset.delete();
+    m_indirect_regs_by_offset.delete();
   end
   if (!$cast(top_rggen_map, top_map)) begin
     return;
@@ -100,24 +100,24 @@ function void rggen_ral_map::Xinit_shadow_reg_address_mapX();
   foreach (submaps[i]) begin
     rggen_ral_map rggen_map;
     if ($cast(rggen_map, submaps[i])) begin
-      rggen_map.Xinit_shadow_reg_address_mapX();
+      rggen_map.Xinit_indirect_reg_address_mapX();
     end
   end
 
   get_registers(regs, UVM_NO_HIER);
   foreach (regs[i]) begin
-    rggen_ral_shadow_reg  shadow_reg;
-    uvm_reg_map_info      map_info;
+    rggen_ral_indirect_reg  indirect_reg;
+    uvm_reg_map_info        map_info;
 
-    if (!$cast(shadow_reg, regs[i])) begin
+    if (!$cast(indirect_reg, regs[i])) begin
       continue;
     end
 
-    map_info          = get_reg_map_info(shadow_reg);
+    map_info          = get_reg_map_info(indirect_reg);
     map_info.unmapped = 0;
-    void'(get_physical_addresses(map_info.offset, 0, shadow_reg.get_n_bytes(), map_info.addr));
+    void'(get_physical_addresses(map_info.offset, 0, indirect_reg.get_n_bytes(), map_info.addr));
     foreach (map_info.addr[j]) begin
-      top_rggen_map.m_shadow_regs_by_offset[map_info.addr[j]].push_back(shadow_reg);
+      top_rggen_map.m_indirect_regs_by_offset[map_info.addr[j]].push_back(indirect_reg);
     end
   end
 endfunction

data/ral/rggen_ral_pkg.sv

@@ -8,7 +8,7 @@ package rggen_ral_pkg;
   `include  "rggen_ral_field.svh"
   `include  "rggen_ral_field_rwl_rwe.svh"
   `include  "rggen_ral_reg.svh"
-  `include  "rggen_ral_shadow_reg.svh"
+  `include  "rggen_ral_indirect_reg.svh"
   `include  "rggen_ral_map.svh"
   `include  "rggen_ral_block.svh"
 endpackage

data/rtl/register/rggen_address_decoder.sv

@@ -1,19 +1,19 @@
 module rggen_address_decoder #(
-  parameter ADDRESS_WIDTH       = 16,
-  parameter START_ADDRESS       = 'h00,
-  parameter END_ADDRESS         = 'h00,
-  parameter USE_SHADOW_INDEX    = 0,
-  parameter SHADOW_INDEX_WIDTH  = 1,
-  parameter SHADOW_INDEX_VALUE  = 'h00
+  parameter ADDRESS_WIDTH         = 16,
+  parameter START_ADDRESS         = 'h00,
+  parameter END_ADDRESS           = 'h00,
+  parameter INDIRECT_REGISTER     = 0,
+  parameter INDIRECT_INDEX_WIDTH  = 1,
+  parameter INDIRECT_INDEX_VALUE  = 'h00
 )(
-  input   [ADDRESS_WIDTH-1:0]       i_address,
-  input   [SHADOW_INDEX_WIDTH-1:0]  i_shadow_index,
-  output                            o_select
+  input   [ADDRESS_WIDTH-1:0]         i_address,
+  input   [INDIRECT_INDEX_WIDTH-1:0]  i_indirect_index,
+  output                              o_select
 );
   logic match_address;
-  logic match_shadow_index;
+  logic match_indirect_index;
 
-  assign  o_select  = (match_address && match_shadow_index) ? 1'b1 : 1'b0;
+  assign  o_select  = (match_address && match_indirect_index) ? 1'b1 : 1'b0;
 
   generate
     if (START_ADDRESS == END_ADDRESS) begin
@@ -27,11 +27,11 @@ module rggen_address_decoder #(
   endgenerate
 
   generate
-    if (USE_SHADOW_INDEX) begin
-      assign  match_shadow_index  = (i_shadow_index == SHADOW_INDEX_VALUE) ? 1'b1 : 1'b0;
+    if (INDIRECT_REGISTER) begin
+      assign  match_indirect_index  = (i_indirect_index == INDIRECT_INDEX_VALUE) ? 1'b1 : 1'b0;
     end
     else begin
-      assign  match_shadow_index  = 1'b1;
+      assign  match_indirect_index  = 1'b1;
     end
   endgenerate
 endmodule

data/sample/sample.csv

@@ -1,22 +1,21 @@
-,block name,block_0,,,,,,,,,
-,byte size,256,,,,,,,,,
-,,,,,,,,,,,
-,offset address,registe name,array dimension,shadow index,external,assignment,field name,type,initial value,reference,
-,0x00,register_0,,,,[31:16],bit_field_0_0,rw,0,,
-,,,,,,[15:0],bit_field_0_1,rw,0,,
-,0x04,register_1,,,,[31:0],bit_field_1_0,rw,0,,
-,0x08,register_2,,,,[16],bit_field_2_0,ro,,,
-,,,,,,[0],bit_field_2_1,rw,0,,
-,0x0C,register_3,,,,[31:0],bit_field_3_0,ro,,,
-,0x10 - 0x1F,register_4,[4],,,[31:16],bit_field_4_0,ro,,,
-,,,,,,[15:0],bit_field_4_1,rw,0,,
-,0x20,register_5,"[2,4]","bit_field_2_1:1, bit_field_0_0, bit_field_0_1",,[31:16],bit_field_5_0,ro,,,
-,,,,,,[15:0],bit_field_5_1,rw,0,,
-,0x24,register_6,,,,[8],bit_field_6_0,w0c,0,bit_field_2_1,
-,,,,,,[0],bit_field_6_1,w1c,0,bit_field_2_1,
-,0x28,register_7,,,,[8],bit_field_7_0,w0s,0,,
-,,,,,,[0],bit_field_7_1,w1s,0,,
-,0x2C,register_8,,,,[31:16],bit_field_8_0,rwl,0,bit_field_2_1,
-,,,,,,[15:0],bit_field_8_1,rwe,0,bit_field_2_1,
-,0x80-0xFF,register_9,,,TRUE,,,,,,
-,,,,,,,,,,,
+,block name,block_0,,,,,,,
+,byte size,256,,,,,,,
+,,,,,,,,,
+,offset address,registe name,array dimension,type,assignment,field name,type,initial value,reference
+,0x00,register_0,,,[31:16],bit_field_0_0,rw,0,
+,,,,,[15:0],bit_field_0_1,rw,0,
+,0x04,register_1,,,[31:0],bit_field_1_0,rw,0,
+,0x08,register_2,,,[16],bit_field_2_0,ro,,
+,,,,,[0],bit_field_2_1,rw,0,
+,0x0C,register_3,,,[31:0],bit_field_3_0,ro,,
+,0x10 - 0x1F,register_4,[4],,[31:16],bit_field_4_0,ro,,
+,,,,,[15:0],bit_field_4_1,rw,0,
+,0x20,register_5,"[2,4]","indirect: bit_field_2_1:1, bit_field_0_0, bit_field_0_1",[31:16],bit_field_5_0,ro,,
+,,,,,[15:0],bit_field_5_1,rw,0,
+,0x24,register_6,,,[8],bit_field_6_0,w0c,0,bit_field_2_1
+,,,,,[0],bit_field_6_1,w1c,0,bit_field_2_1
+,0x28,register_7,,,[8],bit_field_7_0,w0s,0,
+,,,,,[0],bit_field_7_1,w1s,0,
+,0x2C,register_8,,,[31:16],bit_field_8_0,rwl,0,bit_field_2_1
+,,,,,[15:0],bit_field_8_1,rwe,0,bit_field_2_1
+,0x80-0xFF,register_9,,external,,,,,