rggen 0.4.4 → 0.5.1
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- checksums.yaml +4 -4
- data/LICENSE.txt +1 -1
- data/README.md +3 -2
- data/c/rggen.h +17 -0
- data/lib/rggen.rb +7 -16
- data/lib/rggen/base/item_factory.rb +2 -0
- data/lib/rggen/builtins.rb +15 -13
- data/lib/rggen/builtins/bit_field/{reserved.rb → types/reserved.rb} +0 -0
- data/lib/rggen/builtins/bit_field/{ro.erb → types/ro.erb} +0 -0
- data/lib/rggen/builtins/bit_field/{ro.rb → types/ro.rb} +0 -0
- data/lib/rggen/builtins/bit_field/{rw.erb → types/rw.erb} +0 -0
- data/lib/rggen/builtins/bit_field/{rw.rb → types/rw.rb} +0 -0
- data/lib/rggen/builtins/bit_field/{rwl_rwe.erb → types/rwl_rwe.erb} +0 -0
- data/lib/rggen/builtins/bit_field/{rwl_rwe.rb → types/rwl_rwe.rb} +0 -0
- data/lib/rggen/builtins/bit_field/{w0c_w1c.erb → types/w0c_w1c.erb} +0 -0
- data/lib/rggen/builtins/bit_field/{w0c_w1c.rb → types/w0c_w1c.rb} +0 -0
- data/lib/rggen/builtins/bit_field/{w0s_w1s.erb → types/w0s_w1s.erb} +0 -0
- data/lib/rggen/builtins/bit_field/{w0s_w1s.rb → types/w0s_w1s.rb} +0 -0
- data/lib/rggen/builtins/bit_field/{wo.rb → types/wo.rb} +0 -0
- data/lib/rggen/builtins/register/address_decoder.erb +9 -9
- data/lib/rggen/builtins/register/address_decoder.rb +24 -24
- data/lib/rggen/builtins/register/array.rb +0 -22
- data/lib/rggen/builtins/register/bus_exporter.rb +10 -2
- data/lib/rggen/builtins/register/indirect_index_configurator.rb +54 -0
- data/lib/rggen/builtins/register/offset_address.rb +21 -15
- data/lib/rggen/builtins/register/read_data.rb +1 -1
- data/lib/rggen/builtins/register/reg_model.rb +5 -5
- data/lib/rggen/builtins/register/sub_block_model.rb +1 -1
- data/lib/rggen/builtins/register/type.rb +207 -0
- data/lib/rggen/builtins/register/types/external.rb +15 -0
- data/lib/rggen/builtins/register/types/indirect.rb +134 -0
- data/lib/rggen/builtins/register/uniqueness_validator.rb +10 -7
- data/lib/rggen/builtins/register_block/address_struct.rb +56 -0
- data/lib/rggen/builtins/register_block/c_header_file.rb +15 -0
- data/lib/rggen/builtins/register_block/{apb.erb → host_ifs/apb.erb} +0 -0
- data/lib/rggen/builtins/register_block/{apb.rb → host_ifs/apb.rb} +0 -0
- data/lib/rggen/builtins/register_block/{axi4lite.erb → host_ifs/axi4lite.erb} +0 -0
- data/lib/rggen/builtins/register_block/{axi4lite.rb → host_ifs/axi4lite.rb} +0 -0
- data/lib/rggen/builtins/register_block/ral_package.rb +6 -1
- data/lib/rggen/builtins/register_block/response_mux.rb +2 -2
- data/lib/rggen/builtins/register_block/top_module.rb +5 -1
- data/lib/rggen/core_components.rb +25 -0
- data/lib/rggen/core_components/c_header/item.rb +8 -0
- data/lib/rggen/core_components/c_header/setup.rb +19 -0
- data/lib/rggen/core_components/c_utility.rb +19 -0
- data/lib/rggen/core_components/c_utility/data_structure_definition.rb +62 -0
- data/lib/rggen/core_components/c_utility/source_file.rb +10 -0
- data/lib/rggen/core_components/c_utility/variable_declaration.rb +35 -0
- data/lib/rggen/core_components/code_utility.rb +56 -0
- data/lib/rggen/{output_base → core_components/code_utility}/code_block.rb +1 -1
- data/lib/rggen/{output_base → core_components/code_utility}/line.rb +1 -1
- data/lib/rggen/core_components/code_utility/source_file.rb +97 -0
- data/lib/rggen/core_components/erb_engine.rb +15 -0
- data/lib/rggen/core_components/ral/item.rb +2 -1
- data/lib/rggen/core_components/register_map/generic_map.rb +3 -1
- data/lib/rggen/core_components/rtl/item.rb +2 -1
- data/lib/rggen/core_components/verilog_utility.rb +69 -0
- data/lib/rggen/core_components/verilog_utility/class_definition.rb +56 -0
- data/lib/rggen/core_components/verilog_utility/declaration.rb +66 -0
- data/lib/rggen/core_components/verilog_utility/identifier.rb +27 -0
- data/lib/rggen/core_components/verilog_utility/module_definition.rb +71 -0
- data/lib/rggen/core_components/verilog_utility/package_definition.rb +65 -0
- data/lib/rggen/core_components/verilog_utility/source_file.rb +10 -0
- data/lib/rggen/core_components/verilog_utility/structure_definition.rb +50 -0
- data/lib/rggen/core_components/verilog_utility/subroutine_definition.rb +41 -0
- data/lib/rggen/core_extensions/facets.rb +5 -0
- data/lib/rggen/generator.rb +19 -5
- data/lib/rggen/input_base/item.rb +6 -6
- data/lib/rggen/output_base/code_generator.rb +36 -0
- data/lib/rggen/output_base/component.rb +27 -41
- data/lib/rggen/output_base/file_writer.rb +36 -0
- data/lib/rggen/output_base/item.rb +34 -100
- data/lib/rggen/output_base/template_engine.rb +24 -0
- data/lib/rggen/rggen_home.rb +3 -0
- data/lib/rggen/version.rb +2 -2
- data/ral/rggen_ral_block.svh +1 -1
- data/ral/rggen_ral_indirect_reg.svh +193 -0
- data/ral/rggen_ral_map.svh +20 -20
- data/ral/rggen_ral_pkg.sv +1 -1
- data/rtl/register/rggen_address_decoder.sv +14 -14
- data/sample/sample.csv +21 -22
- data/sample/sample.xls +0 -0
- data/sample/sample.xlsx +0 -0
- data/sample/sample_0.h +17 -0
- data/sample/sample_0.sv +92 -92
- data/sample/sample_0_ral_pkg.sv +8 -5
- data/sample/sample_1.h +9 -0
- data/sample/sample_1.sv +27 -27
- data/sample/sample_1_ral_pkg.sv +3 -0
- data/sample/sample_setup.rb +4 -2
- data/setup/default.rb +4 -2
- metadata +53 -36
- data/lib/rggen/builtins/register/accessibility.rb +0 -23
- data/lib/rggen/builtins/register/external.rb +0 -42
- data/lib/rggen/builtins/register/shadow.rb +0 -130
- data/lib/rggen/builtins/register/shadow_index_configurator.rb +0 -56
- data/lib/rggen/output_base/code_utility.rb +0 -50
- data/lib/rggen/output_base/template_utility.rb +0 -29
- data/lib/rggen/output_base/verilog_utility.rb +0 -69
- data/lib/rggen/output_base/verilog_utility/class_definition.rb +0 -58
- data/lib/rggen/output_base/verilog_utility/declaration.rb +0 -68
- data/lib/rggen/output_base/verilog_utility/identifier.rb +0 -29
- data/lib/rggen/output_base/verilog_utility/module_definition.rb +0 -73
- data/lib/rggen/output_base/verilog_utility/package_definition.rb +0 -67
- data/lib/rggen/output_base/verilog_utility/structure_definition.rb +0 -52
- data/lib/rggen/output_base/verilog_utility/subroutine_definition.rb +0 -43
- data/ral/rggen_ral_shadow_reg.svh +0 -193
@@ -1,52 +0,0 @@
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module RgGen
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module OutputBase
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module VerilogUtility
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class StructureDefinition
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include CodeUtility
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def initialize(name, &body)
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body.call(self) if block_given?
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end
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def body(&block)
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bodies << block if block_given?
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end
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def to_code
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code_block do |code|
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code << header_code << nl
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body_code(code) if body_code?
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code << footer_code << nl
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end
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end
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private
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def bodies
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end
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generate_body_code(code, body)
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end
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end
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def generate_body_code(code, body)
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indent(code, 2) do
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code << body.call
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end
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end
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end
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def body_code?
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@bodies && @bodies.size > 0
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end
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end
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module RgGen
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module OutputBase
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module VerilogUtility
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class SubroutineDefinition < StructureDefinition
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def initialize(type, name, &body)
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@type = type
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super(name, &body)
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end
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def return_type(data_type_and_width)
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if [Symbol, String].any?(&data_type_and_width.method(:is_a?))
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@return_type = data_type_and_width
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else
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data_type = data_type_and_width[:data_type]
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width = data_type_and_width[:width ] || 1
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@return_type =
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end
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end
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attr_setter :arguments
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def function?
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"#{@name}(#{Array(@arguments).join(', ')});"
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end
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end
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`ifndef __RGGEN_RAL_SHADOW_REG_SVH__
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`define __RGGEN_RAL_SHADOW_REG_SVH__
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typedef class rggen_ral_shadow_reg_index;
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typedef class rggen_ral_shadow_reg_ftdr_seq;
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class rggen_ral_shadow_reg extends rggen_ral_reg;
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protected rggen_ral_shadow_reg_index shadow_reg_indexes[$];
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extern function new(string name, int unsigned n_bits, int has_coverage);
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extern function void configure(
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uvm_object cfg,
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uvm_reg_block blk_parent,
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uvm_reg_file regfile_parent,
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int indexes[$],
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string hdl_path = ""
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);
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extern virtual function uvm_reg_frontdoor create_frontdoor();
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extern virtual function bit is_active();
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extern protected virtual function void configure_shadow_indexes();
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extern protected function void set_shadow_index(string reg_name, string field_name, uvm_reg_data_t value);
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endclass
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function rggen_ral_shadow_reg::new(string name, int unsigned n_bits, int has_coverage);
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super.new(name, n_bits, has_coverage);
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endfunction
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function void rggen_ral_shadow_reg::configure(
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uvm_object cfg,
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uvm_reg_block blk_parent,
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uvm_reg_file regfile_parent,
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int indexes[$],
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string hdl_path
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);
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super.configure(cfg, blk_parent, regfile_parent, indexes, hdl_path);
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configure_shadow_indexes();
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endfunction
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function uvm_reg_frontdoor rggen_ral_shadow_reg::create_frontdoor();
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rggen_ral_shadow_reg_ftdr_seq fd = new(shadow_reg_indexes);
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return fd;
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endfunction
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function bit rggen_ral_shadow_reg::is_active();
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foreach (shadow_reg_indexes[i]) begin
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if (!shadow_reg_indexes[i].is_matched()) begin
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return 0;
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end
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end
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return 1;
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endfunction
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function void rggen_ral_shadow_reg::configure_shadow_indexes();
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endfunction
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function void rggen_ral_shadow_reg::set_shadow_index(string reg_name, string field_name, uvm_reg_data_t value);
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rggen_ral_shadow_reg_index shadow_reg_index;
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shadow_reg_index = new(this, reg_name, field_name, value);
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shadow_reg_indexes.push_back(shadow_reg_index);
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endfunction
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class rggen_ral_shadow_reg_index;
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protected rggen_ral_shadow_reg shadow_reg;
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protected string reg_name;
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protected string field_name;
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protected uvm_reg_data_t value;
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protected uvm_reg index_reg;
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protected uvm_reg_field index_field;
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extern function new(
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rggen_ral_shadow_reg shadow_reg,
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string reg_name,
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string field_name,
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uvm_reg_data_t value
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);
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extern virtual function bit is_matched();
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extern virtual function void set(string fname = "", int lineno = 0);
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extern virtual function uvm_reg get_index_reg();
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extern virtual function uvm_reg_field get_index_field();
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endclass
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function rggen_ral_shadow_reg_index::new(
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rggen_ral_shadow_reg shadow_reg,
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string reg_name,
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string field_name,
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uvm_reg_data_t value
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);
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this.shadow_reg = shadow_reg;
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this.reg_name = reg_name;
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this.field_name = field_name;
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this.value = value;
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endfunction
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function bit rggen_ral_shadow_reg_index::is_matched();
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void'(get_index_field());
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return (index_field.value == value) ? 1 : 0;
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endfunction
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function void rggen_ral_shadow_reg_index::set(string fname = "", int lineno = 0);
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void'(get_index_field());
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index_field.set(value, fname, lineno);
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endfunction
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function uvm_reg rggen_ral_shadow_reg_index::get_index_reg();
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if (index_reg == null) begin
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uvm_reg_block parent_block;
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parent_block = shadow_reg.get_parent();
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index_reg = parent_block.get_reg_by_name(reg_name);
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if (index_reg == null) begin
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`uvm_fatal("rggen_ral_shadow_reg_index", $sformatf("Unable to locate index register: %s", reg_name))
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return null;
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end
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end
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return index_reg;
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endfunction
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function uvm_reg_field rggen_ral_shadow_reg_index::get_index_field();
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if (index_field == null) begin
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void'(get_index_reg());
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index_field = index_reg.get_field_by_name(field_name);
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if (index_field == null) begin
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`uvm_fatal("rggen_ral_shadow_reg_index", $sformatf("Unable to locate index field: %s", field_name))
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return null;
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end
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end
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return index_field;
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endfunction
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class rggen_ral_shadow_reg_ftdr_seq extends uvm_reg_frontdoor;
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protected rggen_ral_shadow_reg_index shadow_indexes[$];
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protected bit index_regs[uvm_reg];
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extern function new(ref rggen_ral_shadow_reg_index shadow_indexes[$]);
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extern virtual task body();
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extern task update_index_regs(ref uvm_status_e status);
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endclass
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function rggen_ral_shadow_reg_ftdr_seq::new(ref rggen_ral_shadow_reg_index shadow_indexes[$]);
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super.new("rggen_ral_shadow_reg_ftdr_seq");
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foreach (shadow_indexes[i]) begin
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this.shadow_indexes.push_back(shadow_indexes[i]);
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end
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endfunction
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task rggen_ral_shadow_reg_ftdr_seq::body();
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uvm_status_e status;
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update_index_regs(status);
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if (status == UVM_NOT_OK) begin
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`uvm_warning("rggen_ral_shadow_reg_ftdr_seq", "Updating index registers failed")
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|
-
rw_info.status = status;
|
155
|
-
return;
|
156
|
-
end
|
157
|
-
if (rw_info.kind == UVM_WRITE) begin
|
158
|
-
rw_info.local_map.do_write(rw_info);
|
159
|
-
end
|
160
|
-
else begin
|
161
|
-
rw_info.local_map.do_read(rw_info);
|
162
|
-
end
|
163
|
-
endtask
|
164
|
-
|
165
|
-
task rggen_ral_shadow_reg_ftdr_seq::update_index_regs(ref uvm_status_e status);
|
166
|
-
if (index_regs.size() == 0) begin
|
167
|
-
foreach (shadow_indexes[i]) begin
|
168
|
-
uvm_reg index_reg = shadow_indexes[i].get_index_reg();
|
169
|
-
if (!index_regs.exists(index_reg)) begin
|
170
|
-
index_regs[index_reg] = 1;
|
171
|
-
end
|
172
|
-
end
|
173
|
-
end
|
174
|
-
foreach (shadow_indexes[i]) begin
|
175
|
-
shadow_indexes[i].set(rw_info.fname, rw_info.lineno);
|
176
|
-
end
|
177
|
-
foreach (index_regs[index_reg]) begin
|
178
|
-
index_reg.update(
|
179
|
-
status,
|
180
|
-
rw_info.path,
|
181
|
-
rw_info.map,
|
182
|
-
rw_info.parent,
|
183
|
-
rw_info.prior,
|
184
|
-
rw_info.extension,
|
185
|
-
rw_info.fname,
|
186
|
-
rw_info.lineno
|
187
|
-
);
|
188
|
-
if (status == UVM_NOT_OK) begin
|
189
|
-
return;
|
190
|
-
end
|
191
|
-
end
|
192
|
-
endtask
|
193
|
-
`endif
|