rggen 0.4.4 → 0.5.1

data/lib/rggen/output_base/code_utility.rb

@@ -1,50 +0,0 @@
-module RgGen
-  module OutputBase
-    module CodeUtility
-      private
-
-      def newline
-        :newline
-      end
-
-      alias_method :nl, :newline
-
-      def comma
-        ','
-      end
-
-      def semicolon
-        ';'
-      end
-
-      def space(size = 1)
-        ' ' * size
-      end
-
-      def code_block(indent_size = 0, &block)
-        CodeBlock.new.tap do |code|
-          code.indent = indent_size
-          block.call(code) if block_given?
-        end
-      end
-
-      def indent(code_block, indent_size, &indent_block)
-        code_block << nl unless code_block.last_line_empty?
-        code_block.indent += indent_size
-        indent_block.call if block_given?
-        code_block << nl unless code_block.last_line_empty?
-        code_block.indent -= indent_size
-      end
-
-      def wrap(code_block, head, tail, &block)
-        code_block << head
-        block.call if block_given?
-        code_block << tail
-      end
-
-      def loop_index(level)
-        level.times.with_object('i') { |_, index| index.next! }
-      end
-    end
-  end
-end

data/lib/rggen/output_base/template_utility.rb

@@ -1,29 +0,0 @@
-module RgGen
-  module OutputBase
-    module TemplateUtility
-      module Extensions
-        def template_engines
-          @template_engines ||= Hash.new do |engines, path|
-            engines[path] = create_engine(path)
-          end
-        end
-
-        private
-
-        def create_engine(path)
-          template  = File.read(path)
-          BabyErubis::Text.new.from_str(template, path)
-        end
-      end
-
-      def self.included(klass)
-        klass.extend(Extensions)
-      end
-
-      def process_template(path = nil)
-        path  ||= File.ext(caller.first[/^(.+?):\d/, 1], 'erb')
-        self.class.template_engines[path].render(self)
-      end
-    end
-  end
-end

data/lib/rggen/output_base/verilog_utility.rb

@@ -1,69 +0,0 @@
-module RgGen
-  module OutputBase
-    module VerilogUtility
-      private
-
-      def create_identifier(name)
-        Identifier.new(name)
-      end
-
-      def create_declaration(declaration_type, attributes)
-        Declaration.new(declaration_type, attributes)
-      end
-
-      def module_definition(name, &body)
-        ModuleDefinition.new(name, &body).to_code
-      end
-
-      def package_definition(name, &body)
-        PackageDefinition.new(name, &body).to_code
-      end
-
-      def class_definition(name, &body)
-        ClassDefinition.new(name, &body).to_code
-      end
-
-      def function_definition(name, &body)
-        SubroutineDefinition.new(:function, name, &body).to_code
-      end
-
-      def argument(name, attributes)
-        attributes[:name] = name
-        create_declaration(:port, attributes)
-      end
-
-      def assign(lhs, rhs)
-        "assign #{lhs} = #{rhs};"
-      end
-
-      def subroutine_call(subroutine, arguments = nil)
-        "#{subroutine}(#{Array(arguments).join(', ')})"
-      end
-
-      def concat(expression_or_expressions)
-        "{#{Array(expression_or_expressions).join(', ')}}"
-      end
-
-      def array(expression_or_expressions)
-        "'#{concat(expression_or_expressions)}"
-      end
-
-      def string(expression)
-        "\"#{expression}\""
-      end
-
-      def bin(value, width)
-        format("%d'b%0*b", width, width, value)
-      end
-
-      def dec(value, width)
-        format("%d'd%d", width, value)
-      end
-
-      def hex(value, width)
-        print_width = (width + 3) / 4
-        format("%d'h%0*x", width, print_width, value)
-      end
-    end
-  end
-end

data/lib/rggen/output_base/verilog_utility/class_definition.rb

@@ -1,58 +0,0 @@
-module RgGen
-  module OutputBase
-    module VerilogUtility
-      class ClassDefinition < StructureDefinition
-        attr_setter :base
-        attr_setter :parameters
-        attr_setter :variables
-
-        def to_code
-          bodies.unshift(variables_declarations) if variables?
-          super
-        end
-
-        private
-
-        def header_code
-          code_block do |code|
-            code << :class << space   << @name
-            paraemter_declarations(code) if parameters?
-            code << space  <<:extends << space << @base unless @base.nil?
-            code << semicolon
-          end
-        end
-
-        def footer_code
-          :endclass
-        end
-
-        def parameters?
-          !(@parameters.nil? || @parameters.empty?)
-        end
-
-        def variables?
-          !(@variables.nil? || @variables.empty?)
-        end
-
-        def paraemter_declarations(code)
-          wrap(code, '#(', ')') do
-            indent(code, 2) do
-              @parameters.each_with_index do |d, i|
-                code << comma << nl if i > 0
-                code << d
-              end
-            end
-          end
-        end
-
-        def variables_declarations
-          lambda do |code|
-            variables.each do |variable|
-              code << variable << semicolon << nl
-            end
-          end
-        end
-      end
-    end
-  end
-end

data/lib/rggen/output_base/verilog_utility/declaration.rb

@@ -1,68 +0,0 @@
-module RgGen
-  module OutputBase
-    module VerilogUtility
-      class Declaration
-        def initialize(declation_type, attributes)
-          @declation_type = declation_type
-          @attributes     = attributes
-        end
-
-        def to_s
-          code_snippets.join(' ')
-        end
-
-        private
-
-        def code_snippets
-          [
-            random_or_direction_or_parameter_type,
-            data_type,
-            width,
-            identifier,
-            default_value_assignment
-          ].select(&:itself)
-        end
-
-        def random_or_direction_or_parameter_type
-          {
-            variable:  @attributes[:random] && :rand,
-            port:      @attributes[:direction],
-            parameter: @attributes[:parameter_type]
-          }[@declation_type]
-        end
-
-        def data_type
-          @attributes[:data_type]
-        end
-
-        def width
-          return unless vector?
-          "[#{(@attributes[:width] || 1) - 1}:0]"
-        end
-
-        def identifier
-          "#{@attributes[:name]}#{dimensions}"
-        end
-
-        def dimensions
-          return if @attributes[:dimensions].nil?
-          @attributes[:dimensions].map { |dimension| "[#{dimension}]" }.join
-        end
-
-        def default_value_assignment
-          return if @attributes[:default].nil?
-          "= #{@attributes[:default]}"
-        end
-
-        def parameter?
-          @declation_type == :parameter
-        end
-
-        def vector?
-          return true if @attributes[:vector]
-          @attributes[:width] && (parameter? || (@attributes[:width] > 1))
-        end
-      end
-    end
-  end
-end

data/lib/rggen/output_base/verilog_utility/identifier.rb

@@ -1,29 +0,0 @@
-module RgGen
-  module OutputBase
-    module VerilogUtility
-      class Identifier
-        def initialize(name)
-          @name = name
-        end
-
-        def to_s
-          @name.to_s
-        end
-
-        def [](indexes_or_msb, lsb = indexes_or_msb)
-          if indexes_or_msb.nil?
-            self
-          elsif indexes_or_msb.is_a?(Array)
-            indexes_or_msb.inject(self) do |identifer, index|
-              identifer[index]
-            end
-          elsif indexes_or_msb == lsb
-            Identifier.new("#{@name}[#{indexes_or_msb}]")
-          else
-            Identifier.new("#{@name}[#{indexes_or_msb}:#{lsb}]")
-          end
-        end
-      end
-    end
-  end
-end

data/lib/rggen/output_base/verilog_utility/module_definition.rb

@@ -1,73 +0,0 @@
-module RgGen
-  module OutputBase
-    module VerilogUtility
-      class ModuleDefinition < StructureDefinition
-        attr_setter :parameters
-        attr_setter :ports
-        attr_setter :signals
-
-        def to_code
-          bodies.unshift(signal_declarations) if signals?
-          super
-        end
-
-        private
-
-        def header_code
-          code_block do |code|
-            code << :module << space << @name << space
-            parameter_declarations(code)
-            port_declarations(code)
-            code << semicolon
-          end
-        end
-
-        def footer_code
-          :endmodule
-        end
-
-        def parameters?
-          !(@parameters.nil? || @parameters.empty?)
-        end
-
-        def ports?
-          !(@ports.nil? || @ports.empty?)
-        end
-
-        def signals?
-          !(@signals.nil? || @signals.empty?)
-        end
-
-        def parameter_declarations(code)
-          return unless parameters?
-          wrap(code, '#(', ')') do
-            declarations(@parameters, code)
-          end
-        end
-
-        def port_declarations(code)
-          wrap(code, '(', ')') do
-            declarations(@ports, code) if ports?
-          end
-        end
-
-        def signal_declarations
-          lambda do |code|
-            signals.each do |signal|
-              code << signal << semicolon << nl
-            end
-          end
-        end
-
-        def declarations(list, code)
-          indent(code, 2) do
-            list.each_with_index do |d, i|
-              code << comma << nl if i > 0
-              code << d
-            end
-          end
-        end
-      end
-    end
-  end
-end

data/lib/rggen/output_base/verilog_utility/package_definition.rb

@@ -1,67 +0,0 @@
-module RgGen
-  module OutputBase
-    module VerilogUtility
-      class PackageDefinition < StructureDefinition
-        ImportedPackage = Struct.new(:name, :items) do
-          def to_s
-            "import #{import_items.join(', ')};"
-          end
-
-          def import_items
-            (((items.nil? || items.empty?) && [:*]) || items).map do |item|
-              "#{name}::#{item}"
-            end
-          end
-        end
-
-        def import_package(name, items = nil)
-          import_packages << ImportedPackage.new(name, items)
-        end
-
-        def include_file(name)
-          include_files << "`include #{name.to_s.quote}"
-        end
-
-        def to_code
-          bodies.unshift(include_fiels_code ) unless @include_files.nil?
-          bodies.unshift(import_packges_code) unless @import_packages.nil?
-          super
-        end
-
-        private
-
-        def header_code
-          "package #{@name};"
-        end
-
-        def footer_code
-          :endpackage
-        end
-
-        def import_packages
-          @import_packages ||= []
-        end
-
-        def include_files
-          @include_files ||= []
-        end
-
-        def import_packges_code
-          lambda do |code|
-            import_packages.each do |package|
-              code << package << nl
-            end
-          end
-        end
-
-        def include_fiels_code
-          lambda do |code|
-            include_files.each do |file|
-              code << file << nl
-            end
-          end
-        end
-      end
-    end
-  end
-end