rggen 0.4.4 → 0.5.1

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Files changed (107) hide show
  1. checksums.yaml +4 -4
  2. data/LICENSE.txt +1 -1
  3. data/README.md +3 -2
  4. data/c/rggen.h +17 -0
  5. data/lib/rggen.rb +7 -16
  6. data/lib/rggen/base/item_factory.rb +2 -0
  7. data/lib/rggen/builtins.rb +15 -13
  8. data/lib/rggen/builtins/bit_field/{reserved.rb → types/reserved.rb} +0 -0
  9. data/lib/rggen/builtins/bit_field/{ro.erb → types/ro.erb} +0 -0
  10. data/lib/rggen/builtins/bit_field/{ro.rb → types/ro.rb} +0 -0
  11. data/lib/rggen/builtins/bit_field/{rw.erb → types/rw.erb} +0 -0
  12. data/lib/rggen/builtins/bit_field/{rw.rb → types/rw.rb} +0 -0
  13. data/lib/rggen/builtins/bit_field/{rwl_rwe.erb → types/rwl_rwe.erb} +0 -0
  14. data/lib/rggen/builtins/bit_field/{rwl_rwe.rb → types/rwl_rwe.rb} +0 -0
  15. data/lib/rggen/builtins/bit_field/{w0c_w1c.erb → types/w0c_w1c.erb} +0 -0
  16. data/lib/rggen/builtins/bit_field/{w0c_w1c.rb → types/w0c_w1c.rb} +0 -0
  17. data/lib/rggen/builtins/bit_field/{w0s_w1s.erb → types/w0s_w1s.erb} +0 -0
  18. data/lib/rggen/builtins/bit_field/{w0s_w1s.rb → types/w0s_w1s.rb} +0 -0
  19. data/lib/rggen/builtins/bit_field/{wo.rb → types/wo.rb} +0 -0
  20. data/lib/rggen/builtins/register/address_decoder.erb +9 -9
  21. data/lib/rggen/builtins/register/address_decoder.rb +24 -24
  22. data/lib/rggen/builtins/register/array.rb +0 -22
  23. data/lib/rggen/builtins/register/bus_exporter.rb +10 -2
  24. data/lib/rggen/builtins/register/indirect_index_configurator.rb +54 -0
  25. data/lib/rggen/builtins/register/offset_address.rb +21 -15
  26. data/lib/rggen/builtins/register/read_data.rb +1 -1
  27. data/lib/rggen/builtins/register/reg_model.rb +5 -5
  28. data/lib/rggen/builtins/register/sub_block_model.rb +1 -1
  29. data/lib/rggen/builtins/register/type.rb +207 -0
  30. data/lib/rggen/builtins/register/types/external.rb +15 -0
  31. data/lib/rggen/builtins/register/types/indirect.rb +134 -0
  32. data/lib/rggen/builtins/register/uniqueness_validator.rb +10 -7
  33. data/lib/rggen/builtins/register_block/address_struct.rb +56 -0
  34. data/lib/rggen/builtins/register_block/c_header_file.rb +15 -0
  35. data/lib/rggen/builtins/register_block/{apb.erb → host_ifs/apb.erb} +0 -0
  36. data/lib/rggen/builtins/register_block/{apb.rb → host_ifs/apb.rb} +0 -0
  37. data/lib/rggen/builtins/register_block/{axi4lite.erb → host_ifs/axi4lite.erb} +0 -0
  38. data/lib/rggen/builtins/register_block/{axi4lite.rb → host_ifs/axi4lite.rb} +0 -0
  39. data/lib/rggen/builtins/register_block/ral_package.rb +6 -1
  40. data/lib/rggen/builtins/register_block/response_mux.rb +2 -2
  41. data/lib/rggen/builtins/register_block/top_module.rb +5 -1
  42. data/lib/rggen/core_components.rb +25 -0
  43. data/lib/rggen/core_components/c_header/item.rb +8 -0
  44. data/lib/rggen/core_components/c_header/setup.rb +19 -0
  45. data/lib/rggen/core_components/c_utility.rb +19 -0
  46. data/lib/rggen/core_components/c_utility/data_structure_definition.rb +62 -0
  47. data/lib/rggen/core_components/c_utility/source_file.rb +10 -0
  48. data/lib/rggen/core_components/c_utility/variable_declaration.rb +35 -0
  49. data/lib/rggen/core_components/code_utility.rb +56 -0
  50. data/lib/rggen/{output_base → core_components/code_utility}/code_block.rb +1 -1
  51. data/lib/rggen/{output_base → core_components/code_utility}/line.rb +1 -1
  52. data/lib/rggen/core_components/code_utility/source_file.rb +97 -0
  53. data/lib/rggen/core_components/erb_engine.rb +15 -0
  54. data/lib/rggen/core_components/ral/item.rb +2 -1
  55. data/lib/rggen/core_components/register_map/generic_map.rb +3 -1
  56. data/lib/rggen/core_components/rtl/item.rb +2 -1
  57. data/lib/rggen/core_components/verilog_utility.rb +69 -0
  58. data/lib/rggen/core_components/verilog_utility/class_definition.rb +56 -0
  59. data/lib/rggen/core_components/verilog_utility/declaration.rb +66 -0
  60. data/lib/rggen/core_components/verilog_utility/identifier.rb +27 -0
  61. data/lib/rggen/core_components/verilog_utility/module_definition.rb +71 -0
  62. data/lib/rggen/core_components/verilog_utility/package_definition.rb +65 -0
  63. data/lib/rggen/core_components/verilog_utility/source_file.rb +10 -0
  64. data/lib/rggen/core_components/verilog_utility/structure_definition.rb +50 -0
  65. data/lib/rggen/core_components/verilog_utility/subroutine_definition.rb +41 -0
  66. data/lib/rggen/core_extensions/facets.rb +5 -0
  67. data/lib/rggen/generator.rb +19 -5
  68. data/lib/rggen/input_base/item.rb +6 -6
  69. data/lib/rggen/output_base/code_generator.rb +36 -0
  70. data/lib/rggen/output_base/component.rb +27 -41
  71. data/lib/rggen/output_base/file_writer.rb +36 -0
  72. data/lib/rggen/output_base/item.rb +34 -100
  73. data/lib/rggen/output_base/template_engine.rb +24 -0
  74. data/lib/rggen/rggen_home.rb +3 -0
  75. data/lib/rggen/version.rb +2 -2
  76. data/ral/rggen_ral_block.svh +1 -1
  77. data/ral/rggen_ral_indirect_reg.svh +193 -0
  78. data/ral/rggen_ral_map.svh +20 -20
  79. data/ral/rggen_ral_pkg.sv +1 -1
  80. data/rtl/register/rggen_address_decoder.sv +14 -14
  81. data/sample/sample.csv +21 -22
  82. data/sample/sample.xls +0 -0
  83. data/sample/sample.xlsx +0 -0
  84. data/sample/sample_0.h +17 -0
  85. data/sample/sample_0.sv +92 -92
  86. data/sample/sample_0_ral_pkg.sv +8 -5
  87. data/sample/sample_1.h +9 -0
  88. data/sample/sample_1.sv +27 -27
  89. data/sample/sample_1_ral_pkg.sv +3 -0
  90. data/sample/sample_setup.rb +4 -2
  91. data/setup/default.rb +4 -2
  92. metadata +53 -36
  93. data/lib/rggen/builtins/register/accessibility.rb +0 -23
  94. data/lib/rggen/builtins/register/external.rb +0 -42
  95. data/lib/rggen/builtins/register/shadow.rb +0 -130
  96. data/lib/rggen/builtins/register/shadow_index_configurator.rb +0 -56
  97. data/lib/rggen/output_base/code_utility.rb +0 -50
  98. data/lib/rggen/output_base/template_utility.rb +0 -29
  99. data/lib/rggen/output_base/verilog_utility.rb +0 -69
  100. data/lib/rggen/output_base/verilog_utility/class_definition.rb +0 -58
  101. data/lib/rggen/output_base/verilog_utility/declaration.rb +0 -68
  102. data/lib/rggen/output_base/verilog_utility/identifier.rb +0 -29
  103. data/lib/rggen/output_base/verilog_utility/module_definition.rb +0 -73
  104. data/lib/rggen/output_base/verilog_utility/package_definition.rb +0 -67
  105. data/lib/rggen/output_base/verilog_utility/structure_definition.rb +0 -52
  106. data/lib/rggen/output_base/verilog_utility/subroutine_definition.rb +0 -43
  107. data/ral/rggen_ral_shadow_reg.svh +0 -193
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.4.4
4
+ version: 0.5.1
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2016-11-14 00:00:00.000000000 Z
11
+ date: 2017-04-26 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: baby_erubis
@@ -110,7 +110,7 @@ dependencies:
110
110
  version: '0.35'
111
111
  description: |2
112
112
  RgGen is a code generation tool for SoC designers.
113
- It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
113
+ It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, C header file, from its register map document.
114
114
  Also RgGen is customizable so you can build your specific generate tool.
115
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  email:
116
116
  - taichi730@gmail.com
@@ -123,6 +123,7 @@ files:
123
123
  - LICENSE.txt
124
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  - README.md
125
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  - bin/rggen
126
+ - c/rggen.h
126
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  - lib/rggen.rb
127
128
  - lib/rggen/base/component.rb
128
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  - lib/rggen/base/component_factory.rb
@@ -146,19 +147,19 @@ files:
146
147
  - lib/rggen/builtins/bit_field/initial_value.rb
147
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  - lib/rggen/builtins/bit_field/name.rb
148
149
  - lib/rggen/builtins/bit_field/reference.rb
149
- - lib/rggen/builtins/bit_field/reserved.rb
150
- - lib/rggen/builtins/bit_field/ro.erb
151
- - lib/rggen/builtins/bit_field/ro.rb
152
- - lib/rggen/builtins/bit_field/rw.erb
153
- - lib/rggen/builtins/bit_field/rw.rb
154
- - lib/rggen/builtins/bit_field/rwl_rwe.erb
155
- - lib/rggen/builtins/bit_field/rwl_rwe.rb
156
150
  - lib/rggen/builtins/bit_field/type.rb
157
- - lib/rggen/builtins/bit_field/w0c_w1c.erb
158
- - lib/rggen/builtins/bit_field/w0c_w1c.rb
159
- - lib/rggen/builtins/bit_field/w0s_w1s.erb
160
- - lib/rggen/builtins/bit_field/w0s_w1s.rb
161
- - lib/rggen/builtins/bit_field/wo.rb
151
+ - lib/rggen/builtins/bit_field/types/reserved.rb
152
+ - lib/rggen/builtins/bit_field/types/ro.erb
153
+ - lib/rggen/builtins/bit_field/types/ro.rb
154
+ - lib/rggen/builtins/bit_field/types/rw.erb
155
+ - lib/rggen/builtins/bit_field/types/rw.rb
156
+ - lib/rggen/builtins/bit_field/types/rwl_rwe.erb
157
+ - lib/rggen/builtins/bit_field/types/rwl_rwe.rb
158
+ - lib/rggen/builtins/bit_field/types/w0c_w1c.erb
159
+ - lib/rggen/builtins/bit_field/types/w0c_w1c.rb
160
+ - lib/rggen/builtins/bit_field/types/w0s_w1s.erb
161
+ - lib/rggen/builtins/bit_field/types/w0s_w1s.rb
162
+ - lib/rggen/builtins/bit_field/types/wo.rb
162
163
  - lib/rggen/builtins/global/address_width.rb
163
164
  - lib/rggen/builtins/global/data_width.rb
164
165
  - lib/rggen/builtins/loaders/configuration/json_loader.rb
@@ -166,34 +167,36 @@ files:
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  - lib/rggen/builtins/loaders/register_map/csv_loader.rb
167
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  - lib/rggen/builtins/loaders/register_map/xls_loader.rb
168
169
  - lib/rggen/builtins/loaders/register_map/xlsx_ods_loader.rb
169
- - lib/rggen/builtins/register/accessibility.rb
170
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  - lib/rggen/builtins/register/address_decoder.erb
171
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  - lib/rggen/builtins/register/address_decoder.rb
172
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  - lib/rggen/builtins/register/array.rb
173
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  - lib/rggen/builtins/register/bus_exporter.erb
174
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  - lib/rggen/builtins/register/bus_exporter.rb
175
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  - lib/rggen/builtins/register/constructor.rb
176
- - lib/rggen/builtins/register/external.rb
177
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  - lib/rggen/builtins/register/field_model_creator.rb
177
+ - lib/rggen/builtins/register/indirect_index_configurator.rb
178
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  - lib/rggen/builtins/register/name.rb
179
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  - lib/rggen/builtins/register/offset_address.rb
180
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  - lib/rggen/builtins/register/read_data.rb
181
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  - lib/rggen/builtins/register/reg_model.rb
182
- - lib/rggen/builtins/register/shadow.rb
183
- - lib/rggen/builtins/register/shadow_index_configurator.rb
184
182
  - lib/rggen/builtins/register/sub_block_model.rb
183
+ - lib/rggen/builtins/register/type.rb
184
+ - lib/rggen/builtins/register/types/external.rb
185
+ - lib/rggen/builtins/register/types/indirect.rb
185
186
  - lib/rggen/builtins/register/uniqueness_validator.rb
186
- - lib/rggen/builtins/register_block/apb.erb
187
- - lib/rggen/builtins/register_block/apb.rb
188
- - lib/rggen/builtins/register_block/axi4lite.erb
189
- - lib/rggen/builtins/register_block/axi4lite.rb
187
+ - lib/rggen/builtins/register_block/address_struct.rb
190
188
  - lib/rggen/builtins/register_block/base_address.rb
191
189
  - lib/rggen/builtins/register_block/block_model.rb
192
190
  - lib/rggen/builtins/register_block/byte_size.rb
191
+ - lib/rggen/builtins/register_block/c_header_file.rb
193
192
  - lib/rggen/builtins/register_block/clock_reset.rb
194
193
  - lib/rggen/builtins/register_block/constructor.rb
195
194
  - lib/rggen/builtins/register_block/default_map_creator.rb
196
195
  - lib/rggen/builtins/register_block/host_if.rb
196
+ - lib/rggen/builtins/register_block/host_ifs/apb.erb
197
+ - lib/rggen/builtins/register_block/host_ifs/apb.rb
198
+ - lib/rggen/builtins/register_block/host_ifs/axi4lite.erb
199
+ - lib/rggen/builtins/register_block/host_ifs/axi4lite.rb
197
200
  - lib/rggen/builtins/register_block/irq_controller.erb
198
201
  - lib/rggen/builtins/register_block/irq_controller.rb
199
202
  - lib/rggen/builtins/register_block/name.rb
@@ -204,11 +207,22 @@ files:
204
207
  - lib/rggen/builtins/register_block/top_module.rb
205
208
  - lib/rggen/commands.rb
206
209
  - lib/rggen/core_components.rb
210
+ - lib/rggen/core_components/c_header/item.rb
211
+ - lib/rggen/core_components/c_header/setup.rb
212
+ - lib/rggen/core_components/c_utility.rb
213
+ - lib/rggen/core_components/c_utility/data_structure_definition.rb
214
+ - lib/rggen/core_components/c_utility/source_file.rb
215
+ - lib/rggen/core_components/c_utility/variable_declaration.rb
216
+ - lib/rggen/core_components/code_utility.rb
217
+ - lib/rggen/core_components/code_utility/code_block.rb
218
+ - lib/rggen/core_components/code_utility/line.rb
219
+ - lib/rggen/core_components/code_utility/source_file.rb
207
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  - lib/rggen/core_components/configuration/configuration_factory.rb
208
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  - lib/rggen/core_components/configuration/item.rb
209
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  - lib/rggen/core_components/configuration/item_factory.rb
210
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  - lib/rggen/core_components/configuration/raise_error.rb
211
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  - lib/rggen/core_components/configuration/setup.rb
225
+ - lib/rggen/core_components/erb_engine.rb
212
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  - lib/rggen/core_components/ral/component.rb
213
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  - lib/rggen/core_components/ral/item.rb
214
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  - lib/rggen/core_components/ral/setup.rb
@@ -227,6 +241,15 @@ files:
227
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  - lib/rggen/core_components/rtl/component.rb
228
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  - lib/rggen/core_components/rtl/item.rb
229
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  - lib/rggen/core_components/rtl/setup.rb
244
+ - lib/rggen/core_components/verilog_utility.rb
245
+ - lib/rggen/core_components/verilog_utility/class_definition.rb
246
+ - lib/rggen/core_components/verilog_utility/declaration.rb
247
+ - lib/rggen/core_components/verilog_utility/identifier.rb
248
+ - lib/rggen/core_components/verilog_utility/module_definition.rb
249
+ - lib/rggen/core_components/verilog_utility/package_definition.rb
250
+ - lib/rggen/core_components/verilog_utility/source_file.rb
251
+ - lib/rggen/core_components/verilog_utility/structure_definition.rb
252
+ - lib/rggen/core_components/verilog_utility/subroutine_definition.rb
230
253
  - lib/rggen/core_extensions/array.rb
231
254
  - lib/rggen/core_extensions/facets.rb
232
255
  - lib/rggen/core_extensions/forwardable.rb
@@ -240,32 +263,24 @@ files:
240
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  - lib/rggen/input_base/item_factory.rb
241
264
  - lib/rggen/input_base/loader.rb
242
265
  - lib/rggen/input_base/regexp_patterns.rb
243
- - lib/rggen/output_base/code_block.rb
244
- - lib/rggen/output_base/code_utility.rb
266
+ - lib/rggen/output_base/code_generator.rb
245
267
  - lib/rggen/output_base/component.rb
246
268
  - lib/rggen/output_base/component_factory.rb
269
+ - lib/rggen/output_base/file_writer.rb
247
270
  - lib/rggen/output_base/item.rb
248
271
  - lib/rggen/output_base/item_factory.rb
249
- - lib/rggen/output_base/line.rb
250
- - lib/rggen/output_base/template_utility.rb
251
- - lib/rggen/output_base/verilog_utility.rb
252
- - lib/rggen/output_base/verilog_utility/class_definition.rb
253
- - lib/rggen/output_base/verilog_utility/declaration.rb
254
- - lib/rggen/output_base/verilog_utility/identifier.rb
255
- - lib/rggen/output_base/verilog_utility/module_definition.rb
256
- - lib/rggen/output_base/verilog_utility/package_definition.rb
257
- - lib/rggen/output_base/verilog_utility/structure_definition.rb
258
- - lib/rggen/output_base/verilog_utility/subroutine_definition.rb
272
+ - lib/rggen/output_base/template_engine.rb
273
+ - lib/rggen/rggen_home.rb
259
274
  - lib/rggen/version.rb
260
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  - ral/compile.f
261
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  - ral/rggen_ral_block.svh
262
277
  - ral/rggen_ral_field.svh
263
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  - ral/rggen_ral_field_rwl_rwe.svh
279
+ - ral/rggen_ral_indirect_reg.svh
264
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  - ral/rggen_ral_macros.svh
265
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  - ral/rggen_ral_map.svh
266
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  - ral/rggen_ral_pkg.sv
267
283
  - ral/rggen_ral_reg.svh
268
- - ral/rggen_ral_shadow_reg.svh
269
284
  - rtl/bit_field/rggen_bit_field_common.svh
270
285
  - rtl/bit_field/rggen_bit_field_ro.sv
271
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  - rtl/bit_field/rggen_bit_field_rw.sv
@@ -284,8 +299,10 @@ files:
284
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  - sample/sample.xls
285
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  - sample/sample.xlsx
286
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  - sample/sample.yaml
302
+ - sample/sample_0.h
287
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  - sample/sample_0.sv
288
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  - sample/sample_0_ral_pkg.sv
305
+ - sample/sample_1.h
289
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  - sample/sample_1.sv
290
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  - sample/sample_1_ral_pkg.sv
291
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  - sample/sample_setup.rb
@@ -1,23 +0,0 @@
1
- simple_item :register, :accessibility do
2
- register_map do
3
- field :readable? do
4
- register.external? || register.bit_fields.any?(&:readable?)
5
- end
6
-
7
- field :writable? do
8
- register.external? || register.bit_fields.any?(&:writable?)
9
- end
10
-
11
- field :read_only? do
12
- readable? && !writable?
13
- end
14
-
15
- field :write_only? do
16
- writable? && !readable?
17
- end
18
-
19
- field :reserved? do
20
- !register.external? && register.bit_fields.all?(&:reserved?)
21
- end
22
- end
23
- end
@@ -1,42 +0,0 @@
1
- simple_item :register, :external do
2
- register_map do
3
- field :external?
4
- field :internal? do
5
- !external?
6
- end
7
-
8
- input_pattern %r{(true)|(false)|()}i, convert_to_string: true
9
-
10
- build do |cell|
11
- @external = parse(cell)
12
- register.need_no_children if external?
13
- end
14
-
15
- validate do
16
- if (register.array? || register.shadow?) && external?
17
- error 'not use array/shadow and ' \
18
- 'external register on the same register'
19
- end
20
- end
21
-
22
- def parse(cell)
23
- if pattern_matched?
24
- captures.first.not_nil?
25
- else
26
- error "invalid value for 'external': #{cell.inspect}"
27
- end
28
- end
29
- end
30
-
31
- rtl do
32
- export :external_index
33
-
34
- def external_index
35
- external_registers.index(&register.method(:equal?))
36
- end
37
-
38
- def external_registers
39
- register_block.registers.select(&:external?)
40
- end
41
- end
42
- end
@@ -1,130 +0,0 @@
1
- simple_item :register, :shadow do
2
- register_map do
3
- field :shadow?
4
- field :shadow_indexes
5
-
6
- input_pattern %r{(#{variable_name})(?::(#{number}))?}
7
-
8
- build do |cell|
9
- @shadow_indexes = parse_shadow_indexes(cell)
10
- @shadow = @shadow_indexes.not_nil?
11
- end
12
-
13
- validate do
14
- next unless shadow?
15
- check_using_shadow_register_only
16
- check_index_fields
17
- check_size_of_array_index_fields
18
- check_array_index_values
19
- check_specific_value_index_values
20
- end
21
-
22
- define_struct :shadow_index_entry, [:name, :value] do
23
- def initialize(name, value)
24
- self.name = name
25
- self.value = value && Integer(value)
26
- end
27
-
28
- def ==(other)
29
- return false unless name == other.name
30
- return true if [value, other.value].any?(&:nil?)
31
- value == other.value
32
- end
33
- end
34
-
35
- def parse_shadow_indexes(cell)
36
- return nil if cell.nil? || cell.empty?
37
- cell.split(/[,\n]/).map do |entry|
38
- if pattern_match(entry)
39
- shadow_index_entry.new(captures[0], captures[1])
40
- else
41
- error "invalid value for shadow index: #{cell.inspect}"
42
- end
43
- end
44
- end
45
-
46
- def check_using_shadow_register_only
47
- return unless register.multiple? && register.array?
48
- error 'not use real array and shadow register on the same register'
49
- end
50
-
51
- def check_index_fields
52
- shadow_indexes.each do |entry|
53
- case
54
- when use_same_index_field_more_than_once?(entry.name)
55
- error "not use the same index field more than once: #{entry.name}"
56
- when not_find_shadow_index_field?(entry)
57
- error "no such shadow index field: #{entry.name}"
58
- when use_own_bit_field?(entry)
59
- error 'own bit field is specified for shadow index field:' \
60
- " #{entry.name}"
61
- when use_arrayed_bit_field?(entry)
62
- error 'arrayed bit field is specified for shadow index field:' \
63
- " #{entry.name}"
64
- end
65
- end
66
- end
67
-
68
- def use_same_index_field_more_than_once?(name)
69
- shadow_indexes.count { |entry| entry.name == name } > 1
70
- end
71
-
72
- def not_find_shadow_index_field?(entry)
73
- shadow_index_bit_field[entry.name].nil?
74
- end
75
-
76
- def use_own_bit_field?(entry)
77
- register.bit_fields.map(&:name).include?(entry.name)
78
- end
79
-
80
- def use_arrayed_bit_field?(entry)
81
- shadow_index_bit_field[entry.name].register.array?
82
- end
83
-
84
- def check_size_of_array_index_fields
85
- return if size_of_dimensions == array_indexes.size
86
- error 'not match number of array dimensions and' \
87
- ' number of array index fields'
88
- end
89
-
90
- def check_array_index_values
91
- array_indexes.each_with_index do |entry, i|
92
- next if register.dimensions[i] <= (maximum_value(entry.name) + 1)
93
- error "exceeds maximum array size specified by #{entry.name}" \
94
- "(#{maximum_value(entry.name) + 1}): #{register.dimensions[i]}"
95
- end
96
- end
97
-
98
- def check_specific_value_index_values
99
- specific_value_indexes.each do |entry|
100
- next if entry.value <= maximum_value(entry.name)
101
- error "exceeds maximum value of #{entry.name}" \
102
- "(#{maximum_value(entry.name)}): #{entry.value}"
103
- end
104
- end
105
-
106
- def size_of_dimensions
107
- (register.array? && register.dimensions.size) || 0
108
- end
109
-
110
- def array_indexes
111
- shadow_indexes.select { |entry| entry.value.nil? }
112
- end
113
-
114
- def specific_value_indexes
115
- shadow_indexes.select { |entry| entry.value.not_nil? }
116
- end
117
-
118
- def maximum_value(index_name)
119
- 2**shadow_index_bit_field[index_name].width - 1
120
- end
121
-
122
- def shadow_index_bit_field
123
- @shadow_index_bit_field ||= Hash.new do |hash, index_name|
124
- hash[index_name] = register_block.bit_fields.find_by(
125
- name: index_name, reserved?: false
126
- )
127
- end
128
- end
129
- end
130
- end
@@ -1,56 +0,0 @@
1
- simple_item :register, :shadow_index_configurator do
2
- ral do
3
- available? do
4
- register.shadow?
5
- end
6
-
7
- generate_code :reg_model_item do
8
- function_definition :configure_shadow_indexes do |f|
9
- f.return_type :void
10
- f.body { |code| function_body(code) }
11
- end
12
- end
13
-
14
- def function_body(code)
15
- register.shadow_indexes.each do |shadow_index|
16
- code << subroutine_call(:set_shadow_index, arguments(shadow_index))
17
- code << semicolon
18
- code << nl
19
- end
20
- end
21
-
22
- def arguments(shadow_index)
23
- [
24
- parent_name(shadow_index),
25
- index_name(shadow_index),
26
- index_value(shadow_index)
27
- ]
28
- end
29
-
30
- def parent_name(shadow_index)
31
- parent_register = fild_parent_register(shadow_index.name)
32
- string(parent_register.name)
33
- end
34
-
35
- def fild_parent_register(index_name)
36
- register_block.bit_fields.find_by(name: index_name).register
37
- end
38
-
39
- def index_name(shadow_index)
40
- string(shadow_index.name)
41
- end
42
-
43
- def index_value(shadow_index)
44
- if shadow_index.value
45
- shadow_index.value
46
- else
47
- "indexes[#{array_index}]"
48
- end
49
- end
50
-
51
- def array_index
52
- @array_index ||= -1
53
- @array_index += 1
54
- end
55
- end
56
- end