rggen 0.4.4 → 0.5.1

data/sample/sample_0.h

@@ -0,0 +1,17 @@
+#ifndef SAMPLE_0_H
+#define SAMPLE_0_H
+#include "rggen.h"
+typedef struct {
+  rggen_uint32 register_0;
+  rggen_uint32 register_1;
+  rggen_uint32 register_2;
+  rggen_uint32 register_3;
+  rggen_uint32 register_4[4];
+  rggen_uint32 register_5;
+  rggen_uint32 register_6;
+  rggen_uint32 register_7;
+  rggen_uint32 register_8;
+  rggen_uint32 __dummy_0[20];
+  RGGEN_EXTERNAL_REGISTERS(128, REGISTER_9) register_9;
+} s_sample_0_address_struct;
+#endif

data/sample/sample_0.sv

@@ -65,7 +65,7 @@ module sample_0 (
   logic [31:0] bit_field_3_0_value;
   logic [15:0] bit_field_4_0_value[4];
   logic [15:0] bit_field_4_1_value[4];
-  logic [32:0] register_5_shadow_index[2][4];
+  logic [32:0] register_5_indirect_index[2][4];
   logic [15:0] bit_field_5_0_value[2][4];
   logic [15:0] bit_field_5_1_value[2][4];
   logic bit_field_6_0_value;
@@ -132,16 +132,16 @@ module sample_0 (
     .o_irq  (o_irq)
   );
   rggen_address_decoder #(
-    .ADDRESS_WIDTH      (6),
-    .START_ADDRESS      (6'h00),
-    .END_ADDRESS        (6'h00),
-    .USE_SHADOW_INDEX   (0),
-    .SHADOW_INDEX_WIDTH (1),
-    .SHADOW_INDEX_VALUE (1'h0)
+    .ADDRESS_WIDTH        (6),
+    .START_ADDRESS        (6'h00),
+    .END_ADDRESS          (6'h00),
+    .INDIRECT_REGISTER    (0),
+    .INDIRECT_INDEX_WIDTH (1),
+    .INDIRECT_INDEX_VALUE (1'h0)
   ) u_register_0_address_decoder (
-    .i_address      (address[7:2]),
-    .i_shadow_index (1'h0),
-    .o_select       (register_select[0])
+    .i_address        (address[7:2]),
+    .i_indirect_index (1'h0),
+    .o_select         (register_select[0])
   );
   assign register_read_data[0] = {bit_field_0_0_value, bit_field_0_1_value};
   assign o_bit_field_0_0 = bit_field_0_0_value;
@@ -173,16 +173,16 @@ module sample_0 (
     .o_value          (bit_field_0_1_value)
   );
   rggen_address_decoder #(
-    .ADDRESS_WIDTH      (6),
-    .START_ADDRESS      (6'h01),
-    .END_ADDRESS        (6'h01),
-    .USE_SHADOW_INDEX   (0),
-    .SHADOW_INDEX_WIDTH (1),
-    .SHADOW_INDEX_VALUE (1'h0)
+    .ADDRESS_WIDTH        (6),
+    .START_ADDRESS        (6'h01),
+    .END_ADDRESS          (6'h01),
+    .INDIRECT_REGISTER    (0),
+    .INDIRECT_INDEX_WIDTH (1),
+    .INDIRECT_INDEX_VALUE (1'h0)
   ) u_register_1_address_decoder (
-    .i_address      (address[7:2]),
-    .i_shadow_index (1'h0),
-    .o_select       (register_select[1])
+    .i_address        (address[7:2]),
+    .i_indirect_index (1'h0),
+    .o_select         (register_select[1])
   );
   assign register_read_data[1] = {bit_field_1_0_value};
   assign o_bit_field_1_0 = bit_field_1_0_value;
@@ -200,16 +200,16 @@ module sample_0 (
     .o_value          (bit_field_1_0_value)
   );
   rggen_address_decoder #(
-    .ADDRESS_WIDTH      (6),
-    .START_ADDRESS      (6'h02),
-    .END_ADDRESS        (6'h02),
-    .USE_SHADOW_INDEX   (0),
-    .SHADOW_INDEX_WIDTH (1),
-    .SHADOW_INDEX_VALUE (1'h0)
+    .ADDRESS_WIDTH        (6),
+    .START_ADDRESS        (6'h02),
+    .END_ADDRESS          (6'h02),
+    .INDIRECT_REGISTER    (0),
+    .INDIRECT_INDEX_WIDTH (1),
+    .INDIRECT_INDEX_VALUE (1'h0)
   ) u_register_2_address_decoder (
-    .i_address      (address[7:2]),
-    .i_shadow_index (1'h0),
-    .o_select       (register_select[2])
+    .i_address        (address[7:2]),
+    .i_indirect_index (1'h0),
+    .o_select         (register_select[2])
   );
   assign register_read_data[2] = {15'h0000, bit_field_2_0_value, 15'h0000, bit_field_2_1_value};
   rggen_bit_field_ro #(
@@ -233,16 +233,16 @@ module sample_0 (
     .o_value          (bit_field_2_1_value)
   );
   rggen_address_decoder #(
-    .ADDRESS_WIDTH      (6),
-    .START_ADDRESS      (6'h03),
-    .END_ADDRESS        (6'h03),
-    .USE_SHADOW_INDEX   (0),
-    .SHADOW_INDEX_WIDTH (1),
-    .SHADOW_INDEX_VALUE (1'h0)
+    .ADDRESS_WIDTH        (6),
+    .START_ADDRESS        (6'h03),
+    .END_ADDRESS          (6'h03),
+    .INDIRECT_REGISTER    (0),
+    .INDIRECT_INDEX_WIDTH (1),
+    .INDIRECT_INDEX_VALUE (1'h0)
   ) u_register_3_address_decoder (
-    .i_address      (address[7:2]),
-    .i_shadow_index (1'h0),
-    .o_select       (register_select[3])
+    .i_address        (address[7:2]),
+    .i_indirect_index (1'h0),
+    .o_select         (register_select[3])
   );
   assign register_read_data[3] = {bit_field_3_0_value};
   rggen_bit_field_ro #(
@@ -255,16 +255,16 @@ module sample_0 (
     genvar g_i;
     for (g_i = 0;g_i < 4;g_i++) begin : g
       rggen_address_decoder #(
-        .ADDRESS_WIDTH      (6),
-        .START_ADDRESS      (6'h04 + g_i),
-        .END_ADDRESS        (6'h04 + g_i),
-        .USE_SHADOW_INDEX   (0),
-        .SHADOW_INDEX_WIDTH (1),
-        .SHADOW_INDEX_VALUE (1'h0)
+        .ADDRESS_WIDTH        (6),
+        .START_ADDRESS        (6'h04 + g_i),
+        .END_ADDRESS          (6'h04 + g_i),
+        .INDIRECT_REGISTER    (0),
+        .INDIRECT_INDEX_WIDTH (1),
+        .INDIRECT_INDEX_VALUE (1'h0)
       ) u_register_4_address_decoder (
-        .i_address      (address[7:2]),
-        .i_shadow_index (1'h0),
-        .o_select       (register_select[4+g_i])
+        .i_address        (address[7:2]),
+        .i_indirect_index (1'h0),
+        .o_select         (register_select[4+g_i])
       );
       assign register_read_data[4+g_i] = {bit_field_4_0_value[g_i], bit_field_4_1_value[g_i]};
       rggen_bit_field_ro #(
@@ -293,18 +293,18 @@ module sample_0 (
     genvar g_i, g_j;
     for (g_i = 0;g_i < 2;g_i++) begin : g
       for (g_j = 0;g_j < 4;g_j++) begin : g
-        assign register_5_shadow_index[g_i][g_j] = {bit_field_2_1_value, bit_field_0_0_value, bit_field_0_1_value};
+        assign register_5_indirect_index[g_i][g_j] = {bit_field_2_1_value, bit_field_0_0_value, bit_field_0_1_value};
         rggen_address_decoder #(
-          .ADDRESS_WIDTH      (6),
-          .START_ADDRESS      (6'h08),
-          .END_ADDRESS        (6'h08),
-          .USE_SHADOW_INDEX   (1),
-          .SHADOW_INDEX_WIDTH (33),
-          .SHADOW_INDEX_VALUE ({1'h1, g_i[15:0], g_j[15:0]})
+          .ADDRESS_WIDTH        (6),
+          .START_ADDRESS        (6'h08),
+          .END_ADDRESS          (6'h08),
+          .INDIRECT_REGISTER    (1),
+          .INDIRECT_INDEX_WIDTH (33),
+          .INDIRECT_INDEX_VALUE ({1'h1, g_i[15:0], g_j[15:0]})
         ) u_register_5_address_decoder (
-          .i_address      (address[7:2]),
-          .i_shadow_index (register_5_shadow_index[g_i][g_j]),
-          .o_select       (register_select[8+4*g_i+g_j])
+          .i_address        (address[7:2]),
+          .i_indirect_index (register_5_indirect_index[g_i][g_j]),
+          .o_select         (register_select[8+4*g_i+g_j])
         );
         assign register_read_data[8+4*g_i+g_j] = {bit_field_5_0_value[g_i][g_j], bit_field_5_1_value[g_i][g_j]};
         rggen_bit_field_ro #(
@@ -331,16 +331,16 @@ module sample_0 (
     end
   end endgenerate
   rggen_address_decoder #(
-    .ADDRESS_WIDTH      (6),
-    .START_ADDRESS      (6'h09),
-    .END_ADDRESS        (6'h09),
-    .USE_SHADOW_INDEX   (0),
-    .SHADOW_INDEX_WIDTH (1),
-    .SHADOW_INDEX_VALUE (1'h0)
+    .ADDRESS_WIDTH        (6),
+    .START_ADDRESS        (6'h09),
+    .END_ADDRESS          (6'h09),
+    .INDIRECT_REGISTER    (0),
+    .INDIRECT_INDEX_WIDTH (1),
+    .INDIRECT_INDEX_VALUE (1'h0)
   ) u_register_6_address_decoder (
-    .i_address      (address[7:2]),
-    .i_shadow_index (1'h0),
-    .o_select       (register_select[16])
+    .i_address        (address[7:2]),
+    .i_indirect_index (1'h0),
+    .o_select         (register_select[16])
   );
   assign register_read_data[16] = {23'h000000, bit_field_6_0_value, 7'h00, bit_field_6_1_value};
   rggen_bit_field_w01s_w01c #(
@@ -376,16 +376,16 @@ module sample_0 (
     .o_value          (bit_field_6_1_value)
   );
   rggen_address_decoder #(
-    .ADDRESS_WIDTH      (6),
-    .START_ADDRESS      (6'h0a),
-    .END_ADDRESS        (6'h0a),
-    .USE_SHADOW_INDEX   (0),
-    .SHADOW_INDEX_WIDTH (1),
-    .SHADOW_INDEX_VALUE (1'h0)
+    .ADDRESS_WIDTH        (6),
+    .START_ADDRESS        (6'h0a),
+    .END_ADDRESS          (6'h0a),
+    .INDIRECT_REGISTER    (0),
+    .INDIRECT_INDEX_WIDTH (1),
+    .INDIRECT_INDEX_VALUE (1'h0)
   ) u_register_7_address_decoder (
-    .i_address      (address[7:2]),
-    .i_shadow_index (1'h0),
-    .o_select       (register_select[17])
+    .i_address        (address[7:2]),
+    .i_indirect_index (1'h0),
+    .o_select         (register_select[17])
   );
   assign register_read_data[17] = {23'h000000, bit_field_7_0_value, 7'h00, bit_field_7_1_value};
   assign o_bit_field_7_0 = bit_field_7_0_value;
@@ -423,16 +423,16 @@ module sample_0 (
     .o_value          (bit_field_7_1_value)
   );
   rggen_address_decoder #(
-    .ADDRESS_WIDTH      (6),
-    .START_ADDRESS      (6'h0b),
-    .END_ADDRESS        (6'h0b),
-    .USE_SHADOW_INDEX   (0),
-    .SHADOW_INDEX_WIDTH (1),
-    .SHADOW_INDEX_VALUE (1'h0)
+    .ADDRESS_WIDTH        (6),
+    .START_ADDRESS        (6'h0b),
+    .END_ADDRESS          (6'h0b),
+    .INDIRECT_REGISTER    (0),
+    .INDIRECT_INDEX_WIDTH (1),
+    .INDIRECT_INDEX_VALUE (1'h0)
   ) u_register_8_address_decoder (
-    .i_address      (address[7:2]),
-    .i_shadow_index (1'h0),
-    .o_select       (register_select[18])
+    .i_address        (address[7:2]),
+    .i_indirect_index (1'h0),
+    .o_select         (register_select[18])
   );
   assign register_read_data[18] = {bit_field_8_0_value, bit_field_8_1_value};
   assign o_bit_field_8_0 = bit_field_8_0_value;
@@ -468,16 +468,16 @@ module sample_0 (
     .o_value          (bit_field_8_1_value)
   );
   rggen_address_decoder #(
-    .ADDRESS_WIDTH      (6),
-    .START_ADDRESS      (6'h20),
-    .END_ADDRESS        (6'h3f),
-    .USE_SHADOW_INDEX   (0),
-    .SHADOW_INDEX_WIDTH (1),
-    .SHADOW_INDEX_VALUE (1'h0)
+    .ADDRESS_WIDTH        (6),
+    .START_ADDRESS        (6'h20),
+    .END_ADDRESS          (6'h3f),
+    .INDIRECT_REGISTER    (0),
+    .INDIRECT_INDEX_WIDTH (1),
+    .INDIRECT_INDEX_VALUE (1'h0)
   ) u_register_9_address_decoder (
-    .i_address      (address[7:2]),
-    .i_shadow_index (1'h0),
-    .o_select       (register_select[19])
+    .i_address        (address[7:2]),
+    .i_indirect_index (1'h0),
+    .o_select         (register_select[19])
   );
   assign external_register_select[0] = register_select[19];
   rggen_bus_exporter #(

data/sample/sample_0_ral_pkg.sv

@@ -1,3 +1,5 @@
+`ifndef SAMPLE_0_RAL_PKG_SV
+`define SAMPLE_0_RAL_PKG_SV
 package sample_0_ral_pkg;
   import uvm_pkg::*;
   import rggen_ral_pkg::*;
@@ -54,7 +56,7 @@ package sample_0_ral_pkg;
       `rggen_ral_create_field_model(bit_field_4_1, "bit_field_4_1", 16, 0, "RW", 0, 16'h0000, 1, "u_bit_field_4_1.value")
     endfunction
   endclass
-  class register_5_reg_model extends rggen_ral_shadow_reg;
+  class register_5_reg_model extends rggen_ral_indirect_reg;
     rand rggen_ral_field bit_field_5_0;
     rand rggen_ral_field bit_field_5_1;
     function new(string name = "register_5");
@@ -64,10 +66,10 @@ package sample_0_ral_pkg;
       `rggen_ral_create_field_model(bit_field_5_0, "bit_field_5_0", 16, 16, "RO", 0, 16'h0000, 0, "u_bit_field_5_0.i_value")
       `rggen_ral_create_field_model(bit_field_5_1, "bit_field_5_1", 16, 0, "RW", 0, 16'h0000, 1, "u_bit_field_5_1.value")
     endfunction
-    function void configure_shadow_indexes();
-      set_shadow_index("register_2", "bit_field_2_1", 1);
-      set_shadow_index("register_0", "bit_field_0_0", indexes[0]);
-      set_shadow_index("register_0", "bit_field_0_1", indexes[1]);
+    function void configure_indirect_indexes();
+      set_indirect_index("register_2", "bit_field_2_1", 1);
+      set_indirect_index("register_0", "bit_field_0_0", indexes[0]);
+      set_indirect_index("register_0", "bit_field_0_1", indexes[1]);
     endfunction
   endclass
   class register_6_reg_model extends rggen_ral_reg;
@@ -140,3 +142,4 @@ package sample_0_ral_pkg;
     endfunction
   endclass
 endpackage
+`endif

data/sample/sample_1.h

@@ -0,0 +1,9 @@
+#ifndef SAMPLE_1_H
+#define SAMPLE_1_H
+#include "rggen.h"
+typedef struct {
+  rggen_uint32 register_0;
+  rggen_uint32 register_1;
+  rggen_uint32 register_2;
+} s_sample_1_address_struct;
+#endif

data/sample/sample_1.sv

@@ -81,16 +81,16 @@ module sample_1 (
     .i_external_register_status ('{2'b00})
   );
   rggen_address_decoder #(
-    .ADDRESS_WIDTH      (5),
-    .START_ADDRESS      (5'h00),
-    .END_ADDRESS        (5'h00),
-    .USE_SHADOW_INDEX   (0),
-    .SHADOW_INDEX_WIDTH (1),
-    .SHADOW_INDEX_VALUE (1'h0)
+    .ADDRESS_WIDTH        (5),
+    .START_ADDRESS        (5'h00),
+    .END_ADDRESS          (5'h00),
+    .INDIRECT_REGISTER    (0),
+    .INDIRECT_INDEX_WIDTH (1),
+    .INDIRECT_INDEX_VALUE (1'h0)
   ) u_register_0_address_decoder (
-    .i_address      (address[6:2]),
-    .i_shadow_index (1'h0),
-    .o_select       (register_select[0])
+    .i_address        (address[6:2]),
+    .i_indirect_index (1'h0),
+    .o_select         (register_select[0])
   );
   assign register_read_data[0] = {bit_field_0_0_value, bit_field_0_1_value};
   assign o_bit_field_0_0 = bit_field_0_0_value;
@@ -114,16 +114,16 @@ module sample_1 (
     .o_value  (bit_field_0_1_value)
   );
   rggen_address_decoder #(
-    .ADDRESS_WIDTH      (5),
-    .START_ADDRESS      (5'h01),
-    .END_ADDRESS        (5'h01),
-    .USE_SHADOW_INDEX   (0),
-    .SHADOW_INDEX_WIDTH (1),
-    .SHADOW_INDEX_VALUE (1'h0)
+    .ADDRESS_WIDTH        (5),
+    .START_ADDRESS        (5'h01),
+    .END_ADDRESS          (5'h01),
+    .INDIRECT_REGISTER    (0),
+    .INDIRECT_INDEX_WIDTH (1),
+    .INDIRECT_INDEX_VALUE (1'h0)
   ) u_register_1_address_decoder (
-    .i_address      (address[6:2]),
-    .i_shadow_index (1'h0),
-    .o_select       (register_select[1])
+    .i_address        (address[6:2]),
+    .i_indirect_index (1'h0),
+    .o_select         (register_select[1])
   );
   assign register_read_data[1] = {bit_field_1_0_value};
   assign o_bit_field_1_0 = bit_field_1_0_value;
@@ -141,16 +141,16 @@ module sample_1 (
     .o_value          (bit_field_1_0_value)
   );
   rggen_address_decoder #(
-    .ADDRESS_WIDTH      (5),
-    .START_ADDRESS      (5'h02),
-    .END_ADDRESS        (5'h02),
-    .USE_SHADOW_INDEX   (0),
-    .SHADOW_INDEX_WIDTH (1),
-    .SHADOW_INDEX_VALUE (1'h0)
+    .ADDRESS_WIDTH        (5),
+    .START_ADDRESS        (5'h02),
+    .END_ADDRESS          (5'h02),
+    .INDIRECT_REGISTER    (0),
+    .INDIRECT_INDEX_WIDTH (1),
+    .INDIRECT_INDEX_VALUE (1'h0)
   ) u_register_2_address_decoder (
-    .i_address      (address[6:2]),
-    .i_shadow_index (1'h0),
-    .o_select       (register_select[2])
+    .i_address        (address[6:2]),
+    .i_indirect_index (1'h0),
+    .o_select         (register_select[2])
   );
   assign register_read_data[2] = {15'h0000, bit_field_2_0_value, 15'h0000, bit_field_2_1_value};
   rggen_bit_field_ro #(

data/sample/sample_1_ral_pkg.sv

@@ -1,3 +1,5 @@
+`ifndef SAMPLE_1_RAL_PKG_SV
+`define SAMPLE_1_RAL_PKG_SV
 package sample_1_ral_pkg;
   import uvm_pkg::*;
   import rggen_ral_pkg::*;
@@ -51,3 +53,4 @@ package sample_1_ral_pkg;
     endfunction
   endclass
 endpackage
+`endif

data/sample/sample_setup.rb

@@ -10,12 +10,14 @@ end
 
 enable :global        , [:data_width, :address_width]
 enable :register_block, [:name, :base_address]
-enable :register      , [:offset_address, :name, :array, :shadow, :external, :accessibility, :uniquness_validator]
+enable :register      , [:offset_address, :name, :array, :type, :uniquness_validator]
+enable :register      , :type, [:indirect, :external]
 enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
 enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :foo, :reserved]
 enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
 enable :register_block, :host_if, [:apb, :bar]
 enable :register      , [:address_decoder, :read_data, :bus_exporter]
 enable :register_block, [:ral_package, :block_model, :constructor, :sub_model_creator, :default_map_creator]
-enable :register      , [:reg_model, :constructor, :field_model_creator, :shadow_index_configurator, :sub_block_model]
+enable :register      , [:reg_model, :constructor, :field_model_creator, :indirect_index_configurator, :sub_block_model]
 enable :bit_field     , :field_model
+enable :register_block, [:c_header_file, :address_struct]

data/setup/default.rb

@@ -1,11 +1,13 @@
 enable :global        , [:data_width, :address_width]
 enable :register_block, [:name, :byte_size]
-enable :register      , [:offset_address, :name, :array, :shadow, :external, :accessibility, :uniquness_validator]
+enable :register      , [:offset_address, :name, :array, :type, :uniquness_validator]
+enable :register      , :type, [:indirect, :external]
 enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
 enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :reserved]
 enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
 enable :register_block, :host_if, [:apb, :axi4lite]
 enable :register      , [:address_decoder, :read_data, :bus_exporter]
 enable :register_block, [:ral_package, :block_model, :constructor, :sub_model_creator, :default_map_creator]
-enable :register      , [:reg_model, :constructor, :field_model_creator, :shadow_index_configurator, :sub_block_model]
+enable :register      , [:reg_model, :constructor, :field_model_creator, :indirect_index_configurator, :sub_block_model]
 enable :bit_field     , :field_model
+enable :register_block, [:c_header_file, :address_struct]