rggen-vhdl 0.1.0

data/lib/rggen/vhdl/register_file/vhdl_top.rb

@@ -0,0 +1,25 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_file, :vhdl_top) do
+  vhdl do
+    include RgGen::SystemVerilog::RTL::RegisterIndex
+
+    main_code :register_file do
+      local_scope("g_#{register_file.name}") do |scope|
+        scope.loop_size loop_size
+        scope.body(&method(:body_code))
+      end
+    end
+
+    private
+
+    def loop_size
+      (register_file.array? || nil) &&
+        local_loop_variables.zip(register_file.array_size).to_h
+    end
+
+    def body_code(code)
+      register_file.generate_code(code, :register_file, :top_down, 1)
+    end
+  end
+end

data/lib/rggen/vhdl/setup.rb

@@ -0,0 +1,11 @@
+# frozen_string_literal: true
+
+require 'rggen/vhdl'
+
+RgGen.register_plugin RgGen::VHDL do |builder|
+  builder.load_plugin 'rggen/systemverilog/rtl/setup'
+  builder.enable :register_block, [:vhdl_top]
+  builder.enable :register_file, [:vhdl_top]
+  builder.enable :register, [:vhdl_top]
+  builder.enable :bit_field, [:vhdl_top]
+end

data/lib/rggen/vhdl/utility.rb

@@ -0,0 +1,28 @@
+# frozen_string_literal: true
+
+module RgGen
+  module VHDL
+    module Utility
+      include Core::Utility::CodeUtility
+
+      private
+
+      def assign(lhs, rhs)
+        "#{lhs} <= #{rhs};"
+      end
+
+      def bin(value, width = nil)
+        width && format("\"%0*b\"", width, value) || "'#{value[0]}'"
+      end
+
+      def hex(value, width)
+        print_width = (width + 3) / 4
+        format("x\"%0*x\"", print_width, value)
+      end
+
+      def local_scope(scope_name, attributes = {}, &block)
+        LocalScope.new(attributes.merge(name: scope_name), &block).to_code
+      end
+    end
+  end
+end

data/lib/rggen/vhdl/utility/data_object.rb

@@ -0,0 +1,91 @@
+# frozen_string_literal: true
+
+module RgGen
+  module VHDL
+    module Utility
+      class DataObject
+        include Core::Utility::AttributeSetter
+
+        def initialize(object_type, default_attributes = {})
+          @object_type = object_type
+          apply_attributes(**default_attributes)
+          block_given? && yield(self)
+        end
+
+        define_attribute :name
+        define_attribute :direction
+        define_attribute :type
+        define_attribute :width
+        define_attribute :array_size
+        define_attribute :default
+
+        def declaration
+          declaration_snippets
+            .compact
+            .reject(&:empty?)
+            .join(' ')
+        end
+
+        def identifier
+          Identifier.new(name) do |identifier|
+            identifier.__width__(width)
+            identifier.__array_size__(array_size)
+          end
+        end
+
+        private
+
+        def declaration_snippets
+          [
+            object_type_keyword,
+            "#{name}:",
+            direction_keyword,
+            type_declaration,
+            default_value
+          ]
+        end
+
+        def object_type_keyword
+          [:signal].include?(@object_type) && @object_type || nil
+        end
+
+        def direction_keyword
+          @object_type == :port && direction || nil
+        end
+
+        def type_declaration
+          if @object_type == :generic && type
+            type
+          else
+            msb = calc_msb
+            msb && "#{default_vector_type}(#{msb} downto 0)" || default_type
+          end
+        end
+
+        def calc_msb
+          width = calc_actual_width
+          width && (width.is_a?(Integer) && width - 1 || "#{width}-1")
+        end
+
+        def calc_actual_width
+          return width if array_size.nil? || array_size.empty?
+          size = [width, *array_size].compact
+          size.all? { |s| s.is_a?(Integer) } && size.inject(:*) || size.join('*')
+        end
+
+        def default_vector_type
+          @object_type == :generic && 'unsigned' || 'std_logic_vector'
+        end
+
+        def default_type
+          @object_type == :generic && 'unsigned' || 'std_logic'
+        end
+
+        def default_value
+          return nil if @object_type != :generic || default.nil?
+          ":= #{default}"
+        end
+      end
+    end
+  end
+end

data/lib/rggen/vhdl/utility/identifier.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+module RgGen
+  module VHDL
+    module Utility
+      class Identifier < SystemVerilog::Common::Utility::Identifier
+        def __create_select__(array_index_or_lsb, lsb_or_width, width)
+          if array_index_or_lsb.is_a?(Array)
+            __array_select__(array_index_or_lsb, lsb_or_width, width)
+          elsif lsb_or_width
+            __array_slice__(array_index_or_lsb, lsb_or_width)
+          else
+            "(#{array_index_or_lsb})"
+          end
+        end
+
+        def __array_select__(array_index, lsb, width)
+          if @width
+            lsb = __serialized_lsb__(array_index, lsb)
+            __array_slice__(lsb, width || @width)
+          else
+            "(#{__serialized_index__(array_index)})"
+          end
+        end
+
+        def __array_slice__(lsb, width)
+          msb =
+            if integer?(width)
+              __reduce_array__([lsb, width - 1], :+, 0)
+            else
+              __reduce_array__([lsb, width, -1], :+, 0)
+            end
+          "(#{msb} downto #{lsb})"
+        end
+      end
+    end
+  end
+end

data/lib/rggen/vhdl/utility/local_scope.rb

@@ -0,0 +1,66 @@
+# frozen_string_literal: true
+
+module RgGen
+  module VHDL
+    module Utility
+      class LocalScope < SystemVerilog::Common::Utility::StructureDefinition
+        define_attribute :name
+        define_attribute :loop_size
+        define_attribute :signals
+
+        private
+
+        def header_code(code)
+          block_header_code(code)
+          generate_for_header(code)
+        end
+
+        def block_header_code(code)
+          code << "#{name}: block" << nl
+          header_begin(code, no_loop?)
+        end
+
+        def no_loop?
+          loop_size.nil? || loop_size.empty?
+        end
+
+        def generate_for_header(code)
+          loop_size&.each_with_index do |(loop_variable, size), i|
+            code.indent += 2
+            generate_for(code, loop_variable, size, i)
+          end
+        end
+
+        def generate_for(code, loop_variable, size, loop_depth)
+          code << "g: for #{loop_variable} in 0 to #{size - 1} generate" << nl
+          header_begin(code, last_loop?(loop_depth))
+        end
+
+        def last_loop?(loop_depth)
+          loop_depth == (loop_size.size - 1)
+        end
+
+        def header_begin(code, include_declarations)
+          signal_declarations(code) if include_declarations
+          code << 'begin' << nl
+        end
+
+        def signal_declarations(code)
+          indent(code, 2) do
+            add_declarations_to_body(code, Array(signals))
+          end
+        end
+
+        def footer_code(code)
+          loop_size&.each { footer(code, 'generate', true) }
+          footer(code, 'block', false)
+        end
+
+        def footer(code, kind, decrease_indent)
+          code << "end #{kind};" << nl
+          code.indent -= 2 if decrease_indent
+        end
+      end
+    end
+  end
+end

data/lib/rggen/vhdl/version.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+module RgGen
+  module VHDL
+    VERSION = '0.1.0'
+  end
+end

metadata

@@ -0,0 +1,130 @@
+--- !ruby/object:Gem::Specification
+name: rggen-vhdl
+version: !ruby/object:Gem::Version
+  version: 0.1.0
+platform: ruby
+authors:
+- Taichi Ishitani
+autorequire: 
+bindir: bin
+cert_chain: []
+date: 2021-05-16 00:00:00.000000000 Z
+dependencies:
+- !ruby/object:Gem::Dependency
+  name: rggen-systemverilog
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 0.25.1
+  type: :runtime
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: 0.25.1
+- !ruby/object:Gem::Dependency
+  name: bundler
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: '0'
+  type: :development
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - ">="
+      - !ruby/object:Gem::Version
+        version: '0'
+description: VHDL writer plugin for RgGen
+email:
+- rggen@googlegroups.com
+executables: []
+extensions: []
+extra_rdoc_files: []
+files:
+- CODE_OF_CONDUCT.md
+- LICENSE
+- README.md
+- lib/rggen/vhdl.rb
+- lib/rggen/vhdl/bit_field/type.rb
+- lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.erb
+- lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.rb
+- lib/rggen/vhdl/bit_field/type/ro.erb
+- lib/rggen/vhdl/bit_field/type/ro.rb
+- lib/rggen/vhdl/bit_field/type/rof.erb
+- lib/rggen/vhdl/bit_field/type/rof.rb
+- lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.erb
+- lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.rb
+- lib/rggen/vhdl/bit_field/type/rw_w1_wo_wo1.erb
+- lib/rggen/vhdl/bit_field/type/rw_w1_wo_wo1.rb
+- lib/rggen/vhdl/bit_field/type/rwc.erb
+- lib/rggen/vhdl/bit_field/type/rwc.rb
+- lib/rggen/vhdl/bit_field/type/rwe_rwl.erb
+- lib/rggen/vhdl/bit_field/type/rwe_rwl.rb
+- lib/rggen/vhdl/bit_field/type/rws.erb
+- lib/rggen/vhdl/bit_field/type/rws.rb
+- lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
+- lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
+- lib/rggen/vhdl/bit_field/type/w0t_w1t.erb
+- lib/rggen/vhdl/bit_field/type/w0t_w1t.rb
+- lib/rggen/vhdl/bit_field/type/w0trg_w1trg.erb
+- lib/rggen/vhdl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/vhdl/bit_field/type/wrc_wrs.erb
+- lib/rggen/vhdl/bit_field/type/wrc_wrs.rb
+- lib/rggen/vhdl/bit_field/vhdl_top.rb
+- lib/rggen/vhdl/component.rb
+- lib/rggen/vhdl/factories.rb
+- lib/rggen/vhdl/feature.rb
+- lib/rggen/vhdl/register/default.erb
+- lib/rggen/vhdl/register/type.rb
+- lib/rggen/vhdl/register/type/default.erb
+- lib/rggen/vhdl/register/type/external.erb
+- lib/rggen/vhdl/register/type/external.rb
+- lib/rggen/vhdl/register/type/indirect.erb
+- lib/rggen/vhdl/register/type/indirect.rb
+- lib/rggen/vhdl/register/vhdl_top.rb
+- lib/rggen/vhdl/register_block/protocol.rb
+- lib/rggen/vhdl/register_block/protocol/apb.erb
+- lib/rggen/vhdl/register_block/protocol/apb.rb
+- lib/rggen/vhdl/register_block/protocol/axi4lite.erb
+- lib/rggen/vhdl/register_block/protocol/axi4lite.rb
+- lib/rggen/vhdl/register_block/vhdl_top.erb
+- lib/rggen/vhdl/register_block/vhdl_top.rb
+- lib/rggen/vhdl/register_file/vhdl_top.rb
+- lib/rggen/vhdl/setup.rb
+- lib/rggen/vhdl/utility.rb
+- lib/rggen/vhdl/utility/data_object.rb
+- lib/rggen/vhdl/utility/identifier.rb
+- lib/rggen/vhdl/utility/local_scope.rb
+- lib/rggen/vhdl/version.rb
+homepage: https://github.com/rggen/rggen-vhdl
+licenses:
+- MIT
+metadata:
+  bug_tracker_uri: https://github.com/rggen/rggen-vhdl/issues
+  mailing_list_uri: https://groups.google.com/d/forum/rggen
+  source_code_uri: https://github.com/rggen/rggen-vhdl
+  wiki_uri: https://github.com/rggen/rggen/wiki
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: 2.5.0
+required_rubygems_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+requirements: []
+rubygems_version: 3.2.3
+signing_key: 
+specification_version: 4
+summary: rggen-vhdl-0.1.0
+test_files: []