rggen-vhdl 0.1.0

data/lib/rggen/vhdl/bit_field/type/w0trg_w1trg.erb

@@ -0,0 +1,17 @@
+u_bit_field: entity work.rggen_bit_field_w01trg
+  generic map (
+    WRITE_ONE_TRIGGER => <%= write_one_trigger? %>,
+    WIDTH             => <%= width %>
+  )
+  port map (
+    i_clk             => i_clk,
+    i_rst_n           => i_rst_n,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    o_trigger         => <%= trigger[loop_variables] %>
+  );

data/lib/rggen/vhdl/bit_field/type/w0trg_w1trg.rb

@@ -0,0 +1,19 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
+  vhdl do
+    build do
+      output :trigger, {
+        name: "o_#{full_name}_trigger", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def write_one_trigger?
+      bit_field.type == :w1trg
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/type/wrc_wrs.erb

@@ -0,0 +1,25 @@
+u_bit_field: entity work.rggen_bit_field
+  generic map (
+    WIDTH           => <%= width %>,
+    INITIAL_VALUE   => <%= initial_value %>,
+    SW_READ_ACTION  => <%= read_action %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_valid        => <%= bit_field_valid %>,
+    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_write_enable => "1",
+    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_hw_write_enable => "0",
+    i_hw_write_data   => (others => '0'),
+    i_hw_set          => (others => '0'),
+    i_hw_clear        => (others => '0'),
+    i_value           => (others => '0'),
+    i_mask            => (others => '1'),
+    o_value           => <%= value_out[loop_variables] %>,
+    o_value_unmasked  => open
+  );

data/lib/rggen/vhdl/bit_field/type/wrc_wrs.rb

@@ -0,0 +1,22 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
+  vhdl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      {
+        wrc: 'RGGEN_READ_CLEAR',
+        wrs: 'RGGEN_READ_SET'
+      }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/vhdl/bit_field/vhdl_top.rb

@@ -0,0 +1,93 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:bit_field, :vhdl_top) do
+  vhdl do
+    include RgGen::SystemVerilog::RTL::BitFieldIndex
+
+    export :initial_value
+    export :value
+
+    build do
+      if parameterized_initial_value?
+        generic :initial_value, {
+          name: initial_value_name, width: initial_value_width,
+          default: default_initial_value
+        }
+      else
+        define_accessor_for_initial_value
+      end
+    end
+
+    main_code :register do
+      local_scope("g_#{bit_field.name}") do |scope|
+        scope.loop_size loop_size
+        scope.body(&method(:body_code))
+      end
+    end
+
+    def value(offsets = nil, width = nil)
+      value_lsb = bit_field.lsb(offsets&.last || local_index)
+      value_width = width || bit_field.width
+      register_value(offsets&.slice(0..-2), value_lsb, value_width)
+    end
+
+    private
+
+    def parameterized_initial_value?
+      bit_field.initial_value? && !bit_field.fixed_initial_value?
+    end
+
+    def initial_value_name
+      "#{bit_field.full_name('_')}_initial_value".upcase
+    end
+
+    def initial_value_width
+      width = bit_field.width
+      repeat_size = bit_field.sequence_size || 1
+      width * repeat_size
+    end
+
+    def default_initial_value
+      width = bit_field.width
+      repeat_size = bit_field.sequence_size || 1
+      value = initial_value_rhs_default
+      "repeat(#{value}, #{width}, #{repeat_size})"
+    end
+
+    def define_accessor_for_initial_value
+      define_singleton_method(:initial_value) do
+        if bit_field.initial_value_array?
+          array_initial_value_rhs
+        elsif bit_field.initial_value?
+          initial_value_rhs_default
+        end
+      end
+    end
+
+    def initial_value_rhs_default
+      hex(bit_field.register_map.initial_value, bit_field.width)
+    end
+
+    def array_initial_value_rhs
+      value =
+        bit_field.initial_values
+          .map.with_index { |v, i| v << bit_field.width * i }
+          .inject(:|)
+      hex(value, bit_field.sequence_size * bit_field.width)
+    end
+
+    def register_value(offsets, lsb, width)
+      index = register.index(offsets || register.local_indices)
+      register_block.register_value[[index], lsb, width]
+    end
+
+    def loop_size
+      loop_variable = local_index
+      loop_variable && { loop_variable => bit_field.sequence_size }
+    end
+
+    def body_code(code)
+      bit_field.generate_code(code, :bit_field, :top_down)
+    end
+  end
+end

data/lib/rggen/vhdl/component.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+module RgGen
+  module VHDL
+    Component = SystemVerilog::Common::Component
+  end
+end

data/lib/rggen/vhdl/factories.rb

@@ -0,0 +1,11 @@
+# frozen_string_literal: true
+
+module RgGen
+  module VHDL
+    class ComponentFactory < Core::OutputBase::SourceFileComponentFactory
+    end
+
+    class FeatureFactory < Core::OutputBase::FeatureFactory
+    end
+  end
+end

data/lib/rggen/vhdl/feature.rb

@@ -0,0 +1,31 @@
+# frozen_string_literal: true
+
+module RgGen
+  module VHDL
+    class Feature < SystemVerilog::Common::Feature
+      include Utility
+
+      private
+
+      def create_signal(_, attributes, &block)
+        DataObject.new(:signal, attributes, &block)
+      end
+
+      def create_port(direction, attributes, &block)
+        attributes =
+          attributes
+            .merge(direction: { input: :in, output: :out}[direction])
+        DataObject.new(:port, attributes, &block)
+      end
+
+      def create_generic(_, attributes, &block)
+        DataObject.new(:generic, attributes, &block)
+      end
+
+      define_entity :signal, :create_signal, :signal, -> { component }
+      define_entity :input, :create_port, :port, -> { register_block }
+      define_entity :output, :create_port, :port, -> { register_block }
+      define_entity :generic, :create_generic, :generic, -> { register_block }
+    end
+  end
+end

data/lib/rggen/vhdl/register/default.erb

@@ -0,0 +1,29 @@
+rggen_default_register #(
+  .READABLE       (<%= readable %>),
+  .WRITABLE       (<%= writable %>),
+  .ADDRESS_WIDTH  (<%= address_width %>),
+  .OFFSET_ADDRESS (<%= offset_address %>),
+  .BUS_WIDTH      (<%= bus_width %>),
+  .DATA_WIDTH     (<%= width %>),
+  .VALID_BITS     (<%= valid_bits %>),
+  .REGISTER_INDEX (<%= register_index %>)
+) u_register (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_register_valid       (<%= register_valid %>),
+  .i_register_access      (<%= register_access %>),
+  .i_register_address     (<%= register_address %>),
+  .i_register_write_data  (<%= register_write_data %>),
+  .i_register_strobe      (<%= register_strobe %>),
+  .o_register_active      (<%= register_active %>),
+  .o_register_ready       (<%= register_ready %>),
+  .o_register_status      (<%= register_status %>),
+  .o_register_read_data   (<%= register_read_data %>),
+  .o_register_value       (<%= register_value %>),
+  .o_bit_field_valid      (<%= bit_field_valid %>),
+  .o_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .o_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .o_bit_field_write_data (<%= bit_field_write_data %>),
+  .i_bit_field_read_data  (<%= bit_field_read_data %>),
+  .i_bit_field_value      (<%= bit_field_value %>)
+);

data/lib/rggen/vhdl/register/type.rb

@@ -0,0 +1,109 @@
+# frozen_string_literal: true
+
+RgGen.define_list_feature(:register, :type) do
+  vhdl do
+    base_feature do
+      include RgGen::SystemVerilog::RTL::RegisterType
+
+      private
+
+      def readable?
+        register.readable?
+      end
+
+      def writable?
+        register.writable?
+      end
+
+      def clock
+        register_block.clock
+      end
+
+      def reset
+        register_block.reset
+      end
+
+      def register_valid
+        register_block.register_valid
+      end
+
+      def register_access
+        register_block.register_access
+      end
+
+      def register_address
+        register_block.register_address
+      end
+
+      def register_write_data
+        register_block.register_write_data
+      end
+
+      def register_strobe
+        register_block.register_strobe
+      end
+
+      def register_active
+        register_block.register_active[[register.index]]
+      end
+
+      def register_ready
+        register_block.register_ready[[register.index]]
+      end
+
+      def register_status
+        register_block.register_status[[register.index]]
+      end
+
+      def register_read_data
+        register_block.register_read_data[[register.index]]
+      end
+
+      def register_value
+        register_block.register_value[[register.index], 0, width]
+      end
+
+      def bit_field_valid
+        register.bit_field_valid
+      end
+
+      def bit_field_read_mask
+        register.bit_field_read_mask
+      end
+
+      def bit_field_write_mask
+        register.bit_field_write_mask
+      end
+
+      def bit_field_write_data
+        register.bit_field_write_data
+      end
+
+      def bit_field_read_data
+        register.bit_field_read_data
+      end
+
+      def bit_field_value
+        register.bit_field_value
+      end
+    end
+
+    default_feature do
+      main_code :register, from_template: File.join(__dir__, 'type', 'default.erb')
+    end
+
+    factory do
+      def target_feature_key(_configuration, register)
+        type = register.type
+        valid_type?(type) && type ||
+          (error "code generator for #{type} register type is not implemented")
+      end
+
+      private
+
+      def valid_type?(type)
+        target_features.key?(type) || type == :default
+      end
+    end
+  end
+end

data/lib/rggen/vhdl/register/type/default.erb

@@ -0,0 +1,31 @@
+u_register: entity work.rggen_default_register
+  generic map (
+    READABLE        => <%= readable? %>,
+    WRITABLE        => <%= writable? %>,
+    ADDRESS_WIDTH   => <%= address_width %>,
+    OFFSET_ADDRESS  => <%= offset_address %>,
+    BUS_WIDTH       => <%= bus_width %>,
+    DATA_WIDTH      => <%= width %>,
+    VALID_BITS      => <%= valid_bits %>,
+    REGISTER_INDEX  => <%= register_index %>
+  )
+  port map (
+    i_clk                   => <%= clock %>,
+    i_rst_n                 => <%= reset %>,
+    i_register_valid        => <%= register_valid %>,
+    i_register_access       => <%= register_access %>,
+    i_register_address      => <%= register_address %>,
+    i_register_write_data   => <%= register_write_data %>,
+    i_register_strobe       => <%= register_strobe %>,
+    o_register_active       => <%= register_active %>,
+    o_register_ready        => <%= register_ready %>,
+    o_register_status       => <%= register_status %>,
+    o_register_read_data    => <%= register_read_data %>,
+    o_register_value        => <%= register_value %>,
+    o_bit_field_valid       => <%= bit_field_valid %>,
+    o_bit_field_read_mask   => <%= bit_field_read_mask %>,
+    o_bit_field_write_mask  => <%= bit_field_write_mask %>,
+    o_bit_field_write_data  => <%= bit_field_write_data %>,
+    i_bit_field_read_data   => <%= bit_field_read_data %>,
+    i_bit_field_value       => <%= bit_field_value %>
+  );

data/lib/rggen/vhdl/register/type/external.erb

@@ -0,0 +1,29 @@
+u_register: entity work.rggen_external_register
+  generic map (
+    ADDRESS_WIDTH => <%= address_width %>,
+    BUS_WIDTH     => <%= bus_width %>,
+    START_ADDRESS => <%= start_address %>,
+    BYTE_SIZE     => <%= byte_size %>
+  )
+  port map (
+    i_clk                 => <%= clock %>,
+    i_rst_n               => <%= reset %>,
+    i_register_valid      => <%= register_valid %>,
+    i_register_access     => <%= register_access %>,
+    i_register_address    => <%= register_address %>,
+    i_register_write_data => <%= register_write_data %>,
+    i_register_strobe     => <%= register_strobe %>,
+    o_register_active     => <%= register_active %>,
+    o_register_ready      => <%= register_ready %>,
+    o_register_status     => <%= register_status %>,
+    o_register_read_data  => <%= register_read_data %>,
+    o_register_value      => <%= register_value %>,
+    o_external_valid      => <%= external_valid %>,
+    o_external_access     => <%= external_access %>,
+    o_external_address    => <%= external_address %>,
+    o_external_data       => <%= external_write_data %>,
+    o_external_strobe     => <%= external_strobe %>,
+    i_external_ready      => <%= external_ready %>,
+    i_external_status     => <%= external_status %>,
+    i_external_data       => <%= external_read_data %>
+  );

data/lib/rggen/vhdl/register/type/external.rb

@@ -0,0 +1,44 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :external) do
+  vhdl do
+    build do
+      output :external_valid, {
+        name: "o_#{register.name}_valid"
+      }
+      output :external_access, {
+        name: "o_#{register.name}_access", width: 2
+      }
+      output :external_address, {
+        name: "o_#{register.name}_address", width: address_width
+      }
+      output :external_write_data, {
+        name: "o_#{register.name}_data", width: bus_width
+      }
+      output :external_strobe, {
+        name: "o_#{register.name}_strobe", width: bus_width / 8
+      }
+      input :external_ready, {
+        name: "i_#{register.name}_ready"
+      }
+      input :external_status, {
+        name: "i_#{register.name}_status", width: 2
+      }
+      input :external_read_data, {
+        name: "i_#{register.name}_data", width: bus_width
+      }
+    end
+
+    main_code :register, from_template: true
+
+    private
+
+    def start_address
+      hex(register.offset_address, address_width)
+    end
+
+    def byte_size
+      register.byte_size
+    end
+  end
+end