rggen-vhdl 0.1.0

data/lib/rggen/vhdl/register/type/indirect.erb

@@ -0,0 +1,35 @@
+<% index_fields_and_values.each_with_index do |(field, value), i| %>
+<%= indirect_match[i] %> <= '1' when unsigned(<%= field %>) = <%= value %> else '0';
+<% end %>
+u_register: entity work.rggen_indirect_register
+  generic map (
+    READABLE              => <%= readable? %>,
+    WRITABLE              => <%= writable? %>,
+    ADDRESS_WIDTH         => <%= address_width %>,
+    OFFSET_ADDRESS        => <%= offset_address %>,
+    BUS_WIDTH             => <%= bus_width %>,
+    DATA_WIDTH            => <%= width %>,
+    VALID_BITS            => <%= valid_bits %>,
+    INDIRECT_MATCH_WIDTH  => <%= match_width %>
+  )
+  port map (
+    i_clk                   => <%= clock %>,
+    i_rst_n                 => <%= reset %>,
+    i_register_valid        => <%= register_valid %>,
+    i_register_access       => <%= register_access %>,
+    i_register_address      => <%= register_address %>,
+    i_register_write_data   => <%= register_write_data %>,
+    i_register_strobe       => <%= register_strobe %>,
+    o_register_active       => <%= register_active %>,
+    o_register_ready        => <%= register_ready %>,
+    o_register_status       => <%= register_status %>,
+    o_register_read_data    => <%= register_read_data %>,
+    o_register_value        => <%= register_value %>,
+    i_indirect_match        => <%= indirect_match %>,
+    o_bit_field_valid       => <%= bit_field_valid %>,
+    o_bit_field_read_mask   => <%= bit_field_read_mask %>,
+    o_bit_field_write_mask  => <%= bit_field_write_mask %>,
+    o_bit_field_write_data  => <%= bit_field_write_data %>,
+    i_bit_field_read_data   => <%= bit_field_read_data %>,
+    i_bit_field_value       => <%= bit_field_value %>
+  );

data/lib/rggen/vhdl/register/type/indirect.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :indirect) do
+  vhdl do
+    build do
+      signal :indirect_match, {  width: match_width }
+    end
+
+    main_code :register, from_template: true
+
+    private
+
+    def match_width
+      register.index_entries.size
+    end
+
+    def index_fields
+      register
+        .collect_index_fields(register_block.bit_fields)
+        .map(&:value)
+    end
+
+    def index_values
+      loop_variables = register.local_loop_variables
+      register.index_entries.map do |entry|
+        entry.array_index? && loop_variables.shift || entry.value
+      end
+    end
+
+    def index_fields_and_values
+      index_fields.zip(index_values)
+    end
+  end
+end

data/lib/rggen/vhdl/register/vhdl_top.rb

@@ -0,0 +1,40 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register, :vhdl_top) do
+  vhdl do
+    include RgGen::SystemVerilog::RTL::RegisterIndex
+
+    build do
+      unless register.bit_fields.empty?
+        signal :bit_field_valid
+        signal :bit_field_read_mask, width: register.width
+        signal :bit_field_write_mask, width: register.width
+        signal :bit_field_write_data, width: register.width
+        signal :bit_field_read_data, width: register.width
+        signal :bit_field_value, width: register.width
+      end
+    end
+
+    main_code :register_file do
+      local_scope("g_#{register.name}") do |scope|
+        scope.loop_size loop_size
+        scope.signals signals
+        scope.body(&method(:body_code))
+      end
+    end
+
+    private
+
+    def loop_size
+      register.array? && local_loop_variables.zip(register.array_size) || nil
+    end
+
+    def signals
+      register.declarations[:signal]
+    end
+
+    def body_code(code)
+      register.generate_code(code, :register, :top_down)
+    end
+  end
+end

data/lib/rggen/vhdl/register_block/protocol.rb

@@ -0,0 +1,48 @@
+# frozen_string_literal: true
+
+RgGen.define_list_feature(:register_block, :protocol) do
+  vhdl do
+    shared_context.feature_registry(registry)
+
+    base_feature do
+      build do
+        generic :address_width, {
+          name: 'ADDRESS_WIDTH', type: :positive, default: local_address_width
+        }
+        generic :pre_decode, {
+          name: 'PRE_DECODE', type: :boolean, default: false
+        }
+        generic :base_address, {
+          name: 'BASE_ADDRESS', default: hex(0, 4)
+        }
+        generic :error_status, {
+          name: 'ERROR_STATUS', type: :boolean, default: false
+        }
+      end
+
+      private
+
+      def bus_width
+        configuration.bus_width
+      end
+
+      def local_address_width
+        register_block.local_address_width
+      end
+
+      def total_registers
+        register_block.files_and_registers.sum(&:count)
+      end
+
+      def byte_size
+        register_block.byte_size
+      end
+    end
+
+    factory do
+      def target_feature_key(configuration, _register_block)
+        configuration.protocol
+      end
+    end
+  end
+end

data/lib/rggen/vhdl/register_block/protocol/apb.erb

@@ -0,0 +1,34 @@
+u_adapter: entity work.rggen_apb_adaper
+  generic map (
+    ADDRESS_WIDTH       => <%= address_width %>,
+    LOCAL_ADDRESS_WIDTH => <%= local_address_width %>,
+    BUS_WIDTH           => <%= bus_width %>,
+    REGISTERS           => <%= total_registers %>,
+    PRE_DECODE          => <%= pre_decode %>,
+    BASE_ADDRESS        => <%= base_address %>,
+    BYTE_SIZE           => <%= byte_size %>,
+    ERROR_STATUS        => <%= error_status %>
+  )
+  port map (
+    i_clk                 => <%= register_block.clock %>,
+    i_rst_n               => <%= register_block.reset %>,
+    i_psel                => <%= psel %>,
+    i_penable             => <%= penable %>,
+    i_paddr               => <%= paddr %>,
+    i_pprot               => <%= pprot %>,
+    i_pwrite              => <%= pwrite %>,
+    i_pstrb               => <%= pstrb %>,
+    i_pwdata              => <%= pwdata %>,
+    o_pready              => <%= pready %>,
+    o_prdata              => <%= prdata %>,
+    o_pslverr             => <%= pslverr %>,
+    o_register_valid      => <%= register_block.register_valid %>,
+    o_register_access     => <%= register_block.register_access %>,
+    o_register_address    => <%= register_block.register_address %>,
+    o_register_write_data => <%= register_block.register_write_data %>,
+    o_register_strobe     => <%= register_block.register_strobe %>,
+    i_register_active     => <%= register_block.register_active %>,
+    i_register_ready      => <%= register_block.register_ready %>,
+    i_register_status     => <%= register_block.register_status %>,
+    i_register_read_data  => <%= register_block.register_read_data %>
+  );

data/lib/rggen/vhdl/register_block/protocol/apb.rb

@@ -0,0 +1,20 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
+  vhdl do
+    build do
+      input :psel, { name: 'i_psel' }
+      input :penable, { name: 'i_penable' }
+      input :paddr, { name: 'i_paddr', width: address_width }
+      input :pprot, { name: 'i_pprot', width: 3 }
+      input :pwrite, { name: 'i_pwrite' }
+      input :pstrb, { name: 'i_pstrb', width: bus_width / 8 }
+      input :pwdata, { name: 'i_pwdata', width: bus_width }
+      output :pready, { name: 'o_pready' }
+      output :prdata, { name: 'o_prdata', width: bus_width }
+      output :pslverr, { name: 'o_pslverr' }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/vhdl/register_block/protocol/axi4lite.erb

@@ -0,0 +1,49 @@
+u_adapter: entity work.rggen_axi4lite_adapter
+  generic map (
+    ID_WIDTH            => <%= id_width %>,
+    ADDRESS_WIDTH       => <%= address_width %>,
+    LOCAL_ADDRESS_WIDTH => <%= local_address_width %>,
+    BUS_WIDTH           => <%= bus_width %>,
+    REGISTERS           => <%= total_registers %>,
+    PRE_DECODE          => <%= pre_decode %>,
+    BASE_ADDRESS        => <%= base_address %>,
+    BYTE_SIZE           => <%= byte_size %>,
+    ERROR_STATUS        => <%= error_status %>,
+    WRITE_FIRST         => <%= write_first %>
+  )
+  port map (
+    i_clk                 => <%= register_block.clock %>,
+    i_rst_n               => <%= register_block.reset %>,
+    i_awvalid             => <%= awvalid %>,
+    o_awready             => <%= awready %>,
+    i_awid                => <%= awid %>,
+    i_awaddr              => <%= awaddr %>,
+    i_awprot              => <%= awprot %>,
+    i_wvalid              => <%= wvalid %>,
+    o_wready              => <%= wready %>,
+    i_wdata               => <%= wdata %>,
+    i_wstrb               => <%= wstrb %>,
+    o_bvalid              => <%= bvalid %>,
+    i_bready              => <%= bready %>,
+    o_bid                 => <%= bid %>,
+    o_bresp               => <%= bresp %>,
+    i_arvalid             => <%= arvalid %>,
+    o_arready             => <%= arready %>,
+    i_arid                => <%= arid %>,
+    i_araddr              => <%= araddr %>,
+    i_arprot              => <%= arprot %>,
+    o_rvalid              => <%= rvalid %>,
+    i_rready              => <%= rready %>,
+    o_rid                 => <%= rid %>,
+    o_rdata               => <%= rdata %>,
+    o_rresp               => <%= rresp %>,
+    o_register_valid      => <%= register_block.register_valid %>,
+    o_register_access     => <%= register_block.register_access %>,
+    o_register_address    => <%= register_block.register_address %>,
+    o_register_write_data => <%= register_block.register_write_data %>,
+    o_register_strobe     => <%= register_block.register_strobe %>,
+    i_register_active     => <%= register_block.register_active %>,
+    i_register_ready      => <%= register_block.register_ready %>,
+    i_register_status     => <%= register_block.register_status %>,
+    i_register_read_data  => <%= register_block.register_read_data %>
+  );

data/lib/rggen/vhdl/register_block/protocol/axi4lite.rb

@@ -0,0 +1,42 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
+  vhdl do
+    build do
+      generic :id_width, { name: 'ID_WIDTH', type: :natural, default: 0 }
+      generic :write_first, { name: 'WRITE_FIRST', type: :boolean, default: true }
+
+      input :awvalid, { name: 'i_awvalid' }
+      output :awready, { name: 'o_awready' }
+      input :awid, { name: 'i_awid', width: id_width_value }
+      input :awaddr, { name: 'i_awaddr', width: address_width }
+      input :awprot, { name: 'i_awprot', width: 3 }
+      input :wvalid, { name: 'i_wvalid' }
+      output :wready, { name: 'o_wready' }
+      input :wdata, { name: 'i_wdata', width: bus_width }
+      input :wstrb, { name: 'i_wstrb', width: bus_width / 8 }
+      output :bvalid, { name: 'o_bvalid' }
+      input :bready, { name: 'i_bready' }
+      output :bid, { name: 'o_bid', width: id_width_value }
+      output :bresp, { name: 'o_bresp', width: 2 }
+      input :arvalid, { name: 'i_arvalid' }
+      output :arready, { name: 'o_arready' }
+      input :arid, { name: 'i_arid', width: id_width_value }
+      input :araddr, { name: 'i_araddr', width: address_width }
+      input :arprot, { name: 'i_arprot', width: 3 }
+      output :rvalid, { name: 'o_rvalid' }
+      input :rready, { name: 'i_rready' }
+      output :rid, { name: 'o_rid', width: id_width_value }
+      output :rdata, { name: 'o_rdata', width: bus_width }
+      output :rresp, { name: 'o_rresp', width: 2 }
+    end
+
+    main_code :register_block, from_template: true
+
+    private
+
+    def id_width_value
+      "clip_id_width(#{id_width})"
+    end
+  end
+end

data/lib/rggen/vhdl/register_block/vhdl_top.erb

@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.rggen_rtl.all;
+
+entity <%= register_block.name %> is
+  generic (
+<% generic_declarations.each do |declaration| %>
+    <%= declaration %>
+<% end %>
+  );
+  port (
+<% port_declarations.each do |declaration| %>
+    <%= declaration %>
+<% end %>
+  );
+end <%= register_block.name %>;
+
+architecture rtl of <%= register_block.name %> is
+<% signal_declarations.each do |declaration| %>
+  <%= declaration %>;
+<% end %>
+begin
+<%= architecture_body_code.to_s.chomp %>
+end rtl;

data/lib/rggen/vhdl/register_block/vhdl_top.rb

@@ -0,0 +1,103 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :vhdl_top) do
+  vhdl do
+    build do
+      input :clock, { name: 'i_clk' }
+      input :reset, { name: 'i_rst_n' }
+
+      signal :register_valid
+      signal :register_access, {
+        width: 2
+      }
+      signal :register_address, {
+        width: address_width
+      }
+      signal :register_write_data, {
+        width: bus_width
+      }
+      signal :register_strobe, {
+        width: bus_width / 8
+      }
+      signal :register_active, {
+        array_size: [total_registers]
+      }
+      signal :register_ready, {
+        array_size: [total_registers]
+      }
+      signal :register_status, {
+        width: 2, array_size: [total_registers]
+      }
+      signal :register_read_data, {
+        width: bus_width, array_size: [total_registers]
+      }
+      signal :register_value, {
+        width: value_width, array_size: [total_registers]
+      }
+    end
+
+    write_file '<%= register_block.name %>.vhd' do |file|
+      file.body { process_template }
+    end
+
+    private
+
+    def total_registers
+      register_block.files_and_registers.sum(&:count)
+    end
+
+    def address_width
+      register_block.local_address_width
+    end
+
+    def bus_width
+      configuration.bus_width
+    end
+
+    def value_width
+      register_block.registers.map(&:width).max
+    end
+
+    def generic_declarations
+      register_block
+        .declarations[:generic]
+        .yield_self(&method(:add_terminator))
+    end
+
+    def port_declarations
+      register_block
+        .declarations[:port]
+        .yield_self(&method(:sort_port_declarations))
+        .yield_self(&method(:add_terminator))
+    end
+
+    def signal_declarations
+      register_block.declarations[:signal]
+    end
+
+    def architecture_body_code
+      code_block(2) do |code|
+        register_block.generate_code(code, :register_block, :top_down)
+        register_block.generate_code(code, :register_file, :top_down, 1)
+      end
+    end
+
+    def sort_port_declarations(declarations)
+      declarations
+        .partition(&method(:clock_or_reset?))
+        .flatten
+    end
+
+    def clock_or_reset?(declaration)
+      [clock.to_s, reset.to_s]
+        .any? { |port_name| declaration.include?(port_name) }
+    end
+
+    def add_terminator(declarations)
+      declarations.map.with_index do |declaration, i|
+        (i == declarations.size - 1) && declaration ||
+          declaration + semicolon
+      end
+    end
+  end
+end